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synced 2024-12-19 10:53:58 +00:00
Implement EDMA RX for AR93xx and later chips.
This is inspired by ath9k and the reference driver, but it's a new implementation of the RX FIFO handling. This has some issues - notably the FIFO needs to be reprogrammed when the chip is reset.
This commit is contained in:
Adrian Chadd
parent
d434a377d9
commit
99e8d8c3bb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=238317
@ -117,6 +117,38 @@ __FBSDID("$FreeBSD$");
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#include <dev/ath/if_ath_rx_edma.h>
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/*
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* some general macros
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*/
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#define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
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#define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
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MALLOC_DECLARE(M_ATHDEV);
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/*
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* XXX TODO:
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*
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* + Add an RX lock, just to ensure we don't have things clash;
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* + Make sure the FIFO is correctly flushed and reinitialised
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* through a reset;
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* + Handle the "kickpcu" state where the FIFO overflows.
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* + Implement a "flush" routine, which doesn't push any
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* new frames into the FIFO.
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* + Verify multi-descriptor frames work!
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* + There's a "memory use after free" which needs to be tracked down
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* and fixed ASAP. I've seen this in the legacy path too, so it
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* may be a generic RX path issue.
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*/
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/*
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* XXX shuffle the function orders so these pre-declarations aren't
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* required!
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*/
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static int ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype,
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int nbufs);
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static int ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype);
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static void ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf);
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static void
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ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
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{
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@ -128,25 +160,51 @@ ath_edma_stoprecv(struct ath_softc *sc, int dodelay)
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DELAY(3000);
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if (sc->sc_rxpending != NULL) {
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m_freem(sc->sc_rxpending);
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sc->sc_rxpending = NULL;
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/* Flush RX pending for each queue */
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/* XXX should generic-ify this */
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if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending) {
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m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending);
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sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL;
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}
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sc->sc_rxlink = NULL;
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if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending) {
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m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending);
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sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL;
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}
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}
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/*
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* Start receive.
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*
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* XXX TODO: this needs to reallocate the FIFO entries when a reset
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* occurs, in case the FIFO is filled up and no new descriptors get
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* thrown into the FIFO.
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*/
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static int
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ath_edma_startrecv(struct ath_softc *sc)
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{
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struct ath_hal *ah = sc->sc_ah;
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sc->sc_rxlink = NULL;
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sc->sc_rxpending = NULL;
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/* Enable RX FIFO */
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ath_hal_rxena(ah);
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/*
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* XXX write out a complete set of FIFO entries based on
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* what's currently available.
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*/
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/* Add up to m_fifolen entries in each queue */
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/*
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* These must occur after the above write so the FIFO buffers
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* are pushed/tracked in the same order as the hardware will
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* process them.
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*/
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ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_HP,
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sc->sc_rxedma[HAL_RX_QUEUE_HP].m_fifolen);
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ath_edma_rxfifo_alloc(sc, HAL_RX_QUEUE_LP,
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sc->sc_rxedma[HAL_RX_QUEUE_LP].m_fifolen);
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/* XXX setup HP RX queue FIFO pointer */
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/* XXX setup LP RX queue FIFO pointer */
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/* XXX ath_hal_rxena() */
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ath_mode_init(sc);
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ath_hal_startpcurecv(ah);
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return (0);
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@ -157,6 +215,113 @@ ath_edma_recv_flush(struct ath_softc *sc)
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{
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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/*
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* XXX for now, free all descriptors. Later on, complete
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* what can be completed!
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*/
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#if 0
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ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
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ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
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#endif
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}
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/*
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* Process frames from the current queue.
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*
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* TODO:
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*
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* + Add a "dosched" flag, so we don't reschedule any FIFO frames
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* to the hardware or re-kick the PCU after 'kickpcu' is set.
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*
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* + Perhaps split "check FIFO contents" and "handle frames", so
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* we can run the "check FIFO contents" in ath_intr(), but
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* "handle frames" in the RX tasklet.
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*/
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static int
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ath_edma_recv_proc_queue(struct ath_softc *sc, HAL_RX_QUEUE qtype)
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{
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struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
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struct ath_rx_status *rs;
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struct ath_desc *ds;
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struct ath_buf *bf;
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int n = 0;
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struct mbuf *m;
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HAL_STATUS status;
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struct ath_hal *ah = sc->sc_ah;
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uint64_t tsf;
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int16_t nf;
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tsf = ath_hal_gettsf64(ah);
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nf = ath_hal_getchannoise(ah, sc->sc_curchan);
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sc->sc_stats.ast_rx_noise = nf;
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do {
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bf = re->m_fifo[re->m_fifo_head];
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/* This shouldn't occur! */
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if (bf == NULL) {
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device_printf(sc->sc_dev, "%s: Q%d: NULL bf?\n",
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__func__,
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qtype);
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break;
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}
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m = bf->bf_m;
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ds = bf->bf_desc;
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/*
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* Sync descriptor memory - this also syncs the buffer for us.
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*
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* EDMA descriptors are in cached memory.
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*/
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bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
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BUS_DMASYNC_POSTREAD);
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rs = &bf->bf_status.ds_rxstat;
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status = ath_hal_rxprocdesc(ah, ds, bf->bf_daddr, NULL, rs);
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
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ath_printrxbuf(sc, bf, 0, status == HAL_OK);
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#endif
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if (status == HAL_EINPROGRESS)
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break;
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/*
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* Completed descriptor.
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*
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* In the future we'll call ath_rx_pkt(), but it first
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* has to be taught about EDMA RX queues (so it can
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* access sc_rxpending correctly.)
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*/
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DPRINTF(sc, ATH_DEBUG_EDMA_RX,
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"%s: Q%d: completed!\n", __func__, qtype);
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/*
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* Remove the FIFO entry!
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*/
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re->m_fifo[re->m_fifo_head] = NULL;
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/*
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* Skip the RX descriptor status - start at the data offset
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*/
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m_adj(m, sc->sc_rx_statuslen);
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/* Handle the frame */
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(void) ath_rx_pkt(sc, rs, status, tsf, nf, qtype, bf);
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/* Free the buffer/mbuf */
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ath_edma_rxbuf_free(sc, bf);
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/* Bump the descriptor FIFO stats */
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INCR(re->m_fifo_head, re->m_fifolen);
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re->m_fifo_depth--;
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/* XXX check it doesn't fall below 0 */
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} while (re->m_fifo_depth > 0);
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/* Handle resched and kickpcu appropriately */
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/* Append some more fresh frames to the FIFO */
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ath_edma_rxfifo_alloc(sc, qtype, re->m_fifolen);
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return (n);
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}
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static void
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@ -164,18 +329,326 @@ ath_edma_recv_tasklet(void *arg, int npending)
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{
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struct ath_softc *sc = (struct ath_softc *) arg;
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device_printf(sc->sc_dev, "%s: called; npending=%d\n",
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DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: called; npending=%d\n",
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__func__,
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npending);
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/* XXX TODO */
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ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_HP);
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ath_edma_recv_proc_queue(sc, HAL_RX_QUEUE_LP);
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}
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/*
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* Allocate an RX mbuf for the given ath_buf and initialise
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* it for EDMA.
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*
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* + Allocate a 4KB mbuf;
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* + Setup the DMA map for the given buffer;
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* + Keep a pointer to the start of the mbuf - that's where the
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* descriptor lies;
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* + Take a pointer to the start of the RX buffer, set the
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* mbuf "start" to be there;
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* + Return that.
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*/
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static int
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ath_edma_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
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{
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device_printf(sc->sc_dev, "%s: called; bf=%p\n", __func__, bf);
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return (EIO);
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struct mbuf *m;
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int error;
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int len;
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// device_printf(sc->sc_dev, "%s: called; bf=%p\n", __func__, bf);
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m = m_getm(NULL, sc->sc_edma_bufsize, M_DONTWAIT, MT_DATA);
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if (! m)
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return (ENOBUFS); /* XXX ?*/
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/* XXX warn/enforce alignment */
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len = m->m_ext.ext_size;
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#if 0
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device_printf(sc->sc_dev, "%s: called: m=%p, size=%d, mtod=%p\n",
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__func__,
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m,
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len,
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mtod(m, char *));
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#endif
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m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
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/*
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* Create DMA mapping.
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*/
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error = bus_dmamap_load_mbuf_sg(sc->sc_dmat,
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bf->bf_dmamap, m, bf->bf_segs, &bf->bf_nseg, BUS_DMA_NOWAIT);
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if (error != 0) {
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device_printf(sc->sc_dev, "%s: failed; error=%d\n",
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__func__,
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error);
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m_freem(m);
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return (error);
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}
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/*
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* Populate ath_buf fields.
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*/
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bf->bf_desc = mtod(m, struct ath_desc *);
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bf->bf_daddr = bf->bf_segs[0].ds_addr;
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bf->bf_lastds = bf->bf_desc; /* XXX only really for TX? */
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bf->bf_m = m;
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/* Zero the descriptor */
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memset(bf->bf_desc, '\0', sc->sc_rx_statuslen);
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#if 0
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/*
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* Adjust mbuf header and length/size to compensate for the
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* descriptor size.
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*/
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m_adj(m, sc->sc_rx_statuslen);
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#endif
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/* Finish! */
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return (0);
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}
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static struct ath_buf *
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ath_edma_rxbuf_alloc(struct ath_softc *sc)
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{
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struct ath_buf *bf;
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int error;
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/* Allocate buffer */
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bf = TAILQ_FIRST(&sc->sc_rxbuf);
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/* XXX shouldn't happen upon startup? */
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if (bf == NULL)
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return (NULL);
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/* Remove it from the free list */
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TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list);
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/* Assign RX mbuf to it */
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error = ath_edma_rxbuf_init(sc, bf);
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if (error != 0) {
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device_printf(sc->sc_dev,
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"%s: bf=%p, rxbuf alloc failed! error=%d\n",
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__func__,
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bf,
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error);
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TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
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return (NULL);
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}
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return (bf);
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}
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static void
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ath_edma_rxbuf_free(struct ath_softc *sc, struct ath_buf *bf)
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{
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bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap);
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if (bf->bf_m) {
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m_freem(bf->bf_m);
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bf->bf_m = NULL;
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}
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/* XXX lock? */
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TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list);
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}
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/*
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* Allocate up to 'n' entries and push them onto the hardware FIFO.
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*
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* Return how many entries were successfully pushed onto the
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* FIFO.
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*/
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static int
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ath_edma_rxfifo_alloc(struct ath_softc *sc, HAL_RX_QUEUE qtype, int nbufs)
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{
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struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
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struct ath_buf *bf;
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int i;
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/*
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* Allocate buffers until the FIFO is full or nbufs is reached.
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*/
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for (i = 0; i < nbufs && re->m_fifo_depth < re->m_fifolen; i++) {
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/* Ensure the FIFO is already blank, complain loudly! */
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if (re->m_fifo[re->m_fifo_tail] != NULL) {
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device_printf(sc->sc_dev,
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"%s: Q%d: fifo[%d] != NULL (%p)\n",
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__func__,
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qtype,
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re->m_fifo_tail,
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re->m_fifo[re->m_fifo_tail]);
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/* Free the slot */
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ath_edma_rxbuf_free(sc, re->m_fifo[re->m_fifo_tail]);
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re->m_fifo_depth--;
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/* XXX check it's not < 0 */
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re->m_fifo[re->m_fifo_tail] = NULL;
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}
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bf = ath_edma_rxbuf_alloc(sc);
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/* XXX should ensure the FIFO is not NULL? */
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if (bf == NULL) {
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device_printf(sc->sc_dev, "%s: Q%d: alloc failed?\n",
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__func__,
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qtype);
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break;
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}
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re->m_fifo[re->m_fifo_tail] = bf;
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/*
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* Flush the descriptor contents before it's handed to the
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* hardware.
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*/
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bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap,
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BUS_DMASYNC_PREREAD);
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/* Write to the RX FIFO */
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DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: putrxbuf=%p\n",
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__func__,
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qtype,
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bf->bf_desc);
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ath_hal_putrxbuf(sc->sc_ah, bf->bf_daddr, qtype);
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re->m_fifo_depth++;
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INCR(re->m_fifo_tail, re->m_fifolen);
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}
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/*
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* Return how many were allocated.
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*/
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DPRINTF(sc, ATH_DEBUG_EDMA_RX, "%s: Q%d: nbufs=%d, nalloced=%d\n",
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__func__,
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qtype,
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nbufs,
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i);
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return (i);
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}
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static int
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ath_edma_rxfifo_flush(struct ath_softc *sc, HAL_RX_QUEUE qtype)
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{
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struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
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int i;
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for (i = 0; i < re->m_fifolen; i++) {
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if (re->m_fifo[i] != NULL) {
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struct ath_buf *bf = re->m_fifo[i];
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#ifdef ATH_DEBUG
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if (sc->sc_debug & ATH_DEBUG_RECV_DESC)
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ath_printrxbuf(sc, bf, 0, HAL_OK);
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#endif
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ath_edma_rxbuf_free(sc, re->m_fifo[i]);
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re->m_fifo[i] = NULL;
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re->m_fifo_depth--;
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}
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}
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if (re->m_rxpending != NULL) {
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m_freem(re->m_rxpending);
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re->m_rxpending = NULL;
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}
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re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
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return (0);
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}
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/*
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* Setup the initial RX FIFO structure.
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*/
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static int
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ath_edma_setup_rxfifo(struct ath_softc *sc, HAL_RX_QUEUE qtype)
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{
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struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
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if (! ath_hal_getrxfifodepth(sc->sc_ah, qtype, &re->m_fifolen)) {
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device_printf(sc->sc_dev, "%s: qtype=%d, failed\n",
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__func__,
|
||||
qtype);
|
||||
return (-EINVAL);
|
||||
}
|
||||
device_printf(sc->sc_dev, "%s: type=%d, FIFO depth = %d entries\n",
|
||||
__func__,
|
||||
qtype,
|
||||
re->m_fifolen);
|
||||
|
||||
/* Allocate ath_buf FIFO array, pre-zero'ed */
|
||||
re->m_fifo = malloc(sizeof(struct ath_buf *) * re->m_fifolen,
|
||||
M_ATHDEV,
|
||||
M_NOWAIT | M_ZERO);
|
||||
if (re->m_fifo == NULL) {
|
||||
device_printf(sc->sc_dev, "%s: malloc failed\n",
|
||||
__func__);
|
||||
return (-ENOMEM);
|
||||
}
|
||||
|
||||
/*
|
||||
* Set initial "empty" state.
|
||||
*/
|
||||
re->m_rxpending = NULL;
|
||||
re->m_fifo_head = re->m_fifo_tail = re->m_fifo_depth = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ath_edma_rxfifo_free(struct ath_softc *sc, HAL_RX_QUEUE qtype)
|
||||
{
|
||||
struct ath_rx_edma *re = &sc->sc_rxedma[qtype];
|
||||
|
||||
device_printf(sc->sc_dev, "%s: called; qtype=%d\n",
|
||||
__func__,
|
||||
qtype);
|
||||
|
||||
free(re->m_fifo, M_ATHDEV);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ath_edma_dma_rxsetup(struct ath_softc *sc)
|
||||
{
|
||||
int error;
|
||||
|
||||
/* Create RX DMA tag */
|
||||
/* Create RX ath_buf array */
|
||||
|
||||
error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf,
|
||||
"rx", ath_rxbuf, 1);
|
||||
if (error != 0)
|
||||
return error;
|
||||
|
||||
(void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_HP);
|
||||
(void) ath_edma_setup_rxfifo(sc, HAL_RX_QUEUE_LP);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ath_edma_dma_rxteardown(struct ath_softc *sc)
|
||||
{
|
||||
|
||||
device_printf(sc->sc_dev, "%s: called\n", __func__);
|
||||
|
||||
ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_HP);
|
||||
ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_HP);
|
||||
|
||||
ath_edma_rxfifo_flush(sc, HAL_RX_QUEUE_LP);
|
||||
ath_edma_rxfifo_free(sc, HAL_RX_QUEUE_LP);
|
||||
|
||||
/* Free RX ath_buf */
|
||||
/* Free RX DMA tag */
|
||||
if (sc->sc_rxdma.dd_desc_len != 0)
|
||||
ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
@ -184,9 +657,35 @@ ath_recv_setup_edma(struct ath_softc *sc)
|
||||
|
||||
device_printf(sc->sc_dev, "DMA setup: EDMA\n");
|
||||
|
||||
/* Set buffer size to 4k */
|
||||
sc->sc_edma_bufsize = 4096;
|
||||
|
||||
/* Configure the hardware with this */
|
||||
(void) ath_hal_setrxbufsize(sc->sc_ah, sc->sc_edma_bufsize);
|
||||
|
||||
/* Fetch EDMA field and buffer sizes */
|
||||
(void) ath_hal_getrxstatuslen(sc->sc_ah, &sc->sc_rx_statuslen);
|
||||
(void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen);
|
||||
(void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen);
|
||||
(void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps);
|
||||
|
||||
device_printf(sc->sc_dev, "RX status length: %d\n",
|
||||
sc->sc_rx_statuslen);
|
||||
device_printf(sc->sc_dev, "TX descriptor length: %d\n",
|
||||
sc->sc_tx_desclen);
|
||||
device_printf(sc->sc_dev, "TX status length: %d\n",
|
||||
sc->sc_tx_statuslen);
|
||||
device_printf(sc->sc_dev, "TX/RX buffer size: %d\n",
|
||||
sc->sc_edma_bufsize);
|
||||
device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n",
|
||||
sc->sc_tx_nmaps);
|
||||
|
||||
sc->sc_rx.recv_stop = ath_edma_stoprecv;
|
||||
sc->sc_rx.recv_start = ath_edma_startrecv;
|
||||
sc->sc_rx.recv_flush = ath_edma_recv_flush;
|
||||
sc->sc_rx.recv_tasklet = ath_edma_recv_tasklet;
|
||||
sc->sc_rx.recv_rxbuf_init = ath_edma_rxbuf_init;
|
||||
|
||||
sc->sc_rx.recv_setup = ath_edma_dma_rxsetup;
|
||||
sc->sc_rx.recv_teardown = ath_edma_dma_rxteardown;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user