mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-18 10:35:55 +00:00
Remove unused stuff from cpu.h.
Move inappropriate stuff in cpu.h elsewhere:
{s,g}et_intr_mask -> md_var.h
num_tlbentries -> tlb.h
Remove #define clockframe trapframe and fix clock, which was the only place
this was used.
All the rest of this stuff was unused.
# we're not quite minimal yet, since we duplicate a few status register things
# here...
Inspired by: bde@
This commit is contained in:
Warner Losh
parent
fde8aa4e5c
commit
9d1f4f86c5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=210100
@ -17,7 +17,7 @@
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extern int cpu_clock;
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extern uint32_t clockintr(uint32_t, struct clockframe *);
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extern uint32_t clockintr(uint32_t, struct trapframe *);
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#define wall_cmos_clock 0
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#define adjkerntz 0
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@ -83,175 +83,34 @@
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* Exported definitions unique to mips cpu support.
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*/
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#define cpu_swapout(p) panic("cpu_swapout: can't get here");
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#ifndef _LOCORE
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#include <machine/cpufunc.h>
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#include <machine/frame.h>
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/*
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* Arguments to hardclock and gatherstats encapsulate the previous
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* machine state in an opaque clockframe.
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*/
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#define clockframe trapframe /* Use normal trap frame */
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#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
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#define CLKF_PC(framep) ((framep)->pc)
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#define CLKF_INTR(framep) (0)
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#define MIPS_CLKF_INTR() (intr_nesting_level >= 1)
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#define TRAPF_USERMODE(framep) (((framep)->sr & SR_KSU_USER) != 0)
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#define TRAPF_PC(framep) ((framep)->pc)
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#define cpu_getstack(td) ((td)->td_frame->sp)
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#define cpu_setstack(td, nsp) ((td)->td_frame->sp = (nsp))
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#define cpu_spinwait() /* nothing */
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/*
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* A machine-independent interface to the CPU's counter.
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*/
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#define get_cyclecount() mips_rd_count()
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static __inline uint64_t
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get_cyclecount(void)
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{
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return (mips_rd_count());
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}
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#endif /* !_LOCORE */
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/*
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* CTL_MACHDEP definitions.
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*/
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#define CPU_CONSDEV 1 /* dev_t: console terminal device */
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#define CPU_ADJKERNTZ 2 /* int: timezone offset (seconds) */
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#define CPU_DISRTCSET 3 /* int: disable resettodr() call */
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#define CPU_BOOTINFO 4 /* struct: bootinfo */
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#define CPU_WALLCLOCK 5 /* int: indicates wall CMOS clock */
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#define CPU_MAXID 6 /* number of valid machdep ids */
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#define CTL_MACHDEP_NAMES { \
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{ 0, 0 }, \
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{ "console_device", CTLTYPE_STRUCT }, \
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{ "adjkerntz", CTLTYPE_INT }, \
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{ "disable_rtc_set", CTLTYPE_INT }, \
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{ "bootinfo", CTLTYPE_STRUCT }, \
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{ "wall_cmos_clock", CTLTYPE_INT }, \
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}
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/*
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* MIPS CPU types (cp_imp).
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*/
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#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
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#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
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#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
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#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
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#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
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#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
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#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
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#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
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#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
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#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
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#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
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#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
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#define MIPS_RM7000 0x27 /* QED RM7000 CPU ISA IV */
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#define MIPS_RM52X0 0x28 /* QED RM52X0 CPU ISA IV */
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#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */
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#define MIPS_RM9000 0x34 /* E9000 CPU */
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/*
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* MIPS FPU types
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*/
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#define MIPS_SOFT 0x00 /* Software emulation ISA I */
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#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
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#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
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#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
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#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
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#define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */
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#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
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#define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */
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#define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */
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#define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */
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#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
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#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
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#define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */
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#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
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#define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */
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#define MIPS_RM7000 0x27 /* QED RM7000 FPU ISA IV */
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#define MIPS_RM5230 0x28 /* QED RM52X0 based FPU ISA IV */
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#define MIPS_RM52XX 0x28 /* QED RM52X0 based FPU ISA IV */
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#define MIPS_VR5400 0x54 /* NEC Vr5400 FPU ISA IV+ */
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#if defined(_KERNEL) && !defined(_LOCORE)
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struct user;
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int Mips_ConfigCache(void);
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void Mips_SyncCache(void);
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void Mips_SyncDCache(vm_offset_t, int);
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void Mips_HitSyncDCache(vm_offset_t, int);
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void Mips_HitSyncSCache(vm_offset_t, int);
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void Mips_IOSyncDCache(vm_offset_t, int, int);
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void Mips_HitInvalidateDCache(vm_offset_t, int);
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void Mips_SyncICache(vm_offset_t, int);
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void Mips_InvalidateICache(vm_offset_t, int);
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void wbflush(void);
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extern u_int32_t cpu_counter_interval; /* Number of counter ticks/tick */
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extern u_int32_t cpu_counter_last; /* Last compare value loaded */
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extern int num_tlbentries;
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extern char btext[];
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extern char etext[];
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extern int intr_nesting_level;
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#define func_0args_asmmacro(func, in) \
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__asm __volatile ( "jalr %0" \
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: "=r" (in) /* outputs */ \
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: "r" (func) /* inputs */ \
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: "$31", "$4");
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#define func_1args_asmmacro(func, arg0) \
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__asm __volatile ("move $4, %1;" \
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"jalr %0" \
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: /* outputs */ \
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: "r" (func), "r" (arg0) /* inputs */ \
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: "$31", "$4");
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#define func_2args_asmmacro(func, arg0, arg1) \
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__asm __volatile ("move $4, %1;" \
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"move $5, %2;" \
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"jalr %0" \
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: /* outputs */ \
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: "r" (func), "r" (arg0), "r" (arg1) /* inputs */ \
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: "$31", "$4", "$5");
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#define func_3args_asmmacro(func, arg0, arg1, arg2) \
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__asm __volatile ( "move $4, %1;" \
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"move $5, %2;" \
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"move $6, %3;" \
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"jalr %0" \
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: /* outputs */ \
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: "r" (func), "r" (arg0), "r" (arg1), "r" (arg2) /* inputs */ \
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: "$31", "$4", "$5", "$6");
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/*
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* Enable realtime clock (always enabled).
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*/
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#define enablertclock()
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/*
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* Are we in an interrupt handler? required by JunOS
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*/
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#define IN_INT_HANDLER() \
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(curthread->td_intr_nesting_level != 0 || \
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(curthread->td_pflags & TDP_ITHREAD))
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/*
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* Low level access routines to CPU registers
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*/
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void swi_vm(void *);
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void cpu_halt(void);
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void cpu_reset(void);
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u_int32_t set_intr_mask(u_int32_t);
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u_int32_t get_intr_mask(void);
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#define cpu_spinwait() /* nothing */
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#endif /* _KERNEL */
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#endif /* !_MACHINE_CPU_H_ */
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@ -77,4 +77,7 @@ void platform_identify(void);
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extern int busdma_swi_pending;
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void busdma_swi(void);
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u_int32_t set_intr_mask(u_int32_t);
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u_int32_t get_intr_mask(void);
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#endif /* !_MACHINE_MD_VAR_H_ */
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@ -35,5 +35,6 @@ void tlb_invalidate_all(void);
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void tlb_invalidate_all_user(struct pmap *);
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void tlb_save(void);
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void tlb_update(struct pmap *, vm_offset_t, pt_entry_t);
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extern int num_tlbentries;
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#endif /* !_MACHINE_TLB_H_ */
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