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Add simple support for AGP 3.0 including enabling 8x mode. The simple
part of the support is that it still assumes one master and one target where as AGP 3.0 actually supports multiple devices on the bus. Submitted by: Keith Whitwell <keith@tungstengraphics.com> Sponsored by: The Weather Channel
This commit is contained in:
John Baldwin
parent
56f88dba4c
commit
9f9ccd206d
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=121440
@ -278,18 +278,83 @@ agp_generic_detach(device_t dev)
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return 0;
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}
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int
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agp_generic_enable(device_t dev, u_int32_t mode)
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/*
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* This does the enable logic for v3, with the same topology
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* restrictions as in place for v2 -- one bus, one device on the bus.
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*/
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static int
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agp_v3_enable(device_t dev, device_t mdev, u_int32_t mode)
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{
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device_t mdev = agp_find_display();
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u_int32_t tstatus, mstatus;
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u_int32_t command;
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int rq, sba, fw, rate;;
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int rq, sba, fw, rate, arqsz, cal;
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if (!mdev) {
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AGP_DPF("can't find display\n");
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return ENXIO;
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}
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tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
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mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
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/* Set RQ to the min of mode, tstatus and mstatus */
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rq = AGP_MODE_GET_RQ(mode);
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if (AGP_MODE_GET_RQ(tstatus) < rq)
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rq = AGP_MODE_GET_RQ(tstatus);
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if (AGP_MODE_GET_RQ(mstatus) < rq)
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rq = AGP_MODE_GET_RQ(mstatus);
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/*
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* ARQSZ - Set the value to the maximum one.
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* Don't allow the mode register to override values.
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*/
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arqsz = AGP_MODE_GET_ARQSZ(mode);
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if (AGP_MODE_GET_ARQSZ(tstatus) > rq)
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rq = AGP_MODE_GET_ARQSZ(tstatus);
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if (AGP_MODE_GET_ARQSZ(mstatus) > rq)
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rq = AGP_MODE_GET_ARQSZ(mstatus);
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/* Calibration cycle - don't allow override by mode register */
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cal = AGP_MODE_GET_CAL(tstatus);
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if (AGP_MODE_GET_CAL(mstatus) < cal)
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cal = AGP_MODE_GET_CAL(mstatus);
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/* SBA must be supported for AGP v3. */
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sba = 1;
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/* Set FW if all three support it. */
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fw = (AGP_MODE_GET_FW(tstatus)
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& AGP_MODE_GET_FW(mstatus)
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& AGP_MODE_GET_FW(mode));
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/* Figure out the max rate */
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rate = (AGP_MODE_GET_RATE(tstatus)
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& AGP_MODE_GET_RATE(mstatus)
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& AGP_MODE_GET_RATE(mode));
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if (rate & AGP_MODE_V3_RATE_8x)
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rate = AGP_MODE_V3_RATE_8x;
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else
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rate = AGP_MODE_V3_RATE_4x;
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if (bootverbose)
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device_printf(dev, "Setting AGP v3 mode %d\n", rate * 4);
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pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, 0, 4);
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/* Construct the new mode word and tell the hardware */
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command = AGP_MODE_SET_RQ(0, rq);
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command = AGP_MODE_SET_ARQSZ(command, arqsz);
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command = AGP_MODE_SET_CAL(command, cal);
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command = AGP_MODE_SET_SBA(command, sba);
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command = AGP_MODE_SET_FW(command, fw);
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command = AGP_MODE_SET_RATE(command, rate);
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command = AGP_MODE_SET_AGP(command, 1);
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pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, command, 4);
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pci_write_config(mdev, agp_find_caps(mdev) + AGP_COMMAND, command, 4);
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return 0;
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}
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static int
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agp_v2_enable(device_t dev, device_t mdev, u_int32_t mode)
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{
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u_int32_t tstatus, mstatus;
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u_int32_t command;
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int rq, sba, fw, rate;
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tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
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mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
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@ -315,12 +380,14 @@ agp_generic_enable(device_t dev, u_int32_t mode)
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rate = (AGP_MODE_GET_RATE(tstatus)
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& AGP_MODE_GET_RATE(mstatus)
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& AGP_MODE_GET_RATE(mode));
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if (rate & AGP_MODE_RATE_4x)
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rate = AGP_MODE_RATE_4x;
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else if (rate & AGP_MODE_RATE_2x)
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rate = AGP_MODE_RATE_2x;
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if (rate & AGP_MODE_V2_RATE_4x)
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rate = AGP_MODE_V2_RATE_4x;
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else if (rate & AGP_MODE_V2_RATE_2x)
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rate = AGP_MODE_V2_RATE_2x;
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else
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rate = AGP_MODE_RATE_1x;
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rate = AGP_MODE_V2_RATE_1x;
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if (bootverbose)
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device_printf(dev, "Setting AGP v2 mode %d\n", rate);
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/* Construct the new mode word and tell the hardware */
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command = AGP_MODE_SET_RQ(0, rq);
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@ -334,6 +401,34 @@ agp_generic_enable(device_t dev, u_int32_t mode)
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return 0;
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}
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int
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agp_generic_enable(device_t dev, u_int32_t mode)
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{
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device_t mdev = agp_find_display();
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u_int32_t tstatus, mstatus;
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if (!mdev) {
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AGP_DPF("can't find display\n");
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return ENXIO;
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}
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tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
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mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
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/*
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* Check display and bridge for AGP v3 support. AGP v3 allows
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* more variety in topology than v2, e.g. multiple AGP devices
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* attached to one bridge, or multiple AGP bridges in one
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* system. This doesn't attempt to address those situations,
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* but should work fine for a classic single AGP slot system
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* with AGP v3.
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*/
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if (AGP_MODE_GET_MODE_3(tstatus) && AGP_MODE_GET_MODE_3(mstatus))
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return (agp_v3_enable(dev, mdev, mode));
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else
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return (agp_v2_enable(dev, mdev, mode));
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}
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struct agp_memory *
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agp_generic_alloc_memory(device_t dev, int type, vm_size_t size)
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{
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121
sys/pci/agp.c
121
sys/pci/agp.c
@ -278,18 +278,83 @@ agp_generic_detach(device_t dev)
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return 0;
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}
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int
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agp_generic_enable(device_t dev, u_int32_t mode)
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/*
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* This does the enable logic for v3, with the same topology
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* restrictions as in place for v2 -- one bus, one device on the bus.
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*/
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static int
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agp_v3_enable(device_t dev, device_t mdev, u_int32_t mode)
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{
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device_t mdev = agp_find_display();
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u_int32_t tstatus, mstatus;
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u_int32_t command;
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int rq, sba, fw, rate;;
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int rq, sba, fw, rate, arqsz, cal;
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if (!mdev) {
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AGP_DPF("can't find display\n");
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return ENXIO;
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}
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tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
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mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
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/* Set RQ to the min of mode, tstatus and mstatus */
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rq = AGP_MODE_GET_RQ(mode);
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if (AGP_MODE_GET_RQ(tstatus) < rq)
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rq = AGP_MODE_GET_RQ(tstatus);
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if (AGP_MODE_GET_RQ(mstatus) < rq)
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rq = AGP_MODE_GET_RQ(mstatus);
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/*
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* ARQSZ - Set the value to the maximum one.
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* Don't allow the mode register to override values.
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*/
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arqsz = AGP_MODE_GET_ARQSZ(mode);
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if (AGP_MODE_GET_ARQSZ(tstatus) > rq)
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rq = AGP_MODE_GET_ARQSZ(tstatus);
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if (AGP_MODE_GET_ARQSZ(mstatus) > rq)
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rq = AGP_MODE_GET_ARQSZ(mstatus);
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/* Calibration cycle - don't allow override by mode register */
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cal = AGP_MODE_GET_CAL(tstatus);
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if (AGP_MODE_GET_CAL(mstatus) < cal)
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cal = AGP_MODE_GET_CAL(mstatus);
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/* SBA must be supported for AGP v3. */
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sba = 1;
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/* Set FW if all three support it. */
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fw = (AGP_MODE_GET_FW(tstatus)
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& AGP_MODE_GET_FW(mstatus)
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& AGP_MODE_GET_FW(mode));
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/* Figure out the max rate */
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rate = (AGP_MODE_GET_RATE(tstatus)
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& AGP_MODE_GET_RATE(mstatus)
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& AGP_MODE_GET_RATE(mode));
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if (rate & AGP_MODE_V3_RATE_8x)
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rate = AGP_MODE_V3_RATE_8x;
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else
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rate = AGP_MODE_V3_RATE_4x;
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if (bootverbose)
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device_printf(dev, "Setting AGP v3 mode %d\n", rate * 4);
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pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, 0, 4);
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/* Construct the new mode word and tell the hardware */
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command = AGP_MODE_SET_RQ(0, rq);
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command = AGP_MODE_SET_ARQSZ(command, arqsz);
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command = AGP_MODE_SET_CAL(command, cal);
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command = AGP_MODE_SET_SBA(command, sba);
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command = AGP_MODE_SET_FW(command, fw);
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command = AGP_MODE_SET_RATE(command, rate);
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command = AGP_MODE_SET_AGP(command, 1);
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pci_write_config(dev, agp_find_caps(dev) + AGP_COMMAND, command, 4);
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pci_write_config(mdev, agp_find_caps(mdev) + AGP_COMMAND, command, 4);
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return 0;
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}
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static int
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agp_v2_enable(device_t dev, device_t mdev, u_int32_t mode)
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{
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u_int32_t tstatus, mstatus;
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u_int32_t command;
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int rq, sba, fw, rate;
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tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
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mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
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@ -315,12 +380,14 @@ agp_generic_enable(device_t dev, u_int32_t mode)
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rate = (AGP_MODE_GET_RATE(tstatus)
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& AGP_MODE_GET_RATE(mstatus)
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& AGP_MODE_GET_RATE(mode));
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if (rate & AGP_MODE_RATE_4x)
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rate = AGP_MODE_RATE_4x;
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else if (rate & AGP_MODE_RATE_2x)
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rate = AGP_MODE_RATE_2x;
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if (rate & AGP_MODE_V2_RATE_4x)
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rate = AGP_MODE_V2_RATE_4x;
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else if (rate & AGP_MODE_V2_RATE_2x)
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rate = AGP_MODE_V2_RATE_2x;
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else
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rate = AGP_MODE_RATE_1x;
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rate = AGP_MODE_V2_RATE_1x;
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if (bootverbose)
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device_printf(dev, "Setting AGP v2 mode %d\n", rate);
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/* Construct the new mode word and tell the hardware */
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command = AGP_MODE_SET_RQ(0, rq);
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@ -334,6 +401,34 @@ agp_generic_enable(device_t dev, u_int32_t mode)
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return 0;
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}
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int
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agp_generic_enable(device_t dev, u_int32_t mode)
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{
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device_t mdev = agp_find_display();
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u_int32_t tstatus, mstatus;
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if (!mdev) {
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AGP_DPF("can't find display\n");
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return ENXIO;
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}
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tstatus = pci_read_config(dev, agp_find_caps(dev) + AGP_STATUS, 4);
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mstatus = pci_read_config(mdev, agp_find_caps(mdev) + AGP_STATUS, 4);
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/*
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* Check display and bridge for AGP v3 support. AGP v3 allows
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* more variety in topology than v2, e.g. multiple AGP devices
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* attached to one bridge, or multiple AGP bridges in one
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* system. This doesn't attempt to address those situations,
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* but should work fine for a classic single AGP slot system
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* with AGP v3.
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*/
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if (AGP_MODE_GET_MODE_3(tstatus) && AGP_MODE_GET_MODE_3(mstatus))
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return (agp_v3_enable(dev, mdev, mode));
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else
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return (agp_v2_enable(dev, mdev, mode));
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}
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struct agp_memory *
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agp_generic_alloc_memory(device_t dev, int type, vm_size_t size)
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{
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@ -42,20 +42,38 @@
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* FW = Fast Writes
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*/
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#define AGP_MODE_GET_RQ(x) (((x) & 0xff000000U) >> 24)
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#define AGP_MODE_GET_ARQSZ(x) (((x) & 0x0000e000U) >> 13)
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#define AGP_MODE_GET_CAL(x) (((x) & 0x00001c00U) >> 10)
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#define AGP_MODE_GET_SBA(x) (((x) & 0x00000200U) >> 9)
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#define AGP_MODE_GET_AGP(x) (((x) & 0x00000100U) >> 8)
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#define AGP_MODE_GET_4G(x) (((x) & 0x00000020U) >> 5)
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#define AGP_MODE_GET_GART_64(x) (((x) & 0x00000080U) >> 7)
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#define AGP_MODE_GET_OVER_4G(x) (((x) & 0x00000020U) >> 5)
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#define AGP_MODE_GET_FW(x) (((x) & 0x00000010U) >> 4)
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#define AGP_MODE_GET_MODE_3(x) (((x) & 0x00000008U) >> 3)
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#define AGP_MODE_GET_RATE(x) ((x) & 0x00000007U)
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#define AGP_MODE_SET_RQ(x,v) (((x) & ~0xff000000U) | ((v) << 24))
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#define AGP_MODE_SET_ARQSZ(x,v) (((x) & ~0x0000e000U) | ((v) << 13))
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#define AGP_MODE_SET_CAL(x,v) (((x) & ~0x00001c00U) | ((v) << 10))
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#define AGP_MODE_SET_SBA(x,v) (((x) & ~0x00000200U) | ((v) << 9))
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#define AGP_MODE_SET_AGP(x,v) (((x) & ~0x00000100U) | ((v) << 8))
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#define AGP_MODE_SET_4G(x,v) (((x) & ~0x00000020U) | ((v) << 5))
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#define AGP_MODE_SET_GART_64(x,v) (((x) & ~0x00000080U) | ((v) << 7))
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#define AGP_MODE_SET_OVER_4G(x,v) (((x) & ~0x00000020U) | ((v) << 5))
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#define AGP_MODE_SET_FW(x,v) (((x) & ~0x00000010U) | ((v) << 4))
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#define AGP_MODE_SET_MODE_3(x,v) (((x) & ~0x00000008U) | ((v) << 3))
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#define AGP_MODE_SET_RATE(x,v) (((x) & ~0x00000007U) | (v))
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#define AGP_MODE_RATE_1x 0x00000001
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#define AGP_MODE_RATE_2x 0x00000002
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#define AGP_MODE_RATE_4x 0x00000004
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#define AGP_MODE_V2_RATE_1x 0x00000001
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#define AGP_MODE_V2_RATE_2x 0x00000002
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#define AGP_MODE_V2_RATE_4x 0x00000004
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#define AGP_MODE_V3_RATE_4x 0x00000001
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#define AGP_MODE_V3_RATE_8x 0x00000002
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#define AGP_MODE_V3_RATE_RSVD 0x00000004
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/* XXX: Compat */
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#define AGP_MODE_GET_4G(x) AGP_MODE_GET_OVER_4G(x)
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#define AGP_MODE_SET_4G(x) AGP_MODE_SET_OVER_4G(x)
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#define AGP_MODE_RATE_1x AGP_MODE_V2_RATE_1x
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#define AGP_MODE_RATE_2x AGP_MODE_V2_RATE_2x
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#define AGP_MODE_RATE_4x AGP_MODE_V2_RATE_4x
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#define AGPIOC_BASE 'A'
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#define AGPIOC_INFO _IOR (AGPIOC_BASE, 0, agp_info)
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