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Add more definitions for vendor-specific CPU capability bits to the last

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revision, which is renamed to "Intel Processor Vendor-Specific ACPI".
This commit is contained in:
Jung-uk Kim 2011-02-25 18:29:57 +00:00
parent 750ffe843d
commit 9fae4b2a8c
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=219037
1 changed files with 13 additions and 11 deletions
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24
sys/dev/acpica/acpivar.h
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@ -186,18 +186,20 @@ extern struct mtx acpi_mutex;
/*
* Various features and capabilities for the acpi_get_features() method.
* In particular, these are used for the ACPI 3.0 _PDC and _OSC methods.
* See the Intel document titled "Processor Driver Capabilities Bit
* Definitions", number 302223-002.
* See the Intel document titled "Intel Processor Vendor-Specific ACPI",
* number 302223-005.
*/
#define ACPI_CAP_PERF_MSRS (1 << 0) /* Intel SpeedStep PERF_CTL MSRs */
#define ACPI_CAP_C1_IO_HALT (1 << 1) /* Intel C1 "IO then halt" sequence */
#define ACPI_CAP_THR_MSRS (1 << 2) /* Intel OnDemand throttling MSRs */
#define ACPI_CAP_SMP_SAME (1 << 3) /* MP C1, Px, and Tx (all the same) */
#define ACPI_CAP_SMP_SAME_C3 (1 << 4) /* MP C2 and C3 (all the same) */
#define ACPI_CAP_SMP_DIFF_PX (1 << 5) /* MP Px (different, using _PSD) */
#define ACPI_CAP_SMP_DIFF_CX (1 << 6) /* MP Cx (different, using _CSD) */
#define ACPI_CAP_SMP_DIFF_TX (1 << 7) /* MP Tx (different, using _TSD) */
#define ACPI_CAP_SMP_C1_NATIVE (1 << 8) /* MP C1 support other than halt */
#define ACPI_CAP_PERF_MSRS (1 << 0) /* Intel SpeedStep PERF_CTL MSRs */
#define ACPI_CAP_C1_IO_HALT (1 << 1) /* Intel C1 "IO then halt" sequence */
#define ACPI_CAP_THR_MSRS (1 << 2) /* Intel OnDemand throttling MSRs */
#define ACPI_CAP_SMP_SAME (1 << 3) /* MP C1, Px, and Tx (all the same) */
#define ACPI_CAP_SMP_SAME_C3 (1 << 4) /* MP C2 and C3 (all the same) */
#define ACPI_CAP_SMP_DIFF_PX (1 << 5) /* MP Px (different, using _PSD) */
#define ACPI_CAP_SMP_DIFF_CX (1 << 6) /* MP Cx (different, using _CSD) */
#define ACPI_CAP_SMP_DIFF_TX (1 << 7) /* MP Tx (different, using _TSD) */
#define ACPI_CAP_SMP_C1_NATIVE (1 << 8) /* MP C1 support other than halt */
#define ACPI_CAP_SMP_C3_NATIVE (1 << 9) /* MP C2 and C3 support */
#define ACPI_CAP_PX_HW_COORD (1 << 11) /* Intel P-state HW coordination */
/*
* Quirk flags.