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Resolve cache line size from CP15
Switch the cache line size during invalidations/flushes to be read from CP15 cache type register. Submitted by: Wojciech Macek <wma@semihalf.com> Reviewed by: ian, imp Obtained from: Semihalf
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parent
d91f92d285
commit
9fc0d68aeb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=278518
sys/arm
@ -837,6 +837,11 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
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defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
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defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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/* Global cache line sizes, use 32 as default */
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int arm_dcache_min_line_size = 32;
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int arm_icache_min_line_size = 32;
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int arm_idcache_min_line_size = 32;
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static void get_cachetype_cp15(void);
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/* Additional cache information local to this file. Log2 of some of the
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@ -868,6 +873,12 @@ get_cachetype_cp15()
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goto out;
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if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) {
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/* Resolve minimal cache line sizes */
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arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
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arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
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arm_idcache_min_line_size =
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min(arm_icache_min_line_size, arm_dcache_min_line_size);
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__asm __volatile("mrc p15, 1, %0, c0, c0, 1"
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: "=r" (clevel));
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arm_cache_level = clevel;
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@ -41,6 +41,12 @@ __FBSDID("$FreeBSD$");
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.word _C_LABEL(arm_cache_loc)
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.Lcache_type:
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.word _C_LABEL(arm_cache_type)
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.Larmv7_dcache_line_size:
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.word _C_LABEL(arm_dcache_min_line_size)
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.Larmv7_icache_line_size:
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.word _C_LABEL(arm_icache_min_line_size)
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.Larmv7_idcache_line_size:
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.word _C_LABEL(arm_idcache_min_line_size)
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.Lway_mask:
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.word 0x3ff
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.Lmax_index:
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@ -180,14 +186,9 @@ ENTRY(armv7_idcache_wbinv_all)
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RET
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END(armv7_idcache_wbinv_all)
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/* XXX Temporary set it to 32 for MV cores, however this value should be
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* get from Cache Type register
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*/
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.Larmv7_line_size:
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.word 32
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ENTRY(armv7_dcache_wb_range)
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ldr ip, .Larmv7_line_size
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ldr ip, .Larmv7_dcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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@ -202,7 +203,8 @@ ENTRY(armv7_dcache_wb_range)
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END(armv7_dcache_wb_range)
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ENTRY(armv7_dcache_wbinv_range)
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ldr ip, .Larmv7_line_size
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ldr ip, .Larmv7_dcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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@ -221,7 +223,8 @@ END(armv7_dcache_wbinv_range)
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* must use wb-inv of the entire cache.
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*/
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ENTRY(armv7_dcache_inv_range)
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ldr ip, .Larmv7_line_size
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ldr ip, .Larmv7_dcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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@ -236,7 +239,8 @@ ENTRY(armv7_dcache_inv_range)
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END(armv7_dcache_inv_range)
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ENTRY(armv7_idcache_wbinv_range)
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ldr ip, .Larmv7_line_size
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ldr ip, .Larmv7_idcache_line_size
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ldr ip, [ip]
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sub r3, ip, #1
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and r2, r0, r3
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add r1, r1, r2
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@ -264,7 +268,8 @@ ENTRY_NP(armv7_icache_sync_all)
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END(armv7_icache_sync_all)
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ENTRY_NP(armv7_icache_sync_range)
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ldr ip, .Larmv7_line_size
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ldr ip, .Larmv7_icache_line_size
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ldr ip, [ip]
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.Larmv7_sync_next:
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mcr CP15_ICIMVAU(r0)
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mcr CP15_DCCMVAC(r0)
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@ -115,6 +115,10 @@ int arm_pcache_unified;
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int arm_dcache_align;
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int arm_dcache_align_mask;
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int arm_dcache_min_line_size = 32;
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int arm_icache_min_line_size = 32;
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int arm_idcache_min_line_size = 32;
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u_int arm_cache_level;
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u_int arm_cache_type[14];
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u_int arm_cache_loc;
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@ -277,6 +281,13 @@ get_cachetype_cp15()
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goto out;
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if (CPU_CT_FORMAT(ctype) == CPU_CT_ARMV7) {
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/* Resolve minimal cache line sizes */
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arm_dcache_min_line_size = 1 << (CPU_CT_DMINLINE(ctype) + 2);
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arm_icache_min_line_size = 1 << (CPU_CT_IMINLINE(ctype) + 2);
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arm_idcache_min_line_size =
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(arm_dcache_min_line_size > arm_icache_min_line_size ?
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arm_icache_min_line_size : arm_dcache_min_line_size);
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__asm __volatile("mrc p15, 1, %0, c0, c0, 1"
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: "=r" (clevel));
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arm_cache_level = clevel;
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@ -320,6 +320,9 @@
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#define CPU_CT_S (1U << 24) /* split cache */
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#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */
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#define CPU_CT_FORMAT(x) ((x) >> 29)
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/* Cache type register definitions for ARM v7 */
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#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */
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#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */
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#define CPU_CT_CTYPE_WT 0 /* write-through */
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#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */
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