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Add preliminary support for the RTL8153.
Reviewed by: hselasky
This commit is contained in:
Kevin Lo
parent
427e366e43
commit
a24d62b533
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=308121
@ -2713,7 +2713,7 @@ nomatch 32 {
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match "bus" "uhub[0-9]+";
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match "mode" "host";
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match "vendor" "0x0bda";
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match "product" "0x8152";
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match "product" "(0x8152|0x8153)";
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action "kldload -n if_ure";
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};
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@ -1,5 +1,5 @@
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.\"
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.\" Copyright (c) 2015 Kevin Lo <kevlo@FreeBSD.org>
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.\" Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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@ -25,12 +25,12 @@
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.\"
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.\" $FreeBSD$
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.\"
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.Dd December 1, 2015
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.Dd October 31, 2016
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.Dt URE 4
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.Os
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.Sh NAME
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.Nm ure
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.Nd "RealTek RTL8152 USB to Fast Ethernet controller driver"
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.Nd "RealTek RTL8152/RTL8153 USB to Ethernet controller driver"
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.Sh SYNOPSIS
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To compile this driver into the kernel,
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place the following lines in your
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@ -54,10 +54,10 @@ if_ure_load="YES"
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The
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.Nm
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driver provides support for USB Ethernet adapters based on the RealTek
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RTL8152 USB to Fast Ethernet controller chip.
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RealTek RTL8152 and RTL8153 USB Ethernet controllers.
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.Pp
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The RTL8152 contains an integrated Fast Ethernet MAC, which supports
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both 10 and 100Mbps speeds in either full or half duplex.
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NICs based on the RTL8152 are capable of 10 and 100Mbps speeds.
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NICs based on the RTL8153 are capable of 10, 100 and 1000Mbps operation.
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.Pp
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The
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.Nm
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@ -87,12 +87,17 @@ option can also be used to select either
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or
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.Cm half-duplex
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modes.
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.It Cm 1000baseTX
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Set 1000baseTX operation over twisted pair.
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The RealTek gigE chips support 1000Mbps in
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.Cm full-duplex
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mode only.
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.El
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.Pp
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The
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.Nm
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driver supports the following media options:
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.Bl -tag -width ".Cm 10baseT/UTP"
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.Bl -tag -width ".Cm full-duplex"
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.It Cm full-duplex
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Force full duplex operation.
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.It Cm half-duplex
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@ -2788,7 +2788,7 @@ device rue
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# Davicom DM9601E USB to fast ethernet. Supports the Corega FEther USB-TXC.
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device udav
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#
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# RealTek RTL8152 USB to fast ethernet.
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# RealTek RTL8152/RTL8153 USB Ethernet driver
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device ure
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#
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# Moschip MCS7730/MCS7840 USB to fast ethernet. Supports the Sitecom LN030.
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@ -316,7 +316,7 @@ model yyREALTEK RTL8201L 0x0020 RTL8201L 10/100 media interface
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model xxREALTEK RTL8169S 0x0011 RTL8169S/8110S/8211 1000BASE-T media interface
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model REALTEK RTL8305SC 0x0005 RTL8305SC 10/100 802.1q switch
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model REALTEK RTL8201E 0x0008 RTL8201E 10/100 media interface
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model REALTEK RTL8251 0x0000 RTL8251 1000BASE-T media interface
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model REALTEK RTL8251 0x0000 RTL8251/8153 1000BASE-T media interface
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model REALTEK RTL8169S 0x0011 RTL8169S/8110S/8211 1000BASE-T media interface
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/* Seeq Seeq PHYs */
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@ -121,6 +121,8 @@ rgephy_attach(device_t dev)
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flags = 0;
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if (mii_dev_mac_match(dev, "re"))
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flags |= MIIF_PHYPRIV0;
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else if (mii_dev_mac_match(dev, "ure"))
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flags |= MIIF_PHYPRIV1;
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mii_phy_dev_attach(dev, flags, &rgephy_funcs, 0);
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/* RTL8169S do not report auto-sense; add manually. */
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@ -293,7 +295,10 @@ rgephy_linkup(struct mii_softc *sc)
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linkup++;
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}
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} else {
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reg = PHY_READ(sc, RL_GMEDIASTAT);
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if (sc->mii_flags & MIIF_PHYPRIV1)
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reg = PHY_READ(sc, URE_GMEDIASTAT);
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else
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reg = PHY_READ(sc, RL_GMEDIASTAT);
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if (reg & RL_GMEDIASTAT_LINK)
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linkup++;
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}
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@ -378,7 +383,10 @@ rgephy_status(struct mii_softc *sc)
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mii->mii_media_active |= IFM_HDX;
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}
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} else {
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bmsr = PHY_READ(sc, RL_GMEDIASTAT);
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if (sc->mii_flags & MIIF_PHYPRIV1)
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bmsr = PHY_READ(sc, URE_GMEDIASTAT);
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else
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bmsr = PHY_READ(sc, RL_GMEDIASTAT);
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if (bmsr & RL_GMEDIASTAT_1000MBPS)
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mii->mii_media_active |= IFM_1000_T;
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else if (bmsr & RL_GMEDIASTAT_100MBPS)
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@ -199,4 +199,7 @@
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#define EEELPAR_1000T 0x0004 /* link partner 1000baseT EEE capable */
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#define EEELPAR_100TX 0x0002 /* link partner 100baseTX EEE capable */
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/* RTL8153 */
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#define URE_GMEDIASTAT 0xe908 /* media status register */
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#endif /* _DEV_RGEPHY_MIIREG_H_ */
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2015 Kevin Lo <kevlo@FreeBSD.org>
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* Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -66,8 +66,9 @@ SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0,
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* Various supported device vendors/products.
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*/
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static const STRUCT_USB_HOST_ID ure_devs[] = {
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#define URE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) }
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URE_DEV(REALTEK, RTL8152),
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#define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
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URE_DEV(REALTEK, RTL8152, URE_FLAG_8152),
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URE_DEV(REALTEK, RTL8153, 0),
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#undef URE_DEV
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};
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@ -87,8 +88,7 @@ static uether_fn_t ure_init;
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static uether_fn_t ure_stop;
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static uether_fn_t ure_start;
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static uether_fn_t ure_tick;
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static uether_fn_t ure_setmulti;
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static uether_fn_t ure_setpromisc;
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static uether_fn_t ure_rxfilter;
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static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t,
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void *, int);
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@ -112,6 +112,7 @@ static int ure_ifmedia_upd(struct ifnet *);
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static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *);
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static int ure_ioctl(struct ifnet *, u_long, caddr_t);
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static void ure_rtl8152_init(struct ure_softc *);
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static void ure_rtl8153_init(struct ure_softc *);
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static void ure_disable_teredo(struct ure_softc *);
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static void ure_init_fifo(struct ure_softc *);
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@ -129,7 +130,7 @@ static const struct usb_config ure_config[URE_N_TRANSFER] = {
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.type = UE_BULK,
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.endpoint = UE_ADDR_ANY,
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.direction = UE_DIR_IN,
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.bufsize = MCLBYTES,
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.bufsize = 16384,
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.flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
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.callback = ure_bulk_read_callback,
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.timeout = 0, /* no timeout */
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@ -173,8 +174,8 @@ static const struct usb_ether_methods ure_ue_methods = {
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.ue_init = ure_init,
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.ue_stop = ure_stop,
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.ue_tick = ure_tick,
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.ue_setmulti = ure_setmulti,
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.ue_setpromisc = ure_setpromisc,
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.ue_setmulti = ure_rxfilter,
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.ue_setpromisc = ure_rxfilter,
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.ue_mii_upd = ure_ifmedia_upd,
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.ue_mii_sts = ure_ifmedia_sts,
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};
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@ -343,6 +344,13 @@ ure_miibus_readreg(device_t dev, int phy, int reg)
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if (!locked)
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URE_LOCK(sc);
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/* Let the rgephy driver read the URE_GMEDIASTAT register. */
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if (reg == URE_GMEDIASTAT) {
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if (!locked)
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URE_UNLOCK(sc);
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return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA));
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}
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val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2);
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if (!locked)
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@ -398,6 +406,11 @@ ure_miibus_statchg(device_t dev)
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case IFM_100_TX:
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sc->sc_flags |= URE_FLAG_LINK;
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break;
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case IFM_1000_T:
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if ((sc->sc_flags & URE_FLAG_8152) != 0)
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break;
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sc->sc_flags |= URE_FLAG_LINK;
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break;
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default:
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break;
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}
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@ -412,7 +425,7 @@ ure_miibus_statchg(device_t dev)
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}
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/*
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* Probe for a RTL8152 chip.
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* Probe for a RTL8152/RTL8153 chip.
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*/
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static int
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ure_probe(device_t dev)
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@ -443,6 +456,7 @@ ure_attach(device_t dev)
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uint8_t iface_index;
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int error;
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sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
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device_set_usb_desc(dev);
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mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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@ -617,6 +631,18 @@ ure_read_chipver(struct ure_softc *sc)
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case 0x4c10:
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sc->sc_chip |= URE_CHIP_VER_4C10;
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break;
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case 0x5c00:
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sc->sc_chip |= URE_CHIP_VER_5C00;
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break;
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case 0x5c10:
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sc->sc_chip |= URE_CHIP_VER_5C10;
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break;
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case 0x5c20:
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sc->sc_chip |= URE_CHIP_VER_5C20;
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break;
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case 0x5c30:
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sc->sc_chip |= URE_CHIP_VER_5C30;
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break;
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default:
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device_printf(sc->sc_ue.ue_dev,
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"unknown version 0x%04x\n", ver);
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@ -635,7 +661,10 @@ ure_attach_post(struct usb_ether *ue)
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ure_read_chipver(sc);
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/* Initialize controller and get station address. */
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ure_rtl8152_init(sc);
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if (sc->sc_flags & URE_FLAG_8152)
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ure_rtl8152_init(sc);
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else
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ure_rtl8153_init(sc);
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if (sc->sc_chip & URE_CHIP_VER_4C00)
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ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA,
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@ -676,7 +705,6 @@ ure_init(struct usb_ether *ue)
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{
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struct ure_softc *sc = uether_getsc(ue);
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struct ifnet *ifp = uether_getifp(ue);
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uint32_t rxmode;
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URE_LOCK_ASSERT(sc, MA_OWNED);
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@ -709,20 +737,8 @@ ure_init(struct usb_ether *ue)
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ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) &
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~URE_RXDY_GATED_EN);
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/* Set Rx mode. */
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rxmode = URE_RCR_APM;
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/* If we want promiscuous mode, set the allframes bit. */
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if (ifp->if_flags & IFF_PROMISC)
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rxmode |= URE_RCR_AAP;
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if (ifp->if_flags & IFF_BROADCAST)
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rxmode |= URE_RCR_AB;
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ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
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/* Load the multicast filter. */
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ure_setmulti(ue);
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/* Configure RX filters. */
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ure_rxfilter(ue);
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usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]);
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@ -750,30 +766,11 @@ ure_tick(struct usb_ether *ue)
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}
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}
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static void
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ure_setpromisc(struct usb_ether *ue)
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{
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struct ure_softc *sc = uether_getsc(ue);
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struct ifnet *ifp = uether_getifp(ue);
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uint32_t rxmode;
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rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
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if (ifp->if_flags & IFF_PROMISC)
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rxmode |= URE_RCR_AAP;
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else
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rxmode &= ~URE_RCR_AAP;
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ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode);
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ure_setmulti(ue);
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}
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/*
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* Program the 64-bit multicast hash filter.
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*/
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static void
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ure_setmulti(struct usb_ether *ue)
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ure_rxfilter(struct usb_ether *ue)
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{
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struct ure_softc *sc = uether_getsc(ue);
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struct ifnet *ifp = uether_getifp(ue);
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@ -783,7 +780,9 @@ ure_setmulti(struct usb_ether *ue)
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URE_LOCK_ASSERT(sc, MA_OWNED);
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rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA);
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rxmode = URE_RCR_APM;
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if (ifp->if_flags & IFF_BROADCAST)
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rxmode |= URE_RCR_AB;
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if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
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if (ifp->if_flags & IFF_PROMISC)
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rxmode |= URE_RCR_AAP;
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@ -792,6 +791,7 @@ ure_setmulti(struct usb_ether *ue)
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goto done;
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}
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rxmode |= URE_RCR_AM;
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if_maddr_rlock(ifp);
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TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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@ -964,6 +964,156 @@ ure_rtl8152_init(struct ure_softc *sc)
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URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1);
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}
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static void
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ure_rtl8153_init(struct ure_softc *sc)
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{
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uint16_t val;
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uint8_t u1u2[8];
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int i;
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/* Disable ALDPS. */
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ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
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ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
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uether_pause(&sc->sc_ue, hz / 50);
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memset(u1u2, 0x00, sizeof(u1u2));
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ure_write_mem(sc, URE_USB_TOLERANCE,
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URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
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for (i = 0; i < URE_TIMEOUT; i++) {
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if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) &
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URE_AUTOLOAD_DONE)
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break;
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uether_pause(&sc->sc_ue, hz / 100);
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}
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if (i == URE_TIMEOUT)
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device_printf(sc->sc_ue.ue_dev,
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"timeout waiting for chip autoload\n");
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for (i = 0; i < URE_TIMEOUT; i++) {
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val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) &
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URE_PHY_STAT_MASK;
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if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN)
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break;
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uether_pause(&sc->sc_ue, hz / 100);
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}
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if (i == URE_TIMEOUT)
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device_printf(sc->sc_ue.ue_dev,
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"timeout waiting for phy to stabilize\n");
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ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB,
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ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) &
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~URE_U2P3_ENABLE);
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if (sc->sc_chip & URE_CHIP_VER_5C10) {
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val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB);
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val &= ~URE_PWD_DN_SCALE_MASK;
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val |= URE_PWD_DN_SCALE(96);
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ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val);
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ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB,
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ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) |
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URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND);
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} else if (sc->sc_chip & URE_CHIP_VER_5C20) {
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ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA,
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ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) &
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~URE_ECM_ALDPS);
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}
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if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) {
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||||
val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB);
|
||||
if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) ==
|
||||
0)
|
||||
val &= ~URE_DYNAMIC_BURST;
|
||||
else
|
||||
val |= URE_DYNAMIC_BURST;
|
||||
ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val);
|
||||
}
|
||||
|
||||
ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB,
|
||||
ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) |
|
||||
URE_EP4_FULL_FC);
|
||||
|
||||
ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB,
|
||||
ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) &
|
||||
~URE_TIMER11_EN);
|
||||
|
||||
ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA,
|
||||
ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) &
|
||||
~URE_LED_MODE_MASK);
|
||||
|
||||
if ((sc->sc_chip & URE_CHIP_VER_5C10) &&
|
||||
usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER)
|
||||
val = URE_LPM_TIMER_500MS;
|
||||
else
|
||||
val = URE_LPM_TIMER_500US;
|
||||
ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB,
|
||||
val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM);
|
||||
|
||||
val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB);
|
||||
val &= ~URE_SEN_VAL_MASK;
|
||||
val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE;
|
||||
ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val);
|
||||
|
||||
ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001);
|
||||
|
||||
ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB,
|
||||
ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) &
|
||||
~(URE_PWR_EN | URE_PHASE2_EN));
|
||||
ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB,
|
||||
ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) &
|
||||
~URE_PCUT_STATUS);
|
||||
|
||||
memset(u1u2, 0xff, sizeof(u1u2));
|
||||
ure_write_mem(sc, URE_USB_TOLERANCE,
|
||||
URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
|
||||
|
||||
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA,
|
||||
URE_ALDPS_SPDWN_RATIO);
|
||||
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA,
|
||||
URE_EEE_SPDWN_RATIO);
|
||||
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA,
|
||||
URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN |
|
||||
URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN);
|
||||
ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA,
|
||||
URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN |
|
||||
URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN |
|
||||
URE_EEE_SPDWN_EN);
|
||||
|
||||
val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
|
||||
if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
|
||||
val |= URE_U2P3_ENABLE;
|
||||
else
|
||||
val &= ~URE_U2P3_ENABLE;
|
||||
ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
|
||||
|
||||
memset(u1u2, 0x00, sizeof(u1u2));
|
||||
ure_write_mem(sc, URE_USB_TOLERANCE,
|
||||
URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
|
||||
|
||||
/* Disable ALDPS. */
|
||||
ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
|
||||
ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS);
|
||||
uether_pause(&sc->sc_ue, hz / 50);
|
||||
|
||||
ure_init_fifo(sc);
|
||||
|
||||
/* Disable Rx aggregation. */
|
||||
ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB,
|
||||
ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) |
|
||||
URE_RX_AGG_DISABLE);
|
||||
|
||||
val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB);
|
||||
if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10)))
|
||||
val |= URE_U2P3_ENABLE;
|
||||
else
|
||||
val &= ~URE_U2P3_ENABLE;
|
||||
ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val);
|
||||
|
||||
memset(u1u2, 0xff, sizeof(u1u2));
|
||||
ure_write_mem(sc, URE_USB_TOLERANCE,
|
||||
URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2));
|
||||
}
|
||||
|
||||
static void
|
||||
ure_stop(struct usb_ether *ue)
|
||||
{
|
||||
@ -1011,6 +1161,43 @@ ure_init_fifo(struct ure_softc *sc)
|
||||
ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) &
|
||||
~URE_RCR_ACPT_ALL);
|
||||
|
||||
if (!(sc->sc_flags & URE_FLAG_8152)) {
|
||||
if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 |
|
||||
URE_CHIP_VER_5C20)) {
|
||||
ure_ocp_reg_write(sc, URE_OCP_ADC_CFG,
|
||||
URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L);
|
||||
}
|
||||
if (sc->sc_chip & URE_CHIP_VER_5C00) {
|
||||
ure_ocp_reg_write(sc, URE_OCP_EEE_CFG,
|
||||
ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) &
|
||||
~URE_CTAP_SHORT_EN);
|
||||
}
|
||||
ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
|
||||
ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
|
||||
URE_EEE_CLKDIV_EN);
|
||||
ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED,
|
||||
ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) |
|
||||
URE_EN_10M_BGOFF);
|
||||
ure_ocp_reg_write(sc, URE_OCP_POWER_CFG,
|
||||
ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) |
|
||||
URE_EN_10M_PLLOFF);
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE);
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13);
|
||||
ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA,
|
||||
ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) |
|
||||
URE_PFM_PWM_SWITCH);
|
||||
|
||||
/* Enable LPF corner auto tune. */
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG);
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f);
|
||||
|
||||
/* Adjust 10M amplitude. */
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1);
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af);
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2);
|
||||
ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208);
|
||||
}
|
||||
|
||||
ure_reset(sc);
|
||||
|
||||
ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0);
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*-
|
||||
* Copyright (c) 2015 Kevin Lo <kevlo@FreeBSD.org>
|
||||
* Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org>
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -86,7 +86,7 @@
|
||||
#define URE_PLA_OCP_GPHY_BASE 0xe86c
|
||||
#define URE_PLA_TELLYCNT 0xe890
|
||||
#define URE_PLA_SFF_STS_7 0xe8de
|
||||
#define URE_PLA_PHYSTATUS 0xe908
|
||||
#define URE_GMEDIASTAT 0xe908
|
||||
|
||||
#define URE_USB_USB2PHY 0xb41e
|
||||
#define URE_USB_SSPHYLINK2 0xb428
|
||||
@ -424,10 +424,15 @@ struct ure_softc {
|
||||
|
||||
u_int sc_flags;
|
||||
#define URE_FLAG_LINK 0x0001
|
||||
#define URE_FLAG_8152 0x1000 /* RTL8152 */
|
||||
|
||||
u_int sc_chip;
|
||||
#define URE_CHIP_VER_4C00 0x01
|
||||
#define URE_CHIP_VER_4C10 0x02
|
||||
#define URE_CHIP_VER_5C00 0x04
|
||||
#define URE_CHIP_VER_5C10 0x08
|
||||
#define URE_CHIP_VER_5C20 0x10
|
||||
#define URE_CHIP_VER_5C30 0x20
|
||||
};
|
||||
|
||||
#define URE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user