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Cleanup virtual device mapping some more:
o improves understandability by replacing numerous relative address calculations with fixed addresses; everything should now match up more easily with the vm layout shown at the top of the file o move the expansion bus chip select regions to be contiguous with the expansion bus configuration area; this is not exploited right now but allows map consolidation in the future o leave a gap between the expansion bus regions and the pci config space in case we want to map more exp bus cs regions Reviewed by: imp, thompsa
This commit is contained in:
Sam Leffler
parent
baeef61449
commit
a3ae8e385c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=189463
@ -88,22 +88,27 @@
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* SDRAM/DDR Memory Controller
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* F020 0000 --------------------------- IXP425_MCU_VBASE
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*
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* F001 7000 EHCI USB 2 (IXP435)
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* F001 6000 EHCI USB 1 (IXP435)
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* F020 6000 ---------------------------
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* EHCI USB 2 (IXP435)
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* F001 D000 --------------------------- IXP435_USB2_VBASE
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* EHCI USB 1 (IXP435)
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* F001 C000 --------------------------- IXP435_USB1_VBASE
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* Queue manager
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* F001 2000 --------------------------- IXP425_QMGR_VBASE
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* F001 8000 --------------------------- IXP425_QMGR_VBASE
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* PCI Configuration and Status
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* F001 1000 --------------------------- IXP425_PCI_VBASE
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* F001 7000 --------------------------- IXP425_PCI_VBASE
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*
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* (NB: gap for future addition of EXP CS5-7)
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* F001 4000 Expansion Bus Chip Select 4
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* F001 3000 Expansion Bus Chip Select 3
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* F001 2000 Expansion Bus Chip Select 2
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* F001 1000 Expansion Bus Chip Select 1
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* Expansion Bus Configuration
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* F001 0000 --------------------------- IXP425_EXP_VBASE
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* F000 F000 Expansion Bus Chip Select 4
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* F000 E000 Expansion Bus Chip Select 3
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* F000 D000 Expansion Bus Chip Select 2
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* F000 C000 Expansion Bus Chip Select 1
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*
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* F000 C000 MAC-A (IXP435)
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* F000 B000 USB (option on IXP425)
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* F000 A000 MAC-B (IXP425) | MAC-C (IXP435)
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* F000 9000 MAC-A
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* F000 9000 MAC-A (IXP425)
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* F000 8000 NPE-C
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* F000 7000 NPE-B (IXP425)
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* F000 6000 NPE-A
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@ -125,8 +130,7 @@
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#define IXP425_IO_HWBASE 0xc8000000UL
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#define IXP425_IO_SIZE 0x00010000UL
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/* Offset */
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/* Physical/Virtual addresss offsets */
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#define IXP425_UART0_OFFSET 0x00000000UL
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#define IXP425_UART1_OFFSET 0x00001000UL
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#define IXP425_PMC_OFFSET 0x00002000UL
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@ -139,6 +143,7 @@
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#define IXP425_MAC_B_OFFSET 0x00009000UL /* Ethernet MAC on NPE-B */
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#define IXP425_MAC_C_OFFSET 0x0000a000UL /* Ethernet MAC on NPE-C */
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#define IXP425_USB_OFFSET 0x0000b000UL
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#define IXP435_MAC_A_OFFSET 0x0000c000UL /* Ethernet MAC on NPE-A */
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#define IXP425_REG_SIZE 0x1000
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@ -322,9 +327,8 @@
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* Expansion Bus Configuration Space.
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*/
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#define IXP425_EXP_HWBASE 0xc4000000UL
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#define IXP425_EXP_VBASE (IXP425_IO_VBASE + IXP425_IO_SIZE)
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/* 0xf0010000 */
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#define IXP425_EXP_SIZE IXP425_REG_SIZE /* 0x1000 */
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#define IXP425_EXP_VBASE 0xf0010000UL
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#define IXP425_EXP_SIZE 0x1000
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/* offset */
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#define EXP_TIMING_CS0_OFFSET 0x0000
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@ -436,9 +440,8 @@
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* PCI
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*/
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#define IXP425_PCI_HWBASE 0xc0000000
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#define IXP425_PCI_VBASE (IXP425_EXP_VBASE + IXP425_EXP_SIZE)
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/* 0xf0011000 */
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#define IXP425_PCI_SIZE IXP425_REG_SIZE /* 0x1000 */
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#define IXP425_PCI_VBASE 0xf0017000UL
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#define IXP425_PCI_SIZE 0x1000
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#define IXP425_AHB_OFFSET 0x00000000UL /* AHB bus */
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@ -612,7 +615,7 @@
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* Queue Manager
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*/
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#define IXP425_QMGR_HWBASE 0x60000000UL
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#define IXP425_QMGR_VBASE (IXP425_PCI_VBASE + IXP425_PCI_SIZE)
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#define IXP425_QMGR_VBASE 0xf0018000UL
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#define IXP425_QMGR_SIZE 0x4000
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/*
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@ -650,24 +653,26 @@
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#define IXP425_EXP_BUS_CSx_HWBASE(i) \
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(IXP425_EXP_BUS_HWBASE + (i)*IXP425_EXP_BUS_SIZE)
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#define IXP425_EXP_BUS_CSx_SIZE 0x1000
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#define IXP425_EXP_BUS_CSx_VBASE(i) \
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(IXP425_MAC_B_VBASE + (i)*IXP425_MAC_B_SIZE)
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(0xF0011000UL + (((i)-1)*IXP425_EXP_BUS_CSx_SIZE))
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/* NB: CS0 is special; it maps flash */
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#define IXP425_EXP_BUS_CS0_HWBASE IXP425_EXP_BUS_CSx_HWBASE(0)
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#define IXP425_EXP_BUS_CS0_VBASE 0xFD000000UL
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#define IXP425_EXP_BUS_CS0_SIZE 0x01000000 /* NB: 16M */
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#define IXP425_EXP_BUS_CS1_HWBASE IXP425_EXP_BUS_CSx_HWBASE(1)
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#define IXP425_EXP_BUS_CS1_VBASE IXP425_EXP_BUS_CSx_VBASE(1)
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#define IXP425_EXP_BUS_CS1_SIZE 0x1000
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#define IXP425_EXP_BUS_CS1_SIZE IXP425_EXP_BUS_CSx_SIZE
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#define IXP425_EXP_BUS_CS2_HWBASE IXP425_EXP_BUS_CSx_HWBASE(2)
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#define IXP425_EXP_BUS_CS2_VBASE IXP425_EXP_BUS_CSx_VBASE(2)
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#define IXP425_EXP_BUS_CS2_SIZE 0x1000
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#define IXP425_EXP_BUS_CS2_SIZE IXP425_EXP_BUS_CSx_SIZE
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#define IXP425_EXP_BUS_CS3_HWBASE IXP425_EXP_BUS_CSx_HWBASE(3)
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#define IXP425_EXP_BUS_CS3_VBASE IXP425_EXP_BUS_CSx_VBASE(3)
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#define IXP425_EXP_BUS_CS3_SIZE 0x1000
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#define IXP425_EXP_BUS_CS3_SIZE IXP425_EXP_BUS_CSx_SIZE
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#define IXP425_EXP_BUS_CS4_HWBASE IXP425_EXP_BUS_CSx_HWBASE(4)
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#define IXP425_EXP_BUS_CS4_VBASE IXP425_EXP_BUS_CSx_VBASE(4)
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#define IXP425_EXP_BUS_CS4_SIZE 0x1000
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#define IXP425_EXP_BUS_CS4_SIZE IXP425_EXP_BUS_CSx_SIZE
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/* NB: not mapped (yet) */
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#define IXP425_EXP_BUS_CS5_HWBASE IXP425_EXP_BUS_CSx_HWBASE(5)
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@ -689,11 +694,11 @@
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#define CAMBRIA_CFSEL0_SIZE 0x40000
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#define IXP435_USB1_HWBASE 0xcd000000UL /* USB host controller 1 */
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#define IXP435_USB1_VBASE (IXP425_QMGR_VBASE + IXP425_QMGR_SIZE)
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#define IXP435_USB1_VBASE 0xf001C000UL
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#define IXP435_USB1_SIZE 0x1000 /* NB: only uses 0x300 */
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#define IXP435_USB2_HWBASE 0xce000000UL /* USB host controller 2 */
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#define IXP435_USB2_VBASE (IXP435_USB1_VBASE + IXP435_USB1_SIZE)
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#define IXP435_USB2_VBASE 0xf001D000UL
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#define IXP435_USB2_SIZE 0x1000 /* NB: only uses 0x300 */
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#endif /* _IXP425REG_H_ */
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