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Code Issues Releases Activity

Remove support for CPU_XSCALE_80200. None of our configs support it, and

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there wasn;t an option to enable it.

While here remove a check for CPU_ARM10 being defined as it has also been
removed.
This commit is contained in:
Andrew Turner 2015-03-30 09:29:45 +00:00
parent dcdebabdea
commit a3db11e053
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=280847
5 changed files with 16 additions and 64 deletions
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56
sys/arm/arm/cpufunc.c
View File

@ -60,11 +60,6 @@ __FBSDID("$FreeBSD$");
#include <machine/cpuconf.h>
#include <machine/cpufunc.h>
#ifdef CPU_XSCALE_80200
#include <arm/xscale/i80200/i80200reg.h>
#include <arm/xscale/i80200/i80200var.h>
#endif
#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
#include <arm/xscale/i80321/i80321reg.h>
#include <arm/xscale/i80321/i80321var.h>
@ -362,7 +357,7 @@ struct cpu_functions pj4bv7_cpufuncs = {
};
#endif /* CPU_MV_PJ4B */
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
#if defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
@ -427,7 +422,7 @@ struct cpu_functions xscale_cpufuncs = {
xscale_setup /* cpu setup */
};
#endif
/* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
/* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
#ifdef CPU_XSCALE_81342
@ -703,7 +698,7 @@ u_int cpu_reset_needs_v4_MMU_disable; /* flag used in locore.s */
#if defined(CPU_ARM9) || \
defined (CPU_ARM9E) || \
defined(CPU_ARM1176) || defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_ARM1176) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_FA526) || defined(CPU_MV_PJ4B) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
@ -957,47 +952,6 @@ set_cpufuncs()
}
#endif /* CPU_FA526 */
#ifdef CPU_XSCALE_80200
if (cputype == CPU_ID_80200) {
int rev = cpufunc_id() & CPU_ID_REVISION_MASK;
i80200_icu_init();
#if defined(XSCALE_CCLKCFG)
/*
* Crank CCLKCFG to maximum legal value.
*/
__asm __volatile ("mcr p14, 0, %0, c6, c0, 0"
:
: "r" (XSCALE_CCLKCFG));
#endif
/*
* XXX Disable ECC in the Bus Controller Unit; we
* don't really support it, yet. Clear any pending
* error indications.
*/
__asm __volatile("mcr p13, 0, %0, c0, c1, 0"
:
: "r" (BCUCTL_E0|BCUCTL_E1|BCUCTL_EV));
cpufuncs = xscale_cpufuncs;
/*
* i80200 errata: Step-A0 and A1 have a bug where
* D$ dirty bits are not cleared on "invalidate by
* address".
*
* Workaround: Clean cache line before invalidating.
*/
if (rev == 0 || rev == 1)
cpufuncs.cf_dcache_inv_range = xscale_cache_purgeD_rng;
cpu_reset_needs_v4_MMU_disable = 1; /* XScale needs it */
get_cachetype_cp15();
pmap_pte_init_xscale();
goto out;
}
#endif /* CPU_XSCALE_80200 */
#if defined(CPU_XSCALE_80321) || defined(CPU_XSCALE_80219)
if (cputype == CPU_ID_80321_400 || cputype == CPU_ID_80321_600 ||
cputype == CPU_ID_80321_400_B0 || cputype == CPU_ID_80321_600_B0 ||
@ -1417,7 +1371,7 @@ fa526_setup(void)
}
#endif /* CPU_FA526 */
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
#if defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
void
@ -1486,5 +1440,5 @@ xscale_setup(void)
__asm __volatile("mcr p15, 0, %0, c1, c0, 1"
: : "r" (auxctl));
}
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
#endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */

2
sys/arm/arm/elf_trampoline.c
View File

@ -67,7 +67,7 @@ extern void fa526_idcache_wbinv_all(void);
extern void armv5_ec_idcache_wbinv_all(void);
#elif defined(CPU_ARM1176)
#define cpu_idcache_wbinv_all armv6_idcache_wbinv_all
#elif defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
#elif defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219)
#define cpu_idcache_wbinv_all xscale_cache_purgeID

12
sys/arm/include/cpuconf.h
View File

@ -53,7 +53,6 @@
#define CPU_NTYPES (defined(CPU_ARM9) + \
defined(CPU_ARM9E) + \
defined(CPU_ARM1176) + \
defined(CPU_XSCALE_80200) + \
defined(CPU_XSCALE_80321) + \
defined(CPU_XSCALE_PXA2X0) + \
defined(CPU_FA526) + \
@ -71,8 +70,8 @@
#define ARM_ARCH_4 0
#endif
#if (defined(CPU_ARM9E) || defined(CPU_ARM10) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
#if (defined(CPU_ARM9E) || \
defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425))
#define ARM_ARCH_5 1
@ -146,8 +145,7 @@
* MMU, but also has several extensions which
* require different PTE layout to use.
*/
#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || \
defined(CPU_ARM10) || defined(CPU_FA526))
#if (defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_FA526))
#define ARM_MMU_GENERIC 1
#else
#define ARM_MMU_GENERIC 0
@ -165,7 +163,7 @@
#define ARM_MMU_V7 0
#endif
#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
#if (defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
#define ARM_MMU_XSCALE 1
@ -185,7 +183,7 @@
* ARM_XSCALE_PMU Performance Monitoring Unit on 80200 and 80321
*/
#if (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
#if (defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342))
#define ARM_XSCALE_PMU 1
#else

6
sys/arm/include/cpufunc.h
View File

@ -433,7 +433,7 @@ void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
#endif
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || \
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_80321) || \
defined(CPU_FA526) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
@ -447,7 +447,7 @@ void armv4_drain_writebuf (void);
void armv4_idcache_inv_all (void);
#endif
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
#if defined(CPU_XSCALE_80321) || \
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
void xscale_cpwait (void);
@ -487,7 +487,7 @@ void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
void xscale_context_switch (void);
void xscale_setup (void);
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
#endif /* CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
CPU_XSCALE_80219 */
#ifdef CPU_XSCALE_81342

4
sys/conf/files.arm
View File

@ -13,14 +13,14 @@ arm/arm/cpufunc_asm_arm9.S optional cpu_arm9
arm/arm/cpufunc_asm_arm10.S optional cpu_arm9e
arm/arm/cpufunc_asm_arm11.S optional cpu_arm1176
arm/arm/cpufunc_asm_arm11x6.S optional cpu_arm1176
arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_80200 | cpu_xscale_80321 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_80219 | cpu_xscale_81342
arm/arm/cpufunc_asm_armv4.S optional cpu_arm9 | cpu_arm9e | cpu_fa526 | cpu_xscale_80321 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_80219 | cpu_xscale_81342
arm/arm/cpufunc_asm_armv5_ec.S optional cpu_arm9e
arm/arm/cpufunc_asm_armv6.S optional cpu_arm1176
arm/arm/cpufunc_asm_armv7.S optional cpu_cortexa | cpu_krait | cpu_mv_pj4b
arm/arm/cpufunc_asm_fa526.S optional cpu_fa526
arm/arm/cpufunc_asm_pj4b.S optional cpu_mv_pj4b
arm/arm/cpufunc_asm_sheeva.S optional cpu_arm9e
arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_80200 | cpu_xscale_80321 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_80219 | cpu_xscale_81342
arm/arm/cpufunc_asm_xscale.S optional cpu_xscale_80321 | cpu_xscale_pxa2x0 | cpu_xscale_ixp425 | cpu_xscale_80219 | cpu_xscale_81342
arm/arm/cpufunc_asm_xscale_c3.S optional cpu_xscale_81342
arm/arm/cpuinfo.c standard
arm/arm/cpu_asm-v6.S optional armv6