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igc: Remove non-existent legacy absolute and packet timers
igc, derived from igb, does not use these registers. All interrupt timing is governed by EITR or LLI and driven by write-back. MFC after: 1 week Sponsored by: BBOX.io
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1e3b1870ad
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a40ecb6f74
@ -121,9 +121,6 @@ static int igc_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
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static int igc_get_rs(SYSCTL_HANDLER_ARGS);
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static void igc_print_debug_info(struct igc_adapter *);
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static int igc_is_valid_ether_addr(u8 *);
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static int igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS);
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static void igc_add_int_delay_sysctl(struct igc_adapter *, const char *,
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const char *, struct igc_int_delay_info *, int, int);
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/* Management and WOL Support */
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static void igc_get_hw_control(struct igc_adapter *);
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static void igc_release_hw_control(struct igc_adapter *);
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@ -211,12 +208,6 @@ static driver_t igc_if_driver = {
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* Tunable default values.
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*********************************************************************/
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#define IGC_TICKS_TO_USECS(ticks) ((1024 * (ticks) + 500) / 1000)
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#define IGC_USECS_TO_TICKS(usecs) ((1000 * (usecs) + 512) / 1024)
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#define MAX_INTS_PER_SEC 8000
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#define DEFAULT_ITR (1000000000/(MAX_INTS_PER_SEC * 256))
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/* Allow common code without TSO */
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#ifndef CSUM_TSO
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#define CSUM_TSO 0
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@ -229,22 +220,6 @@ static int igc_disable_crc_stripping = 0;
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SYSCTL_INT(_hw_igc, OID_AUTO, disable_crc_stripping, CTLFLAG_RDTUN,
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&igc_disable_crc_stripping, 0, "Disable CRC Stripping");
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static int igc_tx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TIDV_VAL);
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static int igc_rx_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RDTR_VAL);
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SYSCTL_INT(_hw_igc, OID_AUTO, tx_int_delay, CTLFLAG_RDTUN, &igc_tx_int_delay_dflt,
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0, "Default transmit interrupt delay in usecs");
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SYSCTL_INT(_hw_igc, OID_AUTO, rx_int_delay, CTLFLAG_RDTUN, &igc_rx_int_delay_dflt,
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0, "Default receive interrupt delay in usecs");
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static int igc_tx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_TADV_VAL);
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static int igc_rx_abs_int_delay_dflt = IGC_TICKS_TO_USECS(IGC_RADV_VAL);
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SYSCTL_INT(_hw_igc, OID_AUTO, tx_abs_int_delay, CTLFLAG_RDTUN,
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&igc_tx_abs_int_delay_dflt, 0,
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"Default transmit interrupt delay limit in usecs");
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SYSCTL_INT(_hw_igc, OID_AUTO, rx_abs_int_delay, CTLFLAG_RDTUN,
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&igc_rx_abs_int_delay_dflt, 0,
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"Default receive interrupt delay limit in usecs");
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static int igc_smart_pwr_down = false;
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SYSCTL_INT(_hw_igc, OID_AUTO, smart_pwr_down, CTLFLAG_RDTUN, &igc_smart_pwr_down,
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0, "Set to true to leave smart power down enabled on newer adapters");
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@ -536,29 +511,6 @@ igc_if_attach_pre(if_ctx_t ctx)
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igc_setup_msix(ctx);
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igc_get_bus_info(hw);
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/* Set up some sysctls for the tunable interrupt delays */
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igc_add_int_delay_sysctl(adapter, "rx_int_delay",
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"receive interrupt delay in usecs", &adapter->rx_int_delay,
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IGC_REGISTER(hw, IGC_RDTR), igc_rx_int_delay_dflt);
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igc_add_int_delay_sysctl(adapter, "tx_int_delay",
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"transmit interrupt delay in usecs", &adapter->tx_int_delay,
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IGC_REGISTER(hw, IGC_TIDV), igc_tx_int_delay_dflt);
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igc_add_int_delay_sysctl(adapter, "rx_abs_int_delay",
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"receive interrupt delay limit in usecs",
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&adapter->rx_abs_int_delay,
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IGC_REGISTER(hw, IGC_RADV),
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igc_rx_abs_int_delay_dflt);
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igc_add_int_delay_sysctl(adapter, "tx_abs_int_delay",
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"transmit interrupt delay limit in usecs",
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&adapter->tx_abs_int_delay,
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IGC_REGISTER(hw, IGC_TADV),
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igc_tx_abs_int_delay_dflt);
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igc_add_int_delay_sysctl(adapter, "itr",
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"interrupt delay limit in usecs/4",
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&adapter->tx_itr,
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IGC_REGISTER(hw, IGC_ITR),
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DEFAULT_ITR);
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hw->mac.autoneg = DO_AUTO_NEG;
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hw->phy.autoneg_wait_to_complete = false;
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hw->phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
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@ -2015,12 +1967,6 @@ igc_initialize_receive_unit(if_ctx_t ctx)
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if (!igc_disable_crc_stripping)
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rctl |= IGC_RCTL_SECRC;
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/*
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* Set the interrupt throttling rate. Value is calculated
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* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns)
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*/
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IGC_WRITE_REG(hw, IGC_ITR, DEFAULT_ITR);
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rxcsum = IGC_READ_REG(hw, IGC_RXCSUM);
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if (if_getcapenable(ifp) & IFCAP_RXCSUM) {
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rxcsum |= IGC_RXCSUM_CRCOFL;
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@ -2717,61 +2663,6 @@ igc_print_nvm_info(struct igc_adapter *adapter)
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printf("\n");
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}
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static int
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igc_sysctl_int_delay(SYSCTL_HANDLER_ARGS)
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{
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struct igc_int_delay_info *info;
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struct igc_adapter *adapter;
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u32 regval;
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int error, usecs, ticks;
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info = (struct igc_int_delay_info *) arg1;
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usecs = info->value;
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error = sysctl_handle_int(oidp, &usecs, 0, req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (usecs < 0 || usecs > IGC_TICKS_TO_USECS(65535))
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return (EINVAL);
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info->value = usecs;
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ticks = IGC_USECS_TO_TICKS(usecs);
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if (info->offset == IGC_ITR) /* units are 256ns here */
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ticks *= 4;
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adapter = info->adapter;
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regval = IGC_READ_OFFSET(&adapter->hw, info->offset);
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regval = (regval & ~0xffff) | (ticks & 0xffff);
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/* Handle a few special cases. */
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switch (info->offset) {
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case IGC_RDTR:
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break;
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case IGC_TIDV:
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if (ticks == 0) {
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adapter->txd_cmd &= ~IGC_TXD_CMD_IDE;
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/* Don't write 0 into the TIDV register. */
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regval++;
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} else
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adapter->txd_cmd |= IGC_TXD_CMD_IDE;
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break;
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}
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IGC_WRITE_OFFSET(&adapter->hw, info->offset, regval);
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return (0);
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}
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static void
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igc_add_int_delay_sysctl(struct igc_adapter *adapter, const char *name,
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const char *description, struct igc_int_delay_info *info,
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int offset, int value)
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{
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info->adapter = adapter;
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info->offset = offset;
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info->value = value;
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SYSCTL_ADD_PROC(device_get_sysctl_ctx(adapter->dev),
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SYSCTL_CHILDREN(device_get_sysctl_tree(adapter->dev)),
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OID_AUTO, name, CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
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info, 0, igc_sysctl_int_delay, "I", description);
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}
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/*
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* Set flow control using sysctl:
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* Flow control values:
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@ -131,65 +131,6 @@
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#define IGC_DEFAULT_MULTI_RXD 4096
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#define IGC_MAX_RXD 4096
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/*
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* IGC_TIDV_VAL - Transmit Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value delays the generation of transmit interrupts in units of
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* 1.024 microseconds. Transmit interrupt reduction can improve CPU
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* efficiency if properly tuned for specific network traffic. If the
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* system is reporting dropped transmits, this value may be set too high
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* causing the driver to run out of available transmit descriptors.
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*/
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#define IGC_TIDV_VAL 64
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/*
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* IGC_TADV_VAL - Transmit Absolute Interrupt Delay Value
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* transmit interrupt is generated. Useful only if IGC_TIDV is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is sent on the wire within the set amount of time. Proper tuning,
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* along with IGC_TIDV_VAL, may improve traffic throughput in specific
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* network conditions.
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*/
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#define IGC_TADV_VAL 64
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/*
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* IGC_RDTR_VAL - Receive Interrupt Delay Timer (Packet Timer)
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* Valid Range: 0-65535 (0=off)
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* Default Value: 0
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* This value delays the generation of receive interrupts in units of 1.024
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* microseconds. Receive interrupt reduction can improve CPU efficiency if
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* properly tuned for specific network traffic. Increasing this value adds
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* extra latency to frame reception and can end up decreasing the throughput
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* of TCP traffic. If the system is reporting dropped receives, this value
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* may be set too high, causing the driver to run out of available receive
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* descriptors.
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*
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* CAUTION: When setting IGC_RDTR to a value other than 0, adapters
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* may hang (stop transmitting) under certain network conditions.
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* If this occurs a WATCHDOG message is logged in the system
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* event log. In addition, the controller is automatically reset,
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* restoring the network connection. To eliminate the potential
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* for the hang ensure that IGC_RDTR is set to 0.
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*/
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#define IGC_RDTR_VAL 0
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/*
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* Receive Interrupt Absolute Delay Timer
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* Valid Range: 0-65535 (0=off)
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* Default Value: 64
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* This value, in units of 1.024 microseconds, limits the delay in which a
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* receive interrupt is generated. Useful only if IGC_RDTR is non-zero,
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* this value ensures that an interrupt is generated after the initial
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* packet is received within the set amount of time. Proper tuning,
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* along with IGC_RDTR, may improve traffic throughput in specific network
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* conditions.
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*/
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#define IGC_RADV_VAL 64
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/*
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* This parameter controls whether or not autonegotation is enabled.
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* 0 - Disable autonegotiation
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@ -27,7 +27,6 @@
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#define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
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#define IGC_VET 0x00038 /* VLAN Ether Type - RW */
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#define IGC_ICR 0x01500 /* Intr Cause Read - RC/W1C */
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#define IGC_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
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#define IGC_ICS 0x01504 /* Intr Cause Set - WO */
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#define IGC_IMS 0x01508 /* Intr Mask Set/Read - RW */
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#define IGC_IMC 0x0150C /* Intr Mask Clear - WO */
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@ -78,8 +77,6 @@
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#define IGC_FCRTV 0x02460 /* Flow Control Refresh Timer Value - RW */
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/* Split and Replication Rx Control - RW */
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#define IGC_RXPBS 0x02404 /* Rx Packet Buffer Size - RW */
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#define IGC_RDTR 0x02820 /* Rx Delay Timer - RW */
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#define IGC_RADV 0x0282C /* Rx Interrupt Absolute Delay Timer - RW */
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/* Shadow Ram Write Register - RW */
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#define IGC_SRWR 0x12018
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#define IGC_EEC_REG 0x12010
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@ -148,8 +145,6 @@
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#define IGC_FFVT_REG(_i) (0x09800 + ((_i) * 8))
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#define IGC_FFLT_REG(_i) (0x05F00 + ((_i) * 8))
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#define IGC_TXPBS 0x03404 /* Tx Packet Buffer Size - RW */
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#define IGC_TIDV 0x03820 /* Tx Interrupt Delay Value - RW */
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#define IGC_TADV 0x0382C /* Tx Interrupt Absolute Delay Val - RW */
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/* Statistics Register Descriptions */
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#define IGC_CRCERRS 0x04000 /* CRC Error Count - R/clr */
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#define IGC_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
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