mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-18 10:35:55 +00:00
Update em(4) with D3162 after testing further on hardware that failed
to attach with the last version of this commit. This commit fixes attach failures on "ICH8" class devices via modifications to e1000_init_nvm_params_ich8lan() - Fix compiler warning in 80003es2lan.c - Add return value handler for e1000_*_kmrn_reg_80003es2lan - Fix usage of DEBUGOUT - Remove unnecessary variable initializations. - Removed unused variables (complaints from gcc). - Edit defines in 82571.h. - Add workaround for igb hw errata. - Shared code changes for Skylake/I219 support. - Remove unused OBFF and LTR functions. Tested by some of the folks that reported breakage in previous incarnation. Thanks to AllanJude, gjb, gnn, tijl for tempting fate with their machines. Submitted by: erj@freebsd.org MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D3162
This commit is contained in:
Sean Bruno
parent
636b8d937e
commit
a44aa8e030
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=287762
@ -851,11 +851,17 @@ static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
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e1000_release_phy_80003es2lan(hw);
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/* Disable IBIST slave mode (far-end loopback) */
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e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
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&kum_reg_data);
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kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
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e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
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kum_reg_data);
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ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_INBAND_PARAM, &kum_reg_data);
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if (!ret_val) {
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kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_INBAND_PARAM,
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kum_reg_data);
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if (ret_val)
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DEBUGOUT("Error disabling far-end loopback\n");
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} else
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DEBUGOUT("Error disabling far-end loopback\n");
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ret_val = e1000_get_auto_rd_done_generic(hw);
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if (ret_val)
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@ -911,11 +917,18 @@ static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
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return ret_val;
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/* Disable IBIST slave mode (far-end loopback) */
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e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
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&kum_reg_data);
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kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
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e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
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kum_reg_data);
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ret_val =
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e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
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&kum_reg_data);
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if (!ret_val) {
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kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
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ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
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E1000_KMRNCTRLSTA_INBAND_PARAM,
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kum_reg_data);
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if (ret_val)
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DEBUGOUT("Error disabling far-end loopback\n");
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} else
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DEBUGOUT("Error disabling far-end loopback\n");
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/* Set the transmit descriptor write-back policy */
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reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
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@ -66,7 +66,7 @@ static s32 e1000_read_mac_addr_82540(struct e1000_hw *hw);
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static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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phy->addr = 1;
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phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
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@ -329,7 +329,7 @@ static s32 e1000_init_hw_82540(struct e1000_hw *hw)
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{
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struct e1000_mac_info *mac = &hw->mac;
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u32 txdctl, ctrl_ext;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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u16 i;
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DEBUGFUNC("e1000_init_hw_82540");
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@ -411,7 +411,7 @@ static s32 e1000_init_hw_82540(struct e1000_hw *hw)
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static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
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{
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u32 ctrl;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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u16 data;
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DEBUGFUNC("e1000_setup_copper_link_82540");
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@ -498,7 +498,7 @@ static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
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**/
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static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
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{
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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u16 nvm_data;
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DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
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@ -528,7 +528,7 @@ static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
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**/
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static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
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{
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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u16 default_page = 0;
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u16 phy_data;
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@ -85,7 +85,7 @@ static const u16 e1000_igp_cable_length_table[] = {
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static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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DEBUGFUNC("e1000_init_phy_params_82541");
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@ -295,7 +295,7 @@ void e1000_init_function_pointers_82541(struct e1000_hw *hw)
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**/
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static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
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{
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u32 ledctl, ctrl, icr, manc;
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u32 ledctl, ctrl, manc;
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DEBUGFUNC("e1000_reset_hw_82541");
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@ -317,6 +317,7 @@ static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
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/* Must reset the Phy before resetting the MAC */
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if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
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E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
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E1000_WRITE_FLUSH(hw);
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msec_delay(5);
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}
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@ -359,7 +360,7 @@ static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
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E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
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/* Clear any pending interrupt events. */
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icr = E1000_READ_REG(hw, E1000_ICR);
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E1000_READ_REG(hw, E1000_ICR);
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return E1000_SUCCESS;
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}
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@ -317,7 +317,7 @@ static s32 e1000_init_hw_82542(struct e1000_hw *hw)
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static s32 e1000_setup_link_82542(struct e1000_hw *hw)
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{
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struct e1000_mac_info *mac = &hw->mac;
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s32 ret_val = E1000_SUCCESS;
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s32 ret_val;
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DEBUGFUNC("e1000_setup_link_82542");
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@ -565,7 +565,7 @@ static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
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*
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* Reads the device MAC address from the EEPROM and stores the value.
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**/
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static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
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s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
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{
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s32 ret_val = E1000_SUCCESS;
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u16 offset, nvm_data, i;
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@ -900,7 +900,7 @@ static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
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**/
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static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
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{
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u32 ctrl, icr;
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u32 ctrl;
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s32 ret_val = E1000_SUCCESS;
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DEBUGFUNC("e1000_reset_hw_82543");
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@ -942,7 +942,7 @@ static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
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/* Masking off and clearing any pending interrupts */
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E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
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icr = E1000_READ_REG(hw, E1000_ICR);
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E1000_READ_REG(hw, E1000_ICR);
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return ret_val;
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}
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@ -50,9 +50,10 @@
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#define E1000_EIAC_82574 0x000DC /* Ext. Interrupt Auto Clear - RW */
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#define E1000_EIAC_MASK_82574 0x01F00000
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#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
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#define E1000_IVAR_INT_ALLOC_VALID 0x8
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#define E1000_RXCFGL 0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
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/* Manageability Operation Mode mask */
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#define E1000_NVM_INIT_CTRL2_MNGM 0x6000
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#define E1000_BASE1000T_STATUS 10
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#define E1000_IDLE_ERROR_COUNT_MASK 0xFF
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@ -1235,7 +1235,7 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
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DEBUGFUNC("e1000_check_for_link_media_swap");
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/* Check the copper medium. */
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/* Check for copper. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
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if (ret_val)
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return ret_val;
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@ -1247,7 +1247,7 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
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if (data & E1000_M88E1112_STATUS_LINK)
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port = E1000_MEDIA_PORT_COPPER;
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/* Check the other medium. */
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/* Check for other. */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
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if (ret_val)
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return ret_val;
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@ -1256,11 +1256,6 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
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if (ret_val)
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return ret_val;
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/* reset page to 0 */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
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if (ret_val)
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return ret_val;
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if (data & E1000_M88E1112_STATUS_LINK)
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port = E1000_MEDIA_PORT_OTHER;
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@ -1268,8 +1263,20 @@ static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
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if (port && (hw->dev_spec._82575.media_port != port)) {
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hw->dev_spec._82575.media_port = port;
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hw->dev_spec._82575.media_changed = TRUE;
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}
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if (port == E1000_MEDIA_PORT_COPPER) {
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/* reset page to 0 */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
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if (ret_val)
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return ret_val;
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e1000_check_for_link_82575(hw);
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} else {
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ret_val = e1000_check_for_link_82575(hw);
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e1000_check_for_link_82575(hw);
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/* reset page to 0 */
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ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
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if (ret_val)
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return ret_val;
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}
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return E1000_SUCCESS;
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@ -2136,7 +2143,13 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
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u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
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int i, ms_wait;
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DEBUGFUNC("e1000_rx_fifo_workaround_82575");
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DEBUGFUNC("e1000_rx_fifo_flush_82575");
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/* disable IPv6 options as per hardware errata */
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rfctl = E1000_READ_REG(hw, E1000_RFCTL);
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rfctl |= E1000_RFCTL_IPV6_EX_DIS;
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E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
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if (hw->mac.type != e1000_82575 ||
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!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
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return;
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@ -2164,7 +2177,6 @@ void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
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* incoming packets are rejected. Set enable and wait 2ms so that
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* any packet that was coming in as RCTL.EN was set is flushed
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*/
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rfctl = E1000_READ_REG(hw, E1000_RFCTL);
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E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
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rlpml = E1000_READ_REG(hw, E1000_RLPML);
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@ -2894,11 +2906,13 @@ s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw)
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/**
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* e1000_set_eee_i350 - Enable/disable EEE support
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* @hw: pointer to the HW structure
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* @adv1g: boolean flag enabling 1G EEE advertisement
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* @adv100m: boolean flag enabling 100M EEE advertisement
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*
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* Enable/disable EEE based on setting in dev_spec structure.
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*
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**/
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s32 e1000_set_eee_i350(struct e1000_hw *hw)
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s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
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{
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u32 ipcnfg, eeer;
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@ -2914,7 +2928,16 @@ s32 e1000_set_eee_i350(struct e1000_hw *hw)
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if (!(hw->dev_spec._82575.eee_disable)) {
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u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
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ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
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if (adv100M)
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ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
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else
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ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
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if (adv1G)
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ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
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else
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ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
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eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
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E1000_EEER_LPI_FC);
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@ -2938,11 +2961,13 @@ s32 e1000_set_eee_i350(struct e1000_hw *hw)
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/**
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* e1000_set_eee_i354 - Enable/disable EEE support
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* @hw: pointer to the HW structure
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* @adv1g: boolean flag enabling 1G EEE advertisement
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* @adv100m: boolean flag enabling 100M EEE advertisement
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*
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* Enable/disable EEE legacy mode based on setting in dev_spec structure.
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*
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**/
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s32 e1000_set_eee_i354(struct e1000_hw *hw)
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s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
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{
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struct e1000_phy_info *phy = &hw->phy;
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s32 ret_val = E1000_SUCCESS;
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@ -2984,8 +3009,16 @@ s32 e1000_set_eee_i354(struct e1000_hw *hw)
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if (ret_val)
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goto out;
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phy_data |= E1000_EEE_ADV_100_SUPPORTED |
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E1000_EEE_ADV_1000_SUPPORTED;
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if (adv100M)
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phy_data |= E1000_EEE_ADV_100_SUPPORTED;
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else
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phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
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if (adv1G)
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phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
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else
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phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
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ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
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E1000_EEE_ADV_DEV_I354,
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phy_data);
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@ -495,8 +495,8 @@ void e1000_rlpml_set_vf(struct e1000_hw *, u16);
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s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type type);
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u16 e1000_rxpbs_adjust_82580(u32 data);
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s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data);
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s32 e1000_set_eee_i350(struct e1000_hw *);
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s32 e1000_set_eee_i354(struct e1000_hw *);
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s32 e1000_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M);
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s32 e1000_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M);
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s32 e1000_get_eee_status_i354(struct e1000_hw *, bool *);
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s32 e1000_initialize_M88E1512_phy(struct e1000_hw *hw);
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@ -299,6 +299,12 @@ s32 e1000_set_mac_type(struct e1000_hw *hw)
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case E1000_DEV_ID_PCH_I218_V3:
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mac->type = e1000_pch_lpt;
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break;
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case E1000_DEV_ID_PCH_SPT_I219_LM:
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case E1000_DEV_ID_PCH_SPT_I219_V:
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case E1000_DEV_ID_PCH_SPT_I219_LM2:
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case E1000_DEV_ID_PCH_SPT_I219_V2:
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mac->type = e1000_pch_spt;
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break;
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case E1000_DEV_ID_82575EB_COPPER:
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case E1000_DEV_ID_82575EB_FIBER_SERDES:
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case E1000_DEV_ID_82575GB_QUAD_COPPER:
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@ -449,6 +455,7 @@ s32 e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device)
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case e1000_pchlan:
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case e1000_pch2lan:
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case e1000_pch_lpt:
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case e1000_pch_spt:
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e1000_init_function_pointers_ich8lan(hw);
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break;
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case e1000_82575:
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@ -928,21 +935,6 @@ s32 e1000_mng_enable_host_if(struct e1000_hw *hw)
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return e1000_mng_enable_host_if_generic(hw);
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}
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/**
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* e1000_set_obff_timer - Set Optimized Buffer Flush/Fill timer
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* @hw: pointer to the HW structure
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* @itr: u32 indicating itr value
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*
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* Set the OBFF timer based on the given interrupt rate.
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**/
|
||||
s32 e1000_set_obff_timer(struct e1000_hw *hw, u32 itr)
|
||||
{
|
||||
if (hw->mac.ops.set_obff_timer)
|
||||
return hw->mac.ops.set_obff_timer(hw, itr);
|
||||
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_check_reset_block - Verifies PHY can be reset
|
||||
* @hw: pointer to the HW structure
|
||||
@ -1215,6 +1207,21 @@ s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size)
|
||||
return e1000_read_pba_length_generic(hw, pba_num_size);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_read_pba_num - Read device part number
|
||||
* @hw: pointer to the HW structure
|
||||
* @pba_num: pointer to device part number
|
||||
*
|
||||
* Reads the product board assembly (PBA) number from the EEPROM and stores
|
||||
* the value in pba_num.
|
||||
* Currently no func pointer exists and all implementations are handled in the
|
||||
* generic version of this function.
|
||||
**/
|
||||
s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
|
||||
{
|
||||
return e1000_read_pba_num_generic(hw, pba_num);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_validate_nvm_checksum - Verifies NVM (EEPROM) checksum
|
||||
* @hw: pointer to the HW structure
|
||||
|
||||
@ -97,6 +97,7 @@ s32 e1000_phy_commit(struct e1000_hw *hw);
|
||||
void e1000_power_up_phy(struct e1000_hw *hw);
|
||||
void e1000_power_down_phy(struct e1000_hw *hw);
|
||||
s32 e1000_read_mac_addr(struct e1000_hw *hw);
|
||||
s32 e1000_read_pba_num(struct e1000_hw *hw, u32 *part_num);
|
||||
s32 e1000_read_pba_string(struct e1000_hw *hw, u8 *pba_num, u32 pba_num_size);
|
||||
s32 e1000_read_pba_length(struct e1000_hw *hw, u32 *pba_num_size);
|
||||
void e1000_reload_nvm(struct e1000_hw *hw);
|
||||
|
||||
@ -197,6 +197,8 @@
|
||||
#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
|
||||
#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */
|
||||
#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */
|
||||
#define E1000_RCTL_RDMTS_HEX 0x00010000
|
||||
#define E1000_RCTL_RDMTS1_HEX E1000_RCTL_RDMTS_HEX
|
||||
#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
|
||||
#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
|
||||
#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
|
||||
@ -565,9 +567,6 @@
|
||||
#define E1000_ICR_THS 0x00800000 /* ICR.THS: Thermal Sensor Event*/
|
||||
#define E1000_ICR_MDDET 0x10000000 /* Malicious Driver Detect */
|
||||
|
||||
#define E1000_ITR_MASK 0x000FFFFF /* ITR value bitfield */
|
||||
#define E1000_ITR_MULT 256 /* ITR mulitplier in nsec */
|
||||
|
||||
/* PBA ECC Register */
|
||||
#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */
|
||||
#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */
|
||||
@ -753,6 +752,12 @@
|
||||
#define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */
|
||||
#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */
|
||||
|
||||
/* HH Time Sync */
|
||||
#define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */
|
||||
#define E1000_TSYNCTXCTL_SYNC_COMP_ERR 0x20000000 /* sync err */
|
||||
#define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */
|
||||
#define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */
|
||||
|
||||
#define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
|
||||
#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
|
||||
#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00
|
||||
@ -1020,9 +1025,7 @@
|
||||
/* NVM Addressing bits based on type 0=small, 1=large */
|
||||
#define E1000_EECD_ADDR_BITS 0x00000400
|
||||
#define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
|
||||
#ifndef E1000_NVM_GRANT_ATTEMPTS
|
||||
#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */
|
||||
#endif
|
||||
#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */
|
||||
#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */
|
||||
#define E1000_EECD_SIZE_EX_SHIFT 11
|
||||
@ -1059,11 +1062,44 @@
|
||||
/* NVM Word Offsets */
|
||||
#define NVM_COMPAT 0x0003
|
||||
#define NVM_ID_LED_SETTINGS 0x0004
|
||||
#define NVM_VERSION 0x0005
|
||||
#define NVM_SERDES_AMPLITUDE 0x0006 /* SERDES output amplitude */
|
||||
#define NVM_PHY_CLASS_WORD 0x0007
|
||||
#define E1000_I210_NVM_FW_MODULE_PTR 0x0010
|
||||
#define E1000_I350_NVM_FW_MODULE_PTR 0x0051
|
||||
#define NVM_FUTURE_INIT_WORD1 0x0019
|
||||
#define NVM_ETRACK_WORD 0x0042
|
||||
#define NVM_ETRACK_HIWORD 0x0043
|
||||
#define NVM_COMB_VER_OFF 0x0083
|
||||
#define NVM_COMB_VER_PTR 0x003d
|
||||
|
||||
/* NVM version defines */
|
||||
#define NVM_MAJOR_MASK 0xF000
|
||||
#define NVM_MINOR_MASK 0x0FF0
|
||||
#define NVM_IMAGE_ID_MASK 0x000F
|
||||
#define NVM_COMB_VER_MASK 0x00FF
|
||||
#define NVM_MAJOR_SHIFT 12
|
||||
#define NVM_MINOR_SHIFT 4
|
||||
#define NVM_COMB_VER_SHFT 8
|
||||
#define NVM_VER_INVALID 0xFFFF
|
||||
#define NVM_ETRACK_SHIFT 16
|
||||
#define NVM_ETRACK_VALID 0x8000
|
||||
#define NVM_NEW_DEC_MASK 0x0F00
|
||||
#define NVM_HEX_CONV 16
|
||||
#define NVM_HEX_TENS 10
|
||||
|
||||
/* FW version defines */
|
||||
/* Offset of "Loader patch ptr" in Firmware Header */
|
||||
#define E1000_I350_NVM_FW_LOADER_PATCH_PTR_OFFSET 0x01
|
||||
/* Patch generation hour & minutes */
|
||||
#define E1000_I350_NVM_FW_VER_WORD1_OFFSET 0x04
|
||||
/* Patch generation month & day */
|
||||
#define E1000_I350_NVM_FW_VER_WORD2_OFFSET 0x05
|
||||
/* Patch generation year */
|
||||
#define E1000_I350_NVM_FW_VER_WORD3_OFFSET 0x06
|
||||
/* Patch major & minor numbers */
|
||||
#define E1000_I350_NVM_FW_VER_WORD4_OFFSET 0x07
|
||||
|
||||
#define NVM_MAC_ADDR 0x0000
|
||||
#define NVM_SUB_DEV_ID 0x000B
|
||||
#define NVM_SUB_VEN_ID 0x000C
|
||||
@ -1440,8 +1476,6 @@
|
||||
#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */
|
||||
#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */
|
||||
|
||||
#define E1000_DOBFFCTL_OBFFTHR_MASK 0x000000FF /* OBFF threshold */
|
||||
#define E1000_DOBFFCTL_EXIT_ACT_MASK 0x01000000 /* Exit active CB */
|
||||
|
||||
/* Proxy Filter Control */
|
||||
#define E1000_PROXYFC_D0 0x00000001 /* Enable offload in D0 */
|
||||
|
||||
@ -137,6 +137,10 @@ struct e1000_hw;
|
||||
#define E1000_DEV_ID_PCH_I218_V2 0x15A1
|
||||
#define E1000_DEV_ID_PCH_I218_LM3 0x15A2 /* Wildcat Point PCH */
|
||||
#define E1000_DEV_ID_PCH_I218_V3 0x15A3 /* Wildcat Point PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F /* Sunrise Point PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 /* Sunrise Point PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 /* Sunrise Point-H PCH */
|
||||
#define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 /* Sunrise Point-H PCH */
|
||||
#define E1000_DEV_ID_82576 0x10C9
|
||||
#define E1000_DEV_ID_82576_FIBER 0x10E6
|
||||
#define E1000_DEV_ID_82576_SERDES 0x10E7
|
||||
@ -222,6 +226,7 @@ enum e1000_mac_type {
|
||||
e1000_pchlan,
|
||||
e1000_pch2lan,
|
||||
e1000_pch_lpt,
|
||||
e1000_pch_spt,
|
||||
e1000_82575,
|
||||
e1000_82576,
|
||||
e1000_82580,
|
||||
@ -703,7 +708,6 @@ struct e1000_mac_operations {
|
||||
int (*rar_set)(struct e1000_hw *, u8*, u32);
|
||||
s32 (*read_mac_addr)(struct e1000_hw *);
|
||||
s32 (*validate_mdi_setting)(struct e1000_hw *);
|
||||
s32 (*set_obff_timer)(struct e1000_hw *, u32);
|
||||
s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
|
||||
void (*release_swfw_sync)(struct e1000_hw *, u16);
|
||||
};
|
||||
@ -805,7 +809,7 @@ struct e1000_mac_info {
|
||||
enum e1000_serdes_link_state serdes_link_state;
|
||||
bool serdes_has_link;
|
||||
bool tx_pkt_filtering;
|
||||
u32 max_frame_size;
|
||||
u32 max_frame_size;
|
||||
};
|
||||
|
||||
struct e1000_phy_info {
|
||||
|
||||
@ -488,6 +488,105 @@ static s32 e1000_read_invm_i210(struct e1000_hw *hw, u16 offset,
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_read_invm_version - Reads iNVM version and image type
|
||||
* @hw: pointer to the HW structure
|
||||
* @invm_ver: version structure for the version read
|
||||
*
|
||||
* Reads iNVM version and image type.
|
||||
**/
|
||||
s32 e1000_read_invm_version(struct e1000_hw *hw,
|
||||
struct e1000_fw_version *invm_ver)
|
||||
{
|
||||
u32 *record = NULL;
|
||||
u32 *next_record = NULL;
|
||||
u32 i = 0;
|
||||
u32 invm_dword = 0;
|
||||
u32 invm_blocks = E1000_INVM_SIZE - (E1000_INVM_ULT_BYTES_SIZE /
|
||||
E1000_INVM_RECORD_SIZE_IN_BYTES);
|
||||
u32 buffer[E1000_INVM_SIZE];
|
||||
s32 status = -E1000_ERR_INVM_VALUE_NOT_FOUND;
|
||||
u16 version = 0;
|
||||
|
||||
DEBUGFUNC("e1000_read_invm_version");
|
||||
|
||||
/* Read iNVM memory */
|
||||
for (i = 0; i < E1000_INVM_SIZE; i++) {
|
||||
invm_dword = E1000_READ_REG(hw, E1000_INVM_DATA_REG(i));
|
||||
buffer[i] = invm_dword;
|
||||
}
|
||||
|
||||
/* Read version number */
|
||||
for (i = 1; i < invm_blocks; i++) {
|
||||
record = &buffer[invm_blocks - i];
|
||||
next_record = &buffer[invm_blocks - i + 1];
|
||||
|
||||
/* Check if we have first version location used */
|
||||
if ((i == 1) && ((*record & E1000_INVM_VER_FIELD_ONE) == 0)) {
|
||||
version = 0;
|
||||
status = E1000_SUCCESS;
|
||||
break;
|
||||
}
|
||||
/* Check if we have second version location used */
|
||||
else if ((i == 1) &&
|
||||
((*record & E1000_INVM_VER_FIELD_TWO) == 0)) {
|
||||
version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
|
||||
status = E1000_SUCCESS;
|
||||
break;
|
||||
}
|
||||
/*
|
||||
* Check if we have odd version location
|
||||
* used and it is the last one used
|
||||
*/
|
||||
else if ((((*record & E1000_INVM_VER_FIELD_ONE) == 0) &&
|
||||
((*record & 0x3) == 0)) || (((*record & 0x3) != 0) &&
|
||||
(i != 1))) {
|
||||
version = (*next_record & E1000_INVM_VER_FIELD_TWO)
|
||||
>> 13;
|
||||
status = E1000_SUCCESS;
|
||||
break;
|
||||
}
|
||||
/*
|
||||
* Check if we have even version location
|
||||
* used and it is the last one used
|
||||
*/
|
||||
else if (((*record & E1000_INVM_VER_FIELD_TWO) == 0) &&
|
||||
((*record & 0x3) == 0)) {
|
||||
version = (*record & E1000_INVM_VER_FIELD_ONE) >> 3;
|
||||
status = E1000_SUCCESS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (status == E1000_SUCCESS) {
|
||||
invm_ver->invm_major = (version & E1000_INVM_MAJOR_MASK)
|
||||
>> E1000_INVM_MAJOR_SHIFT;
|
||||
invm_ver->invm_minor = version & E1000_INVM_MINOR_MASK;
|
||||
}
|
||||
/* Read Image Type */
|
||||
for (i = 1; i < invm_blocks; i++) {
|
||||
record = &buffer[invm_blocks - i];
|
||||
next_record = &buffer[invm_blocks - i + 1];
|
||||
|
||||
/* Check if we have image type in first location used */
|
||||
if ((i == 1) && ((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) {
|
||||
invm_ver->invm_img_type = 0;
|
||||
status = E1000_SUCCESS;
|
||||
break;
|
||||
}
|
||||
/* Check if we have image type in first location used */
|
||||
else if ((((*record & 0x3) == 0) &&
|
||||
((*record & E1000_INVM_IMGTYPE_FIELD) == 0)) ||
|
||||
((((*record & 0x3) != 0) && (i != 1)))) {
|
||||
invm_ver->invm_img_type =
|
||||
(*next_record & E1000_INVM_IMGTYPE_FIELD) >> 23;
|
||||
status = E1000_SUCCESS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_validate_nvm_checksum_i210 - Validate EEPROM checksum
|
||||
* @hw: pointer to the HW structure
|
||||
|
||||
@ -43,6 +43,8 @@ s32 e1000_write_nvm_srwr_i210(struct e1000_hw *hw, u16 offset,
|
||||
u16 words, u16 *data);
|
||||
s32 e1000_read_nvm_srrd_i210(struct e1000_hw *hw, u16 offset,
|
||||
u16 words, u16 *data);
|
||||
s32 e1000_read_invm_version(struct e1000_hw *hw,
|
||||
struct e1000_fw_version *invm_ver);
|
||||
s32 e1000_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
|
||||
void e1000_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
|
||||
s32 e1000_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr,
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -107,9 +107,25 @@
|
||||
|
||||
#define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100
|
||||
#define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200
|
||||
|
||||
#define E1000_FEXTNVM6_K1_OFF_ENABLE 0x80000000
|
||||
/* bit for disabling packet buffer read */
|
||||
#define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000
|
||||
#define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004
|
||||
#define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020
|
||||
#define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800
|
||||
#define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000
|
||||
#define E1000_FEXTNVM11_DISABLE_PB_READ 0x00000200
|
||||
#define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000
|
||||
|
||||
/* bit24: RXDCTL thresholds granularity: 0 - cache lines, 1 - descriptors */
|
||||
#define E1000_RXDCTL_THRESH_UNIT_DESC 0x01000000
|
||||
|
||||
#define NVM_SIZE_MULTIPLIER 4096 /*multiplier for NVMS field*/
|
||||
#define E1000_FLASH_BASE_ADDR 0xE000 /*offset of NVM access regs*/
|
||||
#define E1000_CTRL_EXT_NVMVS 0x3 /*NVM valid sector */
|
||||
#define E1000_SPT_B_STEP_REV 0x10 /*SPT B step Rev ID*/
|
||||
#define E1000_TARC0_CB_MULTIQ_2_REQ (1 << 29)
|
||||
#define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29)
|
||||
#define PCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL
|
||||
|
||||
#define E1000_ICH_RAR_ENTRIES 7
|
||||
@ -171,6 +187,8 @@
|
||||
|
||||
#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
|
||||
#define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */
|
||||
#define K1_ENTRY_LATENCY 0
|
||||
#define K1_MIN_TIME 1
|
||||
|
||||
/* SMBus Control Phy Register */
|
||||
#define CV_SMB_CTRL PHY_REG(769, 23)
|
||||
@ -281,36 +299,13 @@
|
||||
/* Receive Address Initial CRC Calculation */
|
||||
#define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4))
|
||||
|
||||
/* Latency Tolerance Reporting */
|
||||
#define E1000_LTRV 0x000F8
|
||||
#define E1000_LTRV_VALUE_MASK 0x000003FF
|
||||
#define E1000_LTRV_SCALE_MAX 5
|
||||
#define E1000_LTRV_SCALE_FACTOR 5
|
||||
#define E1000_LTRV_SCALE_SHIFT 10
|
||||
#define E1000_LTRV_SCALE_MASK 0x00001C00
|
||||
#define E1000_LTRV_REQ_SHIFT 15
|
||||
#define E1000_LTRV_NOSNOOP_SHIFT 16
|
||||
#define E1000_LTRV_SEND (1 << 30)
|
||||
|
||||
/* Proprietary Latency Tolerance Reporting PCI Capability */
|
||||
#define E1000_PCI_LTR_CAP_LPT 0xA8
|
||||
|
||||
/* OBFF Control & Threshold Defines */
|
||||
#define E1000_SVCR_OFF_EN 0x00000001
|
||||
#define E1000_SVCR_OFF_MASKINT 0x00001000
|
||||
#define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000
|
||||
#define E1000_SVCR_OFF_TIMER_SHIFT 16
|
||||
#define E1000_SVT_OFF_HWM_MASK 0x0000001F
|
||||
|
||||
#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT)
|
||||
#define E1000_PCI_REVISION_ID_REG 0x08
|
||||
#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */
|
||||
void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
|
||||
bool state);
|
||||
void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
|
||||
void e1000_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
|
||||
void e1000_suspend_workarounds_ich8lan(struct e1000_hw *hw);
|
||||
void e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
|
||||
u32 e1000_resume_workarounds_pchlan(struct e1000_hw *hw);
|
||||
s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
|
||||
void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw);
|
||||
s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
|
||||
|
||||
@ -70,7 +70,6 @@ void e1000_init_mac_ops_generic(struct e1000_hw *hw)
|
||||
mac->ops.setup_link = e1000_null_ops_generic;
|
||||
mac->ops.get_link_up_info = e1000_null_link_info;
|
||||
mac->ops.check_for_link = e1000_null_ops_generic;
|
||||
mac->ops.set_obff_timer = e1000_null_set_obff_timer;
|
||||
/* Management */
|
||||
mac->ops.check_mng_mode = e1000_null_mng_mode;
|
||||
/* VLAN, MC, etc. */
|
||||
@ -155,17 +154,6 @@ int e1000_null_rar_set(struct e1000_hw E1000_UNUSEDARG *hw,
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_null_set_obff_timer - No-op function, return 0
|
||||
* @hw: pointer to the HW structure
|
||||
**/
|
||||
s32 e1000_null_set_obff_timer(struct e1000_hw E1000_UNUSEDARG *hw,
|
||||
u32 E1000_UNUSEDARG a)
|
||||
{
|
||||
DEBUGFUNC("e1000_null_set_obff_timer");
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_get_bus_info_pci_generic - Get PCI(x) bus information
|
||||
* @hw: pointer to the HW structure
|
||||
|
||||
@ -36,9 +36,7 @@
|
||||
#define _E1000_MAC_H_
|
||||
|
||||
void e1000_init_mac_ops_generic(struct e1000_hw *hw);
|
||||
#ifndef E1000_REMOVED
|
||||
#define E1000_REMOVED(a) (0)
|
||||
#endif /* E1000_REMOVED */
|
||||
void e1000_null_mac_generic(struct e1000_hw *hw);
|
||||
s32 e1000_null_ops_generic(struct e1000_hw *hw);
|
||||
s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d);
|
||||
@ -46,7 +44,6 @@ bool e1000_null_mng_mode(struct e1000_hw *hw);
|
||||
void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);
|
||||
void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b);
|
||||
int e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);
|
||||
s32 e1000_null_set_obff_timer(struct e1000_hw *hw, u32 a);
|
||||
s32 e1000_blink_led_generic(struct e1000_hw *hw);
|
||||
s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw);
|
||||
s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw);
|
||||
|
||||
@ -930,6 +930,41 @@ s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size)
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_read_pba_num_generic - Read device part number
|
||||
* @hw: pointer to the HW structure
|
||||
* @pba_num: pointer to device part number
|
||||
*
|
||||
* Reads the product board assembly (PBA) number from the EEPROM and stores
|
||||
* the value in pba_num.
|
||||
**/
|
||||
s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
|
||||
{
|
||||
s32 ret_val;
|
||||
u16 nvm_data;
|
||||
|
||||
DEBUGFUNC("e1000_read_pba_num_generic");
|
||||
|
||||
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("NVM Read Error\n");
|
||||
return ret_val;
|
||||
} else if (nvm_data == NVM_PBA_PTR_GUARD) {
|
||||
DEBUGOUT("NVM Not Supported\n");
|
||||
return -E1000_NOT_IMPLEMENTED;
|
||||
}
|
||||
*pba_num = (u32)(nvm_data << 16);
|
||||
|
||||
ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
|
||||
if (ret_val) {
|
||||
DEBUGOUT("NVM Read Error\n");
|
||||
return ret_val;
|
||||
}
|
||||
*pba_num |= nvm_data;
|
||||
|
||||
return E1000_SUCCESS;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* e1000_read_pba_raw
|
||||
@ -1232,4 +1267,115 @@ static void e1000_reload_nvm_generic(struct e1000_hw *hw)
|
||||
E1000_WRITE_FLUSH(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* e1000_get_fw_version - Get firmware version information
|
||||
* @hw: pointer to the HW structure
|
||||
* @fw_vers: pointer to output version structure
|
||||
*
|
||||
* unsupported/not present features return 0 in version structure
|
||||
**/
|
||||
void e1000_get_fw_version(struct e1000_hw *hw, struct e1000_fw_version *fw_vers)
|
||||
{
|
||||
u16 eeprom_verh, eeprom_verl, etrack_test, fw_version;
|
||||
u8 q, hval, rem, result;
|
||||
u16 comb_verh, comb_verl, comb_offset;
|
||||
|
||||
memset(fw_vers, 0, sizeof(struct e1000_fw_version));
|
||||
|
||||
/* basic eeprom version numbers, bits used vary by part and by tool
|
||||
* used to create the nvm images */
|
||||
/* Check which data format we have */
|
||||
switch (hw->mac.type) {
|
||||
case e1000_i211:
|
||||
e1000_read_invm_version(hw, fw_vers);
|
||||
return;
|
||||
case e1000_82575:
|
||||
case e1000_82576:
|
||||
case e1000_82580:
|
||||
hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
|
||||
/* Use this format, unless EETRACK ID exists,
|
||||
* then use alternate format
|
||||
*/
|
||||
if ((etrack_test & NVM_MAJOR_MASK) != NVM_ETRACK_VALID) {
|
||||
hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
|
||||
fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
|
||||
>> NVM_MAJOR_SHIFT;
|
||||
fw_vers->eep_minor = (fw_version & NVM_MINOR_MASK)
|
||||
>> NVM_MINOR_SHIFT;
|
||||
fw_vers->eep_build = (fw_version & NVM_IMAGE_ID_MASK);
|
||||
goto etrack_id;
|
||||
}
|
||||
break;
|
||||
case e1000_i210:
|
||||
if (!(e1000_get_flash_presence_i210(hw))) {
|
||||
e1000_read_invm_version(hw, fw_vers);
|
||||
return;
|
||||
}
|
||||
/* fall through */
|
||||
case e1000_i350:
|
||||
hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
|
||||
/* find combo image version */
|
||||
hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);
|
||||
if ((comb_offset != 0x0) &&
|
||||
(comb_offset != NVM_VER_INVALID)) {
|
||||
|
||||
hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset
|
||||
+ 1), 1, &comb_verh);
|
||||
hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset),
|
||||
1, &comb_verl);
|
||||
|
||||
/* get Option Rom version if it exists and is valid */
|
||||
if ((comb_verh && comb_verl) &&
|
||||
((comb_verh != NVM_VER_INVALID) &&
|
||||
(comb_verl != NVM_VER_INVALID))) {
|
||||
|
||||
fw_vers->or_valid = TRUE;
|
||||
fw_vers->or_major =
|
||||
comb_verl >> NVM_COMB_VER_SHFT;
|
||||
fw_vers->or_build =
|
||||
(comb_verl << NVM_COMB_VER_SHFT)
|
||||
| (comb_verh >> NVM_COMB_VER_SHFT);
|
||||
fw_vers->or_patch =
|
||||
comb_verh & NVM_COMB_VER_MASK;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);
|
||||
return;
|
||||
}
|
||||
hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);
|
||||
fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)
|
||||
>> NVM_MAJOR_SHIFT;
|
||||
|
||||
/* check for old style version format in newer images*/
|
||||
if ((fw_version & NVM_NEW_DEC_MASK) == 0x0) {
|
||||
eeprom_verl = (fw_version & NVM_COMB_VER_MASK);
|
||||
} else {
|
||||
eeprom_verl = (fw_version & NVM_MINOR_MASK)
|
||||
>> NVM_MINOR_SHIFT;
|
||||
}
|
||||
/* Convert minor value to hex before assigning to output struct
|
||||
* Val to be converted will not be higher than 99, per tool output
|
||||
*/
|
||||
q = eeprom_verl / NVM_HEX_CONV;
|
||||
hval = q * NVM_HEX_TENS;
|
||||
rem = eeprom_verl % NVM_HEX_CONV;
|
||||
result = hval + rem;
|
||||
fw_vers->eep_minor = result;
|
||||
|
||||
etrack_id:
|
||||
if ((etrack_test & NVM_MAJOR_MASK) == NVM_ETRACK_VALID) {
|
||||
hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);
|
||||
hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);
|
||||
fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)
|
||||
| eeprom_verl;
|
||||
} else if ((etrack_test & NVM_ETRACK_VALID) == 0) {
|
||||
hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);
|
||||
hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);
|
||||
fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |
|
||||
eeprom_verl;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -35,12 +35,26 @@
|
||||
#ifndef _E1000_NVM_H_
|
||||
#define _E1000_NVM_H_
|
||||
|
||||
#if !defined(NO_READ_PBA_RAW) || !defined(NO_WRITE_PBA_RAW)
|
||||
struct e1000_pba {
|
||||
u16 word[2];
|
||||
u16 *pba_block;
|
||||
};
|
||||
#endif
|
||||
|
||||
struct e1000_fw_version {
|
||||
u32 etrack_id;
|
||||
u16 eep_major;
|
||||
u16 eep_minor;
|
||||
u16 eep_build;
|
||||
|
||||
u8 invm_major;
|
||||
u8 invm_minor;
|
||||
u8 invm_img_type;
|
||||
|
||||
bool or_valid;
|
||||
u16 or_major;
|
||||
u16 or_build;
|
||||
u16 or_patch;
|
||||
};
|
||||
|
||||
|
||||
void e1000_init_nvm_ops_generic(struct e1000_hw *hw);
|
||||
@ -52,6 +66,7 @@ s32 e1000_acquire_nvm_generic(struct e1000_hw *hw);
|
||||
|
||||
s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
|
||||
s32 e1000_read_mac_addr_generic(struct e1000_hw *hw);
|
||||
s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
|
||||
s32 e1000_read_pba_string_generic(struct e1000_hw *hw, u8 *pba_num,
|
||||
u32 pba_num_size);
|
||||
s32 e1000_read_pba_length_generic(struct e1000_hw *hw, u32 *pba_num_size);
|
||||
@ -76,6 +91,8 @@ s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
|
||||
s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw);
|
||||
void e1000_stop_nvm(struct e1000_hw *hw);
|
||||
void e1000_release_nvm_generic(struct e1000_hw *hw);
|
||||
void e1000_get_fw_version(struct e1000_hw *hw,
|
||||
struct e1000_fw_version *fw_vers);
|
||||
|
||||
#define E1000_STM_OPCODE 0xDB00
|
||||
|
||||
|
||||
@ -74,10 +74,6 @@
|
||||
#define STATIC static
|
||||
#define FALSE 0
|
||||
#define TRUE 1
|
||||
#ifndef __bool_true_false_are_defined
|
||||
#define false FALSE
|
||||
#define true TRUE
|
||||
#endif
|
||||
#define CMD_MEM_WRT_INVALIDATE 0x0010 /* BIT_4 */
|
||||
#define PCI_COMMAND_REGISTER PCIR_COMMAND
|
||||
|
||||
@ -99,9 +95,6 @@ typedef int64_t s64;
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
#ifndef __bool_true_false_are_defined
|
||||
typedef boolean_t bool;
|
||||
#endif
|
||||
|
||||
#define __le16 u16
|
||||
#define __le32 u32
|
||||
|
||||
@ -1827,9 +1827,9 @@ s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
|
||||
phy_data);
|
||||
if (ret_val)
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
|
||||
DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
|
||||
}
|
||||
|
||||
ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
|
||||
if (ret_val)
|
||||
|
||||
@ -65,6 +65,9 @@
|
||||
#define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */
|
||||
#define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */
|
||||
#define E1000_FEXTNVM7 0x000E4 /* Future Extended NVM 7 - RW */
|
||||
#define E1000_FEXTNVM9 0x5BB4 /* Future Extended NVM 9 - RW */
|
||||
#define E1000_FEXTNVM11 0x5BBC /* Future Extended NVM 11 - RW */
|
||||
#define E1000_PCIEANACFG 0x00F18 /* PCIE Analog Config */
|
||||
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
|
||||
#define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
|
||||
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
|
||||
@ -107,6 +110,8 @@
|
||||
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
||||
#define E1000_PBS 0x01008 /* Packet Buffer Size */
|
||||
#define E1000_PBECCSTS 0x0100C /* Packet Buffer ECC Status - RW */
|
||||
#define E1000_IOSFPC 0x00F28 /* TX corrupted data */
|
||||
#define E1000_IOSFPC 0x00F28 /* TX corrupted data */
|
||||
#define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */
|
||||
#define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */
|
||||
#define E1000_EEARBC_I210 0x12024 /* EEPROM Auto Read Bus Control */
|
||||
@ -588,6 +593,10 @@
|
||||
#define E1000_TIMADJL 0x0B60C /* Time sync time adjustment offset Low - RW */
|
||||
#define E1000_TIMADJH 0x0B610 /* Time sync time adjustment offset High - RW */
|
||||
#define E1000_TSAUXC 0x0B640 /* Timesync Auxiliary Control register */
|
||||
#define E1000_SYSSTMPL 0x0B648 /* HH Timesync system stamp low register */
|
||||
#define E1000_SYSSTMPH 0x0B64C /* HH Timesync system stamp hi register */
|
||||
#define E1000_PLTSTMPL 0x0B640 /* HH Timesync platform stamp low register */
|
||||
#define E1000_PLTSTMPH 0x0B644 /* HH Timesync platform stamp hi register */
|
||||
#define E1000_SYSTIMR 0x0B6F8 /* System time register Residue */
|
||||
#define E1000_TSICR 0x0B66C /* Interrupt Cause Register */
|
||||
#define E1000_TSIM 0x0B674 /* Interrupt Mask Register */
|
||||
@ -680,7 +689,6 @@
|
||||
#define E1000_O2BGPTC 0x08FE4 /* OS2BMC packets received by BMC */
|
||||
#define E1000_O2BSPC 0x0415C /* OS2BMC packets transmitted by host */
|
||||
|
||||
#define E1000_DOBFFCTL 0x3F24 /* DMA OBFF Control Register */
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@ -541,9 +541,9 @@ igb_attach(device_t dev)
|
||||
"Disable Energy Efficient Ethernet");
|
||||
if (adapter->hw.phy.media_type == e1000_media_type_copper) {
|
||||
if (adapter->hw.mac.type == e1000_i354)
|
||||
e1000_set_eee_i354(&adapter->hw);
|
||||
e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
|
||||
else
|
||||
e1000_set_eee_i350(&adapter->hw);
|
||||
e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1330,9 +1330,9 @@ igb_init_locked(struct adapter *adapter)
|
||||
/* Set Energy Efficient Ethernet */
|
||||
if (adapter->hw.phy.media_type == e1000_media_type_copper) {
|
||||
if (adapter->hw.mac.type == e1000_i354)
|
||||
e1000_set_eee_i354(&adapter->hw);
|
||||
e1000_set_eee_i354(&adapter->hw, TRUE, TRUE);
|
||||
else
|
||||
e1000_set_eee_i350(&adapter->hw);
|
||||
e1000_set_eee_i350(&adapter->hw, TRUE, TRUE);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user