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- Correct some programming details for the SAF1761 driver.
- Add some more register details. Sponsored by: DARPA, AFRL
This commit is contained in:
Hans Petter Selasky
parent
72fe532cd6
commit
a673f4c22b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=266214
@ -163,8 +163,6 @@ saf1761_dci_pull_up(struct saf1761_dci_softc *sc)
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DPRINTF("\n");
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sc->sc_flags.d_pulled_up = 1;
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SAF1761_WRITE_2(sc, SOTG_CTRL_SET, SOTG_CTRL_DP_PULL_UP);
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}
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}
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@ -177,8 +175,6 @@ saf1761_dci_pull_down(struct saf1761_dci_softc *sc)
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DPRINTF("\n");
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sc->sc_flags.d_pulled_up = 0;
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SAF1761_WRITE_2(sc, SOTG_CTRL_CLR, SOTG_CTRL_DP_PULL_UP);
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}
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}
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@ -212,13 +208,15 @@ saf1761_dci_set_address(struct saf1761_dci_softc *sc, uint8_t addr)
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static void
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saf1761_read_fifo(struct saf1761_dci_softc *sc, void *buf, uint32_t len)
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{
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bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, SOTG_DATA_PORT, buf, len);
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bus_space_read_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl,
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SOTG_DATA_PORT, buf, len);
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}
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static void
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saf1761_write_fifo(struct saf1761_dci_softc *sc, void *buf, uint32_t len)
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{
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bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl, SOTG_DATA_PORT, buf, len);
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bus_space_write_multi_1((sc)->sc_io_tag, (sc)->sc_io_hdl,
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SOTG_DATA_PORT, buf, len);
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}
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static uint8_t
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@ -270,6 +268,7 @@ saf1761_dci_setup_rx(struct saf1761_dci_softc *sc, struct saf1761_dci_td *td)
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if ((req.bmRequestType == UT_WRITE_DEVICE) &&
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(req.bRequest == UR_SET_ADDRESS)) {
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sc->sc_dv_addr = req.wValue[0] & 0x7F;
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DPRINTF("Set address %d\n", sc->sc_dv_addr);
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} else {
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sc->sc_dv_addr = 0xFF;
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}
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@ -563,10 +562,16 @@ saf1761_dci_wait_suspend(struct saf1761_dci_softc *sc, uint8_t on)
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static void
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saf1761_dci_update_vbus(struct saf1761_dci_softc *sc)
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{
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if (SAF1761_READ_4(sc, SOTG_MODE) & SOTG_MODE_VBUSSTAT) {
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DPRINTFN(4, "VBUS ON\n");
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uint16_t status;
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/* VBUS present */
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/* read fresh status */
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status = SAF1761_READ_2(sc, SOTG_STATUS);
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DPRINTFN(4, "STATUS=0x%04x\n", status);
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if ((status & SOTG_STATUS_VBUS_VLD) &&
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(status & SOTG_STATUS_ID)) {
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/* VBUS present and device mode */
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if (!sc->sc_flags.status_vbus) {
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sc->sc_flags.status_vbus = 1;
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@ -574,9 +579,7 @@ saf1761_dci_update_vbus(struct saf1761_dci_softc *sc)
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saf1761_dci_root_intr(sc);
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}
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} else {
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DPRINTFN(4, "VBUS OFF\n");
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/* VBUS not-present */
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/* VBUS not-present or host mode */
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if (sc->sc_flags.status_vbus) {
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sc->sc_flags.status_vbus = 0;
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sc->sc_flags.status_bus_reset = 0;
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@ -602,11 +605,23 @@ saf1761_dci_interrupt(struct saf1761_dci_softc *sc)
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/* acknowledge all interrupts */
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SAF1761_WRITE_4(sc, SOTG_DCINTERRUPT, status);
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DPRINTF("DCINTERRUPT=0x%08x SOF=0x%04x\n", status,
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SAF1761_READ_2(sc, SOTG_FRAME_NUM));
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/* update VBUS and ID bits, if any */
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if (status & SOTG_DCINTERRUPT_IEVBUS) {
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/* update VBUS bit */
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saf1761_dci_update_vbus(sc);
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}
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if (status & SOTG_DCINTERRUPT_IEBRST) {
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/* unlock device */
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SAF1761_WRITE_2(sc, SOTG_UNLOCK_DEVICE,
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SOTG_UNLOCK_DEVICE_CODE);
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/* Enable device address */
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SAF1761_WRITE_1(sc, SOTG_ADDRESS,
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SOTG_ADDRESS_ENABLE);
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sc->sc_flags.status_bus_reset = 1;
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sc->sc_flags.status_suspend = 0;
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sc->sc_flags.change_suspend = 0;
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@ -623,6 +638,10 @@ saf1761_dci_interrupt(struct saf1761_dci_softc *sc)
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* at least 3 milliseconds of inactivity on the USB BUS:
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*/
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if (status & SOTG_DCINTERRUPT_IERESM) {
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/* unlock device */
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SAF1761_WRITE_2(sc, SOTG_UNLOCK_DEVICE,
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SOTG_UNLOCK_DEVICE_CODE);
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if (sc->sc_flags.status_suspend) {
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sc->sc_flags.status_suspend = 0;
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sc->sc_flags.change_suspend = 1;
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@ -833,7 +852,7 @@ saf1761_dci_intr_set(struct usb_xfer *xfer, uint8_t set)
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uint8_t ep_no = (xfer->endpointno & UE_ADDR);
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uint32_t mask;
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DPRINTFN(15, "endpoint 0x%02x\n", xfer->endpointno);
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DPRINTFN(15, "endpoint=%d set=%d\n", xfer->endpointno, set);
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if (ep_no == 0) {
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mask = SOTG_DCINTERRUPT_IEPRX(0) |
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@ -1121,7 +1140,7 @@ saf1761_dci_init(struct saf1761_dci_softc *sc)
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const struct usb_hw_ep_profile *pf;
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uint8_t x;
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DPRINTF("start\n");
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DPRINTF("\n");
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/* set up the bus structure */
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sc->sc_bus.usbrev = USB_REV_2_0;
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@ -1129,6 +1148,19 @@ saf1761_dci_init(struct saf1761_dci_softc *sc)
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USB_BUS_LOCK(&sc->sc_bus);
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/* Enable interrupts */
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sc->sc_hw_mode |= SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN |
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SOTG_HW_MODE_CTRL_COMN_INT;
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/*
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* Set correct hardware mode, must be written twice if bus
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* width is changed:
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*/
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SAF1761_WRITE_2(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
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SAF1761_WRITE_4(sc, SOTG_HW_MODE_CTRL, sc->sc_hw_mode);
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DPRINTF("DCID=0x%08x\n", SAF1761_READ_4(sc, SOTG_DCCHIP_ID));
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/* reset device */
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SAF1761_WRITE_2(sc, SOTG_MODE, SOTG_MODE_SFRESET);
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SAF1761_WRITE_2(sc, SOTG_MODE, 0);
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@ -1142,7 +1174,7 @@ saf1761_dci_init(struct saf1761_dci_softc *sc)
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/* wait 10ms for pulldown to stabilise */
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usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 100);
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for (x = 0;; x++) {
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for (x = 1;; x++) {
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saf1761_dci_get_hw_ep_profile(NULL, &pf, x);
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if (pf == NULL)
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@ -1156,10 +1188,6 @@ saf1761_dci_init(struct saf1761_dci_softc *sc)
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/* select the maximum packet size */
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SAF1761_WRITE_2(sc, SOTG_EP_MAXPACKET, pf->max_in_frame_size);
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if (x == 0) {
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/* enable control endpoint */
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SAF1761_WRITE_2(sc, SOTG_EP_TYPE, SOTG_EP_TYPE_ENABLE);
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}
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/* select the correct endpoint */
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SAF1761_WRITE_1(sc, SOTG_EP_INDEX,
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(x << SOTG_EP_INDEX_ENDP_INDEX_SHIFT) |
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@ -1167,20 +1195,35 @@ saf1761_dci_init(struct saf1761_dci_softc *sc)
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/* select the maximum packet size */
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SAF1761_WRITE_2(sc, SOTG_EP_MAXPACKET, pf->max_out_frame_size);
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if (x == 0) {
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/* enable control endpoint */
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SAF1761_WRITE_2(sc, SOTG_EP_TYPE, SOTG_EP_TYPE_ENABLE);
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}
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}
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/* enable interrupts */
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SAF1761_WRITE_2(sc, SOTG_MODE, SOTG_MODE_GLINTENA);
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SAF1761_WRITE_2(sc, SOTG_MODE, SOTG_MODE_GLINTENA |
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SOTG_MODE_CLKAON | SOTG_MODE_WKUPCS);
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/* set default values */
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SAF1761_WRITE_1(sc, SOTG_INTERRUPT_CFG,
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SOTG_INTERRUPT_CFG_CDBGMOD |
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SOTG_INTERRUPT_CFG_DDBGMODIN |
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SOTG_INTERRUPT_CFG_DDBGMODOUT);
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/* enable VBUS and ID interrupt */
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SAF1761_WRITE_2(sc, SOTG_IRQ_ENABLE_CLR, 0xFFFF);
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SAF1761_WRITE_2(sc, SOTG_IRQ_ENABLE_SET,
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SOTG_IRQ_ID | SOTG_IRQ_VBUS_VLD);
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/* enable interrupts */
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sc->sc_intr_enable = SOTG_DCINTERRUPT_EN, SOTG_DCINTERRUPT_IEVBUS |
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sc->sc_intr_enable = SOTG_DCINTERRUPT_IEVBUS |
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SOTG_DCINTERRUPT_IEBRST | SOTG_DCINTERRUPT_IESUSP;
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SAF1761_WRITE_2(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
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SAF1761_WRITE_4(sc, SOTG_DCINTERRUPT_EN, sc->sc_intr_enable);
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/* connect ATX port 1 to device controller */
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SAF1761_WRITE_2(sc, SOTG_CTRL_CLR, 0xFFFF);
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SAF1761_WRITE_2(sc, SOTG_CTRL_SET, SOTG_CTRL_SW_SEL_HC_DC |
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SOTG_CTRL_BDIS_ACON_EN);
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/* disable device address */
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SAF1761_WRITE_1(sc, SOTG_ADDRESS, 0);
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/* poll initial VBUS status */
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saf1761_dci_update_vbus(sc);
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@ -107,7 +107,6 @@ struct saf1761_dci_flags {
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uint8_t port_powered:1;
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uint8_t port_enabled:1;
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uint8_t d_pulled_up:1;
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uint8_t mcsr_feat:1;
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};
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struct saf1761_dci_softc {
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@ -123,6 +122,7 @@ struct saf1761_dci_softc {
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bus_space_handle_t sc_io_hdl;
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uint32_t sc_intr_enable; /* enabled interrupts */
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uint32_t sc_hw_mode; /* hardware mode */
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uint8_t sc_rt_addr; /* root HUB address */
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uint8_t sc_dv_addr; /* device address */
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@ -102,6 +102,17 @@
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#define SOTG_DEBUG_SET (1 << 0)
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#define SOTG_DCINTERRUPT_EN 0x214
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#define SOTG_HW_MODE_CTRL 0x300
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#define SOTG_HW_MODE_CTRL_ALL_ATX_RESET (1 << 31)
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#define SOTG_HW_MODE_CTRL_ANA_DIGI_OC (1 << 15)
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#define SOTG_HW_MODE_CTRL_DEV_DMA (1 << 11)
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#define SOTG_HW_MODE_CTRL_COMN_INT (1 << 10)
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#define SOTG_HW_MODE_CTRL_COMN_DMA (1 << 9)
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#define SOTG_HW_MODE_CTRL_DATA_BUS_WIDTH (1 << 8)
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#define SOTG_HW_MODE_CTRL_DACK_POL (1 << 6)
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#define SOTG_HW_MODE_CTRL_DREQ_POL (1 << 5)
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#define SOTG_HW_MODE_CTRL_INTR_POL (1 << 2)
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#define SOTG_HW_MODE_CTRL_INTR_LEVEL (1 << 1)
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#define SOTG_HW_MODE_CTRL_GLOBAL_INTR_EN (1 << 0)
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#define SOTG_OTG_CTRL 0x374
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#define SOTG_EP_INDEX 0x22c
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#define SOTG_EP_INDEX_EP0SETUP (1 << 5)
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@ -155,5 +166,29 @@
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#define SOTG_UNLOCK_DEVICE_CODE 0xAA37
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#define SOTG_IRQ_PULSE_WIDTH 0x280
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#define SOTG_TEST_MODE 0x284
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#define SOTG_TEST_MODE_FORCEHS (1 << 7)
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#define SOTG_TEST_MODE_FORCEFS (1 << 4)
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#define SOTG_TEST_MODE_PRBS (1 << 3)
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#define SOTG_TEST_MODE_KSTATE (1 << 2)
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#define SOTG_TEST_MODE_JSTATE (1 << 1)
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#define SOTG_TEST_MODE_SE0_NAK (1 << 0)
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/* Host controller specific registers */
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#define SOTG_CONFIGFLAG 0x0060
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#define SOTG_CONFIGFLAG_ENABLE (1 << 0)
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#define SOTG_PORTSC1 0x0064
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#define SOTG_PORTSC1_PO (1 << 13)
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#define SOTG_PORTSC1_PP (1 << 12)
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#define SOTG_PORTSC1_PR (1 << 8)
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#define SOTG_PORTSC1_SUSP (1 << 7)
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#define SOTG_PORTSC1_FPR (1 << 6)
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#define SOTG_PORTSC1_PED (1 << 2)
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#define SOTG_PORTSC1_ECSC (1 << 1)
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#define SOTG_PORTSC1_ECCS (1 << 0)
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#define SOTG_ASYNC_PDT(x) (0x400 + (60 * 1024) + ((x) * 32))
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#define SOTG_INTR_PDT(x) (0x400 + (61 * 1024) + ((x) * 32))
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#define SOTG_ISOC_PDT(x) (0x400 + (62 * 1024) + ((x) * 32))
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#define SOTG_HC_MEMORY_ADDR(x) (((x) - 0x400) >> 3)
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#endif /* _SAF1761_DCI_REG_H_ */
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