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Code Issues Releases Activity

trim trailing spaces that have accumulated over the years (these files

Browse Source 
served as the basis for too many other platforms).
This commit is contained in:
Warner Losh 2012-06-13 04:38:09 +00:00
parent cca63ae56b
commit a698b62cf5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=236987
40 changed files with 203 additions and 204 deletions
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22
sys/arm/xscale/i80321/ep80219_machdep.c
View File

@ -40,7 +40,7 @@
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
* This file needs a lot of work.
*
* Created : 17/09/94
*/
@ -142,7 +142,7 @@ struct pv_addr minidataclean;
/* Static device mappings. */
static const struct pmap_devmap ep80219_devmap[] = {
/*
/*
* Map the on-board devices VA == PA so that we can access them
* with the MMU on or off.
*/
@ -150,7 +150,7 @@ static const struct pmap_devmap ep80219_devmap[] = {
IQ80321_OBIO_BASE,
IQ80321_OBIO_BASE,
IQ80321_OBIO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
@ -159,7 +159,7 @@ static const struct pmap_devmap ep80219_devmap[] = {
VERDE_OUT_XLATE_IO_WIN_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
},
{
IQ80321_80321_VBASE,
VERDE_PMMR_BASE,
@ -192,8 +192,8 @@ initarm(struct arm_boot_params *abp)
vm_offset_t lastaddr;
uint32_t memsize, memstart;
lastaddr = parse_boot_param(abp);
set_cpufuncs();
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
@ -222,7 +222,7 @@ initarm(struct arm_boot_params *abp)
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0x20000000;
}
}
@ -291,13 +291,13 @@ initarm(struct arm_boot_params *abp)
(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
@ -306,7 +306,7 @@ initarm(struct arm_boot_params *abp)
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif
@ -338,7 +338,7 @@ initarm(struct arm_boot_params *abp)
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
@ -386,7 +386,7 @@ initarm(struct arm_boot_params *abp)
dump_avail[1] = 0xa0000000 + memsize;
dump_avail[2] = 0;
dump_avail[3] = 0;
pmap_bootstrap(pmap_curmaxkvaddr,
pmap_bootstrap(pmap_curmaxkvaddr,
0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);

6
sys/arm/xscale/i80321/i80321.c
View File

@ -225,9 +225,9 @@ i80321_attach(struct i80321_softc *sc)
static __inline uint32_t
i80321_iintsrc_read(void)
{
uint32_t iintsrc;
{
uint32_t iintsrc;
__asm __volatile("mrc p6, 0, %0, c8, c0, 0"
: "=r" (iintsrc));

20
sys/arm/xscale/i80321/i80321_aau.c
View File

@ -111,14 +111,14 @@ i80321_aau_attach(device_t dev)
mtx_init(&softc->mtx, "AAU mtx", NULL, MTX_SPIN);
softc->sc_st = sc->sc_st;
if (bus_space_subregion(softc->sc_st, sc->sc_sh, VERDE_AAU_BASE,
if (bus_space_subregion(softc->sc_st, sc->sc_sh, VERDE_AAU_BASE,
VERDE_AAU_SIZE, &softc->sc_aau_sh) != 0)
panic("%s: unable to subregion AAU registers",
device_get_name(dev));
if (bus_dma_tag_create(NULL, sizeof(i80321_aaudesc_t), 0,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
AAU_RING_SIZE * sizeof(i80321_aaudesc_t),
1, sizeof(i80321_aaudesc_t), BUS_DMA_ALLOCNOW, busdma_lock_mutex,
1, sizeof(i80321_aaudesc_t), BUS_DMA_ALLOCNOW, busdma_lock_mutex,
&Giant, &softc->dmatag))
panic("Couldn't create a dma tag");
if (bus_dmamem_alloc(softc->dmatag, (void **)&aaudescs,
@ -186,7 +186,7 @@ aau_bzero(void *dst, int len, int flags)
desc->next_desc = 0;
desc->count = len;
desc->descr_ctrl = 2 << 1 | 1 << 31; /* Fill, enable dest write */
bus_dmamap_sync(sc->dmatag, sc->aauring[0].map,
bus_dmamap_sync(sc->dmatag, sc->aauring[0].map,
BUS_DMASYNC_PREWRITE);
} else {
test_virt_addr(dst, len);
@ -218,8 +218,8 @@ aau_bzero(void *dst, int len, int flags)
if (tmplen <= 0 && descnb > 0) {
sc->aauring[descnb - 1].desc->next_desc
= 0;
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb - 1].map,
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb - 1].map,
BUS_DMASYNC_PREWRITE);
}
continue;
@ -241,15 +241,15 @@ aau_bzero(void *dst, int len, int flags)
if (tmplen > 0) {
desc->next_desc = sc->aauring[descnb + 1].
phys_addr;
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb].map,
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb].map,
BUS_DMASYNC_PREWRITE);
desc = sc->aauring[descnb + 1].desc;
descnb++;
} else {
desc->next_desc = 0;
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb].map,
bus_dmamap_sync(sc->dmatag,
sc->aauring[descnb].map,
BUS_DMASYNC_PREWRITE);
}

22
sys/arm/xscale/i80321/i80321_dma.c
View File

@ -115,13 +115,13 @@ i80321_dma_attach(device_t dev)
mtx_init(&softc->mtx, "DMA engine mtx", NULL, MTX_SPIN);
softc->sc_st = sc->sc_st;
if (bus_space_subregion(softc->sc_st, sc->sc_sh, unit == 0 ?
VERDE_DMA_BASE0 : VERDE_DMA_BASE1, VERDE_DMA_SIZE,
VERDE_DMA_BASE0 : VERDE_DMA_BASE1, VERDE_DMA_SIZE,
&softc->sc_dma_sh) != 0)
panic("%s: unable to subregion DMA registers",
device_get_name(dev));
if (bus_dma_tag_create(NULL, sizeof(i80321_dmadesc_t),
0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
DMA_RING_SIZE * sizeof(i80321_dmadesc_t), 1,
0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
DMA_RING_SIZE * sizeof(i80321_dmadesc_t), 1,
sizeof(i80321_dmadesc_t), BUS_DMA_ALLOCNOW, busdma_lock_mutex,
&Giant, &softc->dmatag))
panic("Couldn't create a dma tag");
@ -131,7 +131,7 @@ i80321_dma_attach(device_t dev)
panic("Couldn't alloc dma memory");
for (int i = 0; i < DMA_RING_SIZE; i++) {
if (i > 0)
if (bus_dmamap_create(softc->dmatag, 0,
if (bus_dmamap_create(softc->dmatag, 0,
&softc->dmaring[i].map))
panic("Couldn't alloc dmamap");
softc->dmaring[i].desc = &dmadescs[i];
@ -213,11 +213,11 @@ dma_memcpy(void *dst, void *src, int len, int flags)
desc->local_addr = (vm_paddr_t)dst;
desc->count = len;
desc->descr_ctrl = 1 << 6; /* Local memory to local memory. */
bus_dmamap_sync(sc->dmatag,
sc->dmaring[0].map,
bus_dmamap_sync(sc->dmatag,
sc->dmaring[0].map,
BUS_DMASYNC_PREWRITE);
} else {
if (!virt_addr_is_valid(dst, len, 1, !(flags & DST_IS_USER)) ||
if (!virt_addr_is_valid(dst, len, 1, !(flags & DST_IS_USER)) ||
!virt_addr_is_valid(src, len, 0, !(flags & SRC_IS_USER))) {
mtx_lock_spin(&sc->mtx);
sc->flags &= ~BUSY;
@ -275,8 +275,8 @@ dma_memcpy(void *dst, void *src, int len, int flags)
if (tmplen <= 0 && descnb > 0) {
sc->dmaring[descnb - 1].desc->next_desc
= 0;
bus_dmamap_sync(sc->dmatag,
sc->dmaring[descnb - 1].map,
bus_dmamap_sync(sc->dmatag,
sc->dmaring[descnb - 1].map,
BUS_DMASYNC_PREWRITE);
}
continue;
@ -301,8 +301,8 @@ dma_memcpy(void *dst, void *src, int len, int flags)
if (tmplen > 0) {
desc->next_desc = sc->dmaring[descnb + 1].
phys_addr;
bus_dmamap_sync(sc->dmatag,
sc->dmaring[descnb].map,
bus_dmamap_sync(sc->dmatag,
sc->dmaring[descnb].map,
BUS_DMASYNC_PREWRITE);
desc = sc->dmaring[descnb + 1].desc;
descnb++;

2
sys/arm/xscale/i80321/i80321_intr.h
View File

@ -33,7 +33,7 @@
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*
* $FreeBSD$
*
*/

18
sys/arm/xscale/i80321/i80321_pci.c
View File

@ -79,7 +79,7 @@ static int
i80321_pci_attach(device_t dev)
{
uint32_t busno;
uint32_t busno;
struct i80321_pci_softc *sc = device_get_softc(dev);
sc->sc_st = i80321_softc->sc_st;
@ -100,16 +100,16 @@ i80321_pci_attach(device_t dev)
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "I80321 PCI I/O Ports";
if (rman_init(&sc->sc_io_rman) != 0 ||
rman_manage_region(&sc->sc_io_rman,
sc->sc_io,
sc->sc_io +
rman_manage_region(&sc->sc_io_rman,
sc->sc_io,
sc->sc_io +
VERDE_OUT_XLATE_IO_WIN_SIZE) != 0) {
panic("i80321_pci_probe: failed to set up I/O rman");
}
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "I80321 PCI Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman,
rman_manage_region(&sc->sc_mem_rman,
0, VERDE_OUT_XLATE_MEM_WIN_SIZE) != 0) {
panic("i80321_pci_probe: failed to set up memory rman");
}
@ -325,7 +325,7 @@ i80321_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_release_resource(rv);
return (NULL);
}
}
}
}
return (rv);
}
@ -340,7 +340,7 @@ i80321_pci_activate_resource(device_t bus, device_t child, int type, int rid,
if (type == SYS_RES_MEMORY) {
error = bus_space_map(rman_get_bustag(r),
rman_get_bushandle(r), rman_get_size(r), 0, &p);
if (error)
if (error)
return (error);
rman_set_bushandle(r, p);
@ -350,8 +350,8 @@ i80321_pci_activate_resource(device_t bus, device_t child, int type, int rid,
static int
i80321_pci_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags,
filt, intr, arg, cookiep));

6
sys/arm/xscale/i80321/i80321_space.c
View File

@ -279,7 +279,7 @@ i80321_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
panic("i80321_io_bs_alloc(): not implemented");
}
void
void
i80321_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
@ -299,7 +299,7 @@ i80321_mem_bs_map(void *t, bus_addr_t bpa, bus_size_t size, int flags,
endpa = round_page(bpa + size);
*bshp = (vm_offset_t)pmap_mapdev(pa, endpa - pa);
return (0);
}
@ -324,7 +324,7 @@ i80321_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
panic("i80321_mem_bs_alloc(): not implemented");
}
void
void
i80321_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{

10
sys/arm/xscale/i80321/i80321_timer.c
View File

@ -62,7 +62,7 @@ __FBSDID("$FreeBSD$");
#include <arm/xscale/i80321/i80321var.h>
#ifdef CPU_XSCALE_81342
#define ICU_INT_TIMER0 (8) /* XXX: Can't include i81342reg.h because
#define ICU_INT_TIMER0 (8) /* XXX: Can't include i81342reg.h because
definitions overrides the ones from i80321reg.h
*/
#endif
@ -79,7 +79,7 @@ static unsigned i80321_timer_get_timecount(struct timecounter *tc);
static uint32_t counts_per_hz;
#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
#if defined(XSCALE_DISABLE_CCNT) || defined(CPU_XSCALE_81342)
static uint32_t offset;
static uint32_t last = -1;
#endif
@ -383,17 +383,17 @@ cpu_initclocks(void)
oldirqstate = disable_interrupts(I32_bit);
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
#ifdef CPU_XSCALE_81342
ICU_INT_TIMER0, ICU_INT_TIMER0,
#else
ICU_INT_TMR0, ICU_INT_TMR0,
ICU_INT_TMR0, ICU_INT_TMR0,
#endif
1, RF_ACTIVE);
if (!irq)
panic("Unable to setup the clock irq handler.\n");
else
bus_setup_intr(dev, irq, INTR_TYPE_CLK, clockhandler, NULL,
bus_setup_intr(dev, irq, INTR_TYPE_CLK, clockhandler, NULL,
NULL, &ihl);
tmr0_write(0); /* stop timer */
tisr_write(TISR_TMR0); /* clear interrupt */

6
sys/arm/xscale/i80321/i80321reg.h
View File

@ -38,8 +38,8 @@
*
*/
#ifndef _ARM_XSCALE_I80321REG_H_
#define _ARM_XSCALE_I80321REG_H_
#ifndef _ARM_XSCALE_I80321REG_H_
#define _ARM_XSCALE_I80321REG_H_
/*
* Register definitions for the Intel 80321 (``Verde'') I/O processor,
@ -102,7 +102,7 @@
#if defined(CPU_XSCALE_80321)
#define VERDE_AAU_BASE 0x0800
#define VERDE_AAU_SIZE 0x0100
#endif
#endif
#define VERDE_I2C_BASE 0x1680
#define VERDE_I2C_BASE0 (VERDE_I2C_BASE + 0x00)

4
sys/arm/xscale/i80321/iq31244_7seg.c
View File

@ -206,7 +206,7 @@ static const uint8_t digitmap[] = {
SEG_D|SEG_E,
};
static uint8_t
static uint8_t
iq80321_7seg_xlate(char c)
{
uint8_t rv;
@ -336,7 +336,7 @@ static const uint8_t snakemap[][2] = {
static SYSCTL_NODE(_hw, OID_AUTO, sevenseg, CTLFLAG_RD, 0, "7 seg");
static int freq = 20;
SYSCTL_INT(_hw_sevenseg, OID_AUTO, freq, CTLFLAG_RW, &freq, 0,
SYSCTL_INT(_hw_sevenseg, OID_AUTO, freq, CTLFLAG_RW, &freq, 0,
"7 Seg update frequency");
static void
iq31244_7seg_snake(void)

22
sys/arm/xscale/i80321/iq31244_machdep.c
View File

@ -40,7 +40,7 @@
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
* This file needs a lot of work.
*
* Created : 17/09/94
*/
@ -140,7 +140,7 @@ struct pv_addr minidataclean;
#define IQ80321_OBIO_SIZE 0x00100000UL
/* Static device mappings. */
static const struct pmap_devmap iq80321_devmap[] = {
/*
/*
* Map the on-board devices VA == PA so that we can access them
* with the MMU on or off.
*/
@ -148,7 +148,7 @@ static const struct pmap_devmap iq80321_devmap[] = {
IQ80321_OBIO_BASE,
IQ80321_OBIO_BASE,
IQ80321_OBIO_SIZE,
VM_PROT_READ|VM_PROT_WRITE,
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
@ -158,7 +158,7 @@ static const struct pmap_devmap iq80321_devmap[] = {
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
IQ80321_80321_VBASE,
VERDE_PMMR_BASE,
@ -193,8 +193,8 @@ initarm(struct arm_boot_params *abp)
vm_offset_t lastaddr;
uint32_t memsize, memstart;
lastaddr = parse_boot_param(abp);
set_cpufuncs();
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
@ -223,7 +223,7 @@ initarm(struct arm_boot_params *abp)
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0x20000000;
}
}
@ -290,13 +290,13 @@ initarm(struct arm_boot_params *abp)
(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
@ -305,7 +305,7 @@ initarm(struct arm_boot_params *abp)
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif
@ -337,7 +337,7 @@ initarm(struct arm_boot_params *abp)
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
@ -393,7 +393,7 @@ initarm(struct arm_boot_params *abp)
dump_avail[2] = 0;
dump_avail[3] = 0;
pmap_bootstrap(pmap_curmaxkvaddr,
pmap_bootstrap(pmap_curmaxkvaddr,
0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);

4
sys/arm/xscale/i80321/iq80321.c
View File

@ -324,7 +324,7 @@ arm_unmask_irq(uintptr_t nb)
void
cpu_reset()
{
{
(void) disable_interrupts(I32_bit|F32_bit);
*(__volatile uint32_t *)(IQ80321_80321_VBASE + VERDE_ATU_BASE +
ATU_PCSR) = PCSR_RIB | PCSR_RPB;
@ -351,7 +351,7 @@ iq80321_alloc_resource(device_t dev, device_t child, int type, int *rid,
static int
iq80321_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t *filt,
struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
int error;

2
sys/arm/xscale/i80321/obio.c
View File

@ -120,7 +120,7 @@ obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
if (rv == NULL)
return (NULL);
if (type == SYS_RES_IRQ)
return (rv);

16
sys/arm/xscale/i8134x/crb_machdep.c
View File

@ -40,7 +40,7 @@
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
* This file needs a lot of work.
*
* Created : 17/09/94
*/
@ -162,7 +162,7 @@ static const struct pmap_devmap iq81342_devmap[] = {
VM_PROT_READ|VM_PROT_WRITE,
PTE_NOCACHE,
},
{
{
0,
0,
0,
@ -189,8 +189,8 @@ initarm(struct arm_boot_params *abp)
vm_offset_t lastaddr;
uint32_t memsize, memstart;
lastaddr = parse_boot_param(abp);
set_cpufuncs();
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
@ -219,7 +219,7 @@ initarm(struct arm_boot_params *abp)
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0xc0000000;
}
}
@ -278,7 +278,7 @@ initarm(struct arm_boot_params *abp)
(((uint32_t)(lastaddr) - KERNBASE - 0x200000) + L1_S_SIZE) & ~(L1_S_SIZE - 1),
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
freemem_after = ((int)lastaddr + PAGE_SIZE) & ~(PAGE_SIZE - 1);
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
afterkern = round_page(((vm_offset_t)lastaddr + L1_S_SIZE) & ~(L1_S_SIZE
- 1));
for (i = 0; i < KERNEL_PT_AFKERNEL_NUM; i++) {
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
@ -291,7 +291,7 @@ initarm(struct arm_boot_params *abp)
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif
@ -319,7 +319,7 @@ initarm(struct arm_boot_params *abp)
* of the stack memory.
*/
set_stackptr(PSR_IRQ32_MODE,
irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE,
@ -365,7 +365,7 @@ initarm(struct arm_boot_params *abp)
dump_avail[2] = 0;
dump_avail[3] = 0;
pmap_bootstrap(pmap_curmaxkvaddr,
pmap_bootstrap(pmap_curmaxkvaddr,
0xd0000000, &kernel_l1pt);
msgbufp = (void*)msgbufpv.pv_va;
msgbufinit(msgbufp, msgbufsize);

4
sys/arm/xscale/i8134x/i81342.c
View File

@ -425,8 +425,8 @@ i81342_alloc_resource(device_t dev, device_t child, int type, int *rid,
}
static int
i81342_setup_intr(device_t dev, device_t child, struct resource *ires,
int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
i81342_setup_intr(device_t dev, device_t child, struct resource *ires,
int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
void **cookiep)
{
int error;

2
sys/arm/xscale/i8134x/i81342_mcu.c
View File

@ -38,7 +38,7 @@ __FBSDID("$FreeBSD$");
#include <arm/xscale/i8134x/i81342var.h>
void
i81342_sdram_bounds(bus_space_tag_t bt, bus_space_handle_t bh,
i81342_sdram_bounds(bus_space_tag_t bt, bus_space_handle_t bh,
vm_paddr_t *start, vm_size_t *size)
{
uint32_t reg;

14
sys/arm/xscale/i8134x/i81342_pci.c
View File

@ -180,7 +180,7 @@ i81342_pci_attach(device_t dev)
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "I81342 PCI I/O Ports";
if (rman_init(&sc->sc_io_rman) != 0 ||
rman_manage_region(&sc->sc_io_rman,
rman_manage_region(&sc->sc_io_rman,
sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
IOP34X_PCIE_OIOBAR_VADDR,
(sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR :
@ -190,7 +190,7 @@ i81342_pci_attach(device_t dev)
sc->sc_mem_rman.rm_type = RMAN_ARRAY;
sc->sc_mem_rman.rm_descr = "I81342 PCI Memory";
if (rman_init(&sc->sc_mem_rman) != 0 ||
rman_manage_region(&sc->sc_mem_rman,
rman_manage_region(&sc->sc_mem_rman,
0, 0xffffffff) != 0) {
panic("i81342_pci_attach: failed to set up memory rman");
}
@ -198,12 +198,12 @@ i81342_pci_attach(device_t dev)
sc->sc_irq_rman.rm_descr = "i81342 PCI IRQs";
if (sc->sc_is_atux) {
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, ICU_INT_XINT0,
rman_manage_region(&sc->sc_irq_rman, ICU_INT_XINT0,
ICU_INT_XINT3) != 0)
panic("i83142_pci_attach: failed to set up IRQ rman");
} else {
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, ICU_INT_ATUE_MA,
rman_manage_region(&sc->sc_irq_rman, ICU_INT_ATUE_MA,
ICU_INT_ATUE_MD) != 0)
panic("i81342_pci_attach: failed to set up IRQ rman");
@ -242,7 +242,7 @@ i81342_pci_conf_setup(struct i81342_pci_softc *sc, int bus, int slot, int func,
*addr = (1 << (slot + 16)) | (slot << 11) |
(func << 8) | reg;
else
*addr = (bus << 16) | (slot << 11) | (func << 11) |
*addr = (bus << 16) | (slot << 11) | (func << 11) |
reg | 1;
} else {
*addr = (bus << 24) | (slot << 19) | (func << 16) | reg;
@ -297,7 +297,7 @@ i81342_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
}
static void
i81342_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
i81342_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
u_int reg, u_int32_t data, int bytes)
{
struct i81342_pci_softc *sc = device_get_softc(dev);
@ -372,7 +372,7 @@ i81342_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_release_resource(rv);
return (NULL);
}
}
}
}
return (rv);

4
sys/arm/xscale/i8134x/i81342_space.c
View File

@ -260,7 +260,7 @@ i81342_io_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
panic("i81342_io_bs_alloc(): not implemented");
}
void
void
i81342_io_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
@ -337,7 +337,7 @@ i81342_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
panic("i81342_mem_bs_alloc(): not implemented");
}
void
void
i81342_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{

4
sys/arm/xscale/i8134x/i81342reg.h
View File

@ -29,7 +29,7 @@
#ifndef I83142_REG_H_
#define I83142_REG_H_
/* Physical Memory Map */
/*
/*
* 0x000000000 - 0x07FFFFFFF SDRAM
* 0x090100000 - 0x0901FFFFF ATUe Outbound IO Window
* 0x0F0000000 - 0x0F1FFFFFF Flash
@ -62,7 +62,7 @@
#define IOP34X_ADMA_IE (1 << 0) /* Interrupt enable */
#define IOP34X_ADMA_TR (1 << 1) /* Transfert Direction */
/*
/*
* Source Destination
* 00 Host I/O Interface Local Memory
* 01 Local Memory Host I/O Interface

4
sys/arm/xscale/i8134x/iq81342_7seg.c
View File

@ -207,7 +207,7 @@ static const uint8_t digitmap[] = {
~(SEG_D|SEG_E),
};
static uint8_t
static uint8_t
iq81342_7seg_xlate(char c)
{
uint8_t rv;
@ -337,7 +337,7 @@ static const uint8_t snakemap[][2] = {
static SYSCTL_NODE(_hw, OID_AUTO, sevenseg, CTLFLAG_RD, 0, "7 seg");
static int freq = 20;
SYSCTL_INT(_hw_sevenseg, OID_AUTO, freq, CTLFLAG_RW, &freq, 0,
SYSCTL_INT(_hw_sevenseg, OID_AUTO, freq, CTLFLAG_RW, &freq, 0,
"7 Seg update frequency");
static void
iq81342_7seg_snake(void)

2
sys/arm/xscale/i8134x/obio.c
View File

@ -127,7 +127,7 @@ obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
if (rv == NULL)
return (NULL);
if (type == SYS_RES_IRQ)
return (rv);

2
sys/arm/xscale/i8134x/uart_cpu_i81342.c
View File

@ -55,7 +55,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = &obio_bs_tag;
di->bas.regshft = 2;
di->bas.regshft = 2;
di->bas.rclk = 33334000;
di->baudrate = 115200;
di->databits = 8;

2
sys/arm/xscale/ixp425/avila_ata.c
View File

@ -304,7 +304,7 @@ ata_avila_release_resource(device_t dev, device_t child, int type, int rid,
}
static int
ata_avila_setup_intr(device_t dev, device_t child, struct resource *irq,
ata_avila_setup_intr(device_t dev, device_t child, struct resource *irq,
int flags, driver_filter_t *filt,
driver_intr_t *function, void *argument, void **cookiep)
{

2
sys/arm/xscale/ixp425/avila_gpio.c
View File

@ -102,7 +102,7 @@ static struct avila_gpio_pin avila_gpio_pins[] = {
/*
* Helpers
*/
static void avila_gpio_pin_configure(struct avila_gpio_softc *sc,
static void avila_gpio_pin_configure(struct avila_gpio_softc *sc,
struct gpio_pin *pin, uint32_t flags);
static int avila_gpio_pin_flags(struct avila_gpio_softc *sc, uint32_t pin);

10
sys/arm/xscale/ixp425/avila_machdep.c
View File

@ -40,7 +40,7 @@
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
* This file needs a lot of work.
*
* Created : 17/09/94
*/
@ -238,8 +238,8 @@ initarm(struct arm_boot_params *abp)
vm_offset_t lastaddr;
uint32_t memsize;
lastaddr = parse_boot_param(abp);
set_cpufuncs(); /* NB: sets cputype */
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
@ -283,7 +283,7 @@ initarm(struct arm_boot_params *abp)
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa +
(KERNVIRTADDR - KERNPHYSADDR);
}
@ -364,7 +364,7 @@ initarm(struct arm_boot_params *abp)
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
#ifdef ARM_USE_SMALL_ALLOC
@ -372,7 +372,7 @@ initarm(struct arm_boot_params *abp)
arm_add_smallalloc_pages((void *)(freemem_after),
(void*)(freemem_after + PAGE_SIZE),
afterkern - (freemem_after + PAGE_SIZE), 0);
}
#endif

2
sys/arm/xscale/ixp425/cambria_exp_space.c
View File

@ -249,7 +249,7 @@ cambria_exp_bus_init(struct ixp425_softc *sc)
cs3 = EXP_BUS_READ_4(sc, EXP_TIMING_CS3_OFFSET);
/* XXX force slowest possible timings and byte mode */
EXP_BUS_WRITE_4(sc, EXP_TIMING_CS3_OFFSET,
cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) |
cs3 | (EXP_T1|EXP_T2|EXP_T3|EXP_T4|EXP_T5) |
EXP_BYTE_EN | EXP_WR_EN | EXP_BYTE_RD16 | EXP_CS_EN);
/* XXX force GPIO 3+4 for GPS+RS485 uarts */

10
sys/arm/xscale/ixp425/if_npe.c
View File

@ -89,8 +89,8 @@ __FBSDID("$FreeBSD$");
#include "miibus_if.h"
/*
* XXX: For the main bus dma tag. Can go away if the new method to get the
/*
* XXX: For the main bus dma tag. Can go away if the new method to get the
* dma tag from the parent got MFC'd into RELENG_6.
*/
extern struct ixp425_softc *ixp425_softc;
@ -302,7 +302,7 @@ npe_probe(device_t dev)
int unit = device_get_unit(dev);
int npeid;
if (unit > 2 ||
if (unit > 2 ||
(ixp4xx_read_feature_bits() &
(unit == 0 ? EXP_FCTRL_ETH0 : EXP_FCTRL_ETH1)) == 0)
return EINVAL;
@ -496,7 +496,7 @@ npe_dma_setup(struct npe_softc *sc, struct npedma *dma,
}
/* DMA tag and map for the NPE buffers */
error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
error = bus_dma_tag_create(ixp425_softc->sc_dmat, sizeof(uint32_t), 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
nbuf * sizeof(struct npehwbuf), 1,
nbuf * sizeof(struct npehwbuf), 0,
@ -1445,7 +1445,7 @@ npestop(struct npe_softc *sc)
/*
* The MAC core rx/tx disable may leave the MAC hardware in an
* unpredictable state. A hw reset is executed before resetting
* unpredictable state. A hw reset is executed before resetting
* all the MAC parameters to a known value.
*/
WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET);

14
sys/arm/xscale/ixp425/if_npereg.h
View File

@ -32,7 +32,7 @@
/*
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -44,8 +44,8 @@
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -253,19 +253,19 @@ struct npestats {
/* NB: shorthands for mii bus mdio routines */
#define NPE_MAC_MDIO_CMD NPE_MAC_MDIO_CMD_1
#define NPE_MAC_MDIO_STS NPE_MAC_MDIO_STS_1
#define NPE_MII_GO (1<<31)
#define NPE_MII_WRITE (1<<26)
#define NPE_MII_TIMEOUT_10TH_SECS 5
#define NPE_MII_TIMEOUT_10TH_SECS 5
#define NPE_MII_10TH_SEC_IN_MILLIS 100
#define NPE_MII_READ_FAIL (1<<31)
#define NPE_MII_PHY_DEF_DELAY 300 /* max delay before link up, etc. */
#define NPE_MII_PHY_NO_DELAY 0x0 /* do not delay */
#define NPE_MII_PHY_NULL 0xff /* PHY is not present */
#define NPE_MII_PHY_DEF_ADDR 0x0 /* default PHY's logical address */
/* Register definition */
/* Register definition */
#define NPE_MII_CTRL_REG 0x0 /* Control Register */
#define NPE_MII_STAT_REG 0x1 /* Status Register */
#define NPE_MII_PHY_ID1_REG 0x2 /* PHY identifier 1 Register */

12
sys/arm/xscale/ixp425/ixp425.c
View File

@ -177,7 +177,7 @@ ixp425_set_gpio(struct ixp425_softc *sc, int pin, int type)
gpiotr | GPIO_TYPE(pin, type));
/* configure gpio line as an input */
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER,
GPIO_CONF_WRITE_4(sc, IXP425_GPIO_GPOER,
GPIO_CONF_READ_4(sc, IXP425_GPIO_GPOER) | (1<<pin));
IXP4XX_GPIO_UNLOCK();
}
@ -330,7 +330,7 @@ ixp425_attach(device_t dev)
cambria_exp_bus_init(sc);
if (bus_dma_tag_create(NULL, 1, 0, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
NULL, NULL, &sc->sc_dmat))
panic("%s: failed to create dma tag", __func__);
@ -534,7 +534,7 @@ ixp425_alloc_resource(device_t dev, device_t child, int type, int *rid,
device_printf(child,
"%s: assign 0x%lx:0x%lx%s\n",
__func__, start, end - start,
vtrans->isa4x ? " A4X" :
vtrans->isa4x ? " A4X" :
vtrans->isslow ? " SLOW" : "");
}
} else
@ -602,7 +602,7 @@ ixp425_activate_resource(device_t dev, device_t child, int type, int rid,
static int
ixp425_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
struct resource *r)
{
/* NB: no private resources, just deactive */
return (rman_deactivate_resource(r));
@ -635,8 +635,8 @@ update_masks(uint32_t mask, uint32_t mask2)
static int
ixp425_setup_intr(device_t dev, device_t child,
struct resource *res, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
struct resource *res, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
uint32_t mask, mask2;
int error;

8
sys/arm/xscale/ixp425/ixp425_iic.c
View File

@ -100,7 +100,7 @@ ixpiic_callback(device_t dev, int index, caddr_t data)
return (0);
}
static int
static int
ixpiic_getscl(device_t dev)
{
struct ixpiic_softc *sc = ixpiic_sc;
@ -114,7 +114,7 @@ ixpiic_getscl(device_t dev)
return (reg & GPIO_I2C_SCL_BIT);
}
static int
static int
ixpiic_getsda(device_t dev)
{
struct ixpiic_softc *sc = ixpiic_sc;
@ -128,7 +128,7 @@ ixpiic_getsda(device_t dev)
return (reg & GPIO_I2C_SDA_BIT);
}
static void
static void
ixpiic_setsda(device_t dev, int val)
{
struct ixpiic_softc *sc = ixpiic_sc;
@ -143,7 +143,7 @@ ixpiic_setsda(device_t dev, int val)
DELAY(I2C_DELAY);
}
static void
static void
ixpiic_setscl(device_t dev, int val)
{
struct ixpiic_softc *sc = ixpiic_sc;

40
sys/arm/xscale/ixp425/ixp425_npe.c
View File

@ -30,7 +30,7 @@
/*-
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -42,8 +42,8 @@
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -135,7 +135,7 @@ static struct ixpnpe_softc *npes[NPE_MAX];
/*
* masks used to extract address info from State information context
* register addresses as read from microcode image
* register addresses as read from microcode image
*/
#define IX_NPEDL_MASK_STATE_ADDR_CTXT_REG 0x0000000F
#define IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM 0x000000F0
@ -332,7 +332,7 @@ ixpnpe_attach(device_t dev, int npeid)
NULL, ixpnpe_intr, sc, &sc->sc_ih);
/*
* Enable output fifo interrupts (NB: must also set OFIFO Write Enable)
*/
*/
npe_reg_write(sc, IX_NPECTL,
npe_reg_read(sc, IX_NPECTL) | (IX_NPECTL_OFE | IX_NPECTL_OFWE));
@ -347,7 +347,7 @@ ixpnpe_detach(struct ixpnpe_softc *sc)
if (--sc->sc_nrefs == 0) {
npes[sc->sc_npeid] = NULL;
/* disable output fifo interrupts */
/* disable output fifo interrupts */
npe_reg_write(sc, IX_NPECTL,
npe_reg_read(sc, IX_NPECTL) &~ (IX_NPECTL_OFE | IX_NPECTL_OFWE));
@ -671,7 +671,7 @@ npe_load_stateinfo(struct ixpnpe_softc *sc,
const IxNpeDlNpeMgrStateInfoBlock *bp, int verify)
{
int i, nentries, error;
npe_cpu_step_save(sc);
/* for each state-info context register entry in block */
@ -683,7 +683,7 @@ npe_load_stateinfo(struct ixpnpe_softc *sc,
uint32_t addrInfo = bp->ctxtRegEntry[i].addressInfo;
uint32_t reg = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_REG);
uint32_t cNum = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
uint32_t cNum = (addrInfo & IX_NPEDL_MASK_STATE_ADDR_CTXT_NUM) >>
IX_NPEDL_OFFSET_STATE_ADDR_CTXT_NUM;
/* error-check Context Register No. and Context Number values */
@ -692,13 +692,13 @@ npe_load_stateinfo(struct ixpnpe_softc *sc,
"invalid Context Register %u\n", reg);
error = EINVAL;
break;
}
}
if (!(0 <= cNum && cNum < IX_NPEDL_CTXT_NUM_MAX)) {
device_printf(sc->sc_dev,
"invalid Context Number %u\n", cNum);
error = EINVAL;
break;
}
}
/* NOTE that there is no STEVT register for Context 0 */
if (cNum == 0 && reg == IX_NPEDL_CTXT_REG_STEVT) {
device_printf(sc->sc_dev,
@ -735,7 +735,7 @@ npe_load_image(struct ixpnpe_softc *sc,
/*
* Read Download Map, checking each block type and calling
* appropriate function to perform download
* appropriate function to perform download
*/
error = 0;
downloadMap = (const IxNpeDlNpeMgrDownloadMap *) imageCodePtr;
@ -844,7 +844,7 @@ npe_cpu_reset(struct ixpnpe_softc *sc)
(ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK));
DPRINTFn(2, sc->sc_dev, "%s: dis parity int, CTL => 0x%x\n",
__func__, ixNpeConfigCtrlRegVal & IX_NPEDL_PARITY_BIT_MASK);
npe_cpu_step_save(sc);
/*
@ -873,7 +873,7 @@ npe_cpu_reset(struct ixpnpe_softc *sc)
DPRINTF(sc->sc_dev, "%s: cannot step (1), error %u\n",
__func__, error);
npe_cpu_step_restore(sc);
return error;
return error;
}
}
@ -888,10 +888,10 @@ npe_cpu_reset(struct ixpnpe_softc *sc)
DPRINTF(sc->sc_dev, "%s: cannot step (2), error %u\n",
__func__, error);
npe_cpu_step_restore(sc);
return error;
return error;
}
/*
/*
* Reset the physical registers in the NPE register file:
* Note: no need to save/restore REGMAP for Context 0 here
* since all Context Store regs are reset in subsequent code.
@ -965,7 +965,7 @@ npe_cpu_reset(struct ixpnpe_softc *sc)
error = npe_cpu_stop(sc);
/* restore NPE configuration bus Control Register - Parity Settings */
npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL,
npe_reg_write(sc, IX_NPEDL_REG_OFFSET_CTL,
(ixNpeConfigCtrlRegVal & IX_NPEDL_CONFIG_CTRL_REG_MASK));
DPRINTFn(2, sc->sc_dev, "%s: restore CTL => 0x%x\n",
__func__, npe_reg_read(sc, IX_NPEDL_REG_OFFSET_CTL));
@ -1189,10 +1189,10 @@ npe_cpu_step(struct ixpnpe_softc *sc, uint32_t npeInstruction,
newWatchcount == oldWatchcount; tries++) {
/* Watch Count register incr's when NPE completes an inst */
newWatchcount = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_WC);
}
}
return (tries < IX_NPE_DL_MAX_NUM_OF_RETRIES) ? 0 : EIO;
#undef IX_NPE_DL_MAX_NUM_OF_RETRIES
}
}
static void
npe_cpu_step_restore(struct ixpnpe_softc *sc)
@ -1283,7 +1283,7 @@ npe_logical_reg_write(struct ixpnpe_softc *sc, uint32_t regAddr, uint32_t regVal
} else {
uint32_t npeInstruction;
switch (regSize) {
switch (regSize) {
case IX_NPEDL_REG_SIZE_BYTE:
npeInstruction = IX_NPEDL_INSTR_WR_REG_BYTE;
regVal &= 0xff;
@ -1353,7 +1353,7 @@ npe_physical_reg_write(struct ixpnpe_softc *sc,
/* regAddr = 0 or 4 */
regAddr = (regAddr & IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR) *
sizeof(uint32_t);
error = npe_logical_reg_write(sc, regAddr, regValue,
error = npe_logical_reg_write(sc, regAddr, regValue,
IX_NPEDL_REG_SIZE_WORD, 0, verify);
}
return error;

20
sys/arm/xscale/ixp425/ixp425_npereg.h
View File

@ -32,7 +32,7 @@
/*-
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -44,8 +44,8 @@
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -93,7 +93,7 @@
(((imageId) >> 0) & 0xff)
/*
* Instruction and Data Memory Size (in words) for each NPE
* Instruction and Data Memory Size (in words) for each NPE
*/
#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
#define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
@ -135,7 +135,7 @@
#define IX_NPEDL_MASK_STAT_IFNE 0x00080000 /* IFNE bit */
/*
* EXCTL (Execution Control) Register commands
* EXCTL (Execution Control) Register commands
*/
#define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01 /* Step 1 instruction */
#define IX_NPEDL_EXCTL_CMD_NPE_START 0x02 /* Start execution */
@ -164,7 +164,7 @@
#define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000 /* pipeline Klean */
/*
* Executing Context Stack (ECS) level registers
* Executing Context Stack (ECS) level registers
*/
#define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00 /* reg 0 @ bg ctx */
#define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01 /* reg 1 @ bg ctx */
@ -220,14 +220,14 @@
* Bit-Offsets from LSB of particular bit-fields in Execution Access registers.
*/
#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
/*
* NPE core & co-processor instruction templates to load into NPE Instruction
* NPE core & co-processor instruction templates to load into NPE Instruction
* Register, for read/write of NPE register file registers.
*/
@ -268,7 +268,7 @@
* Write a 16-bit NPE internal logical register.
* NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
*/
#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
#define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
/*
* Reset Mailbox (MBST) register
@ -292,7 +292,7 @@
* Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
* SRC field of immediate-mode NPE instruction
*/
#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
/**
* Mask the bits of 16-bit data value (most-sig 11 bits) to be used in

14
sys/arm/xscale/ixp425/ixp425_pci.c
View File

@ -132,10 +132,10 @@ ixppcib_attach(device_t dev)
/* NB: PCI dma window is 64M so anything above must be bounced */
if (bus_dma_tag_create(NULL, 1, 0, IXP425_AHB_OFFSET + 64 * 1024 * 1024,
BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
BUS_SPACE_MAXADDR, NULL, NULL, 0xffffffff, 0xff, 0xffffffff, 0,
NULL, NULL, &sc->sc_dmat))
panic("couldn't create the PCI dma tag !");
/*
/*
* The PCI bus can only address 64MB. However, due to the way our
* implementation of busdma works, busdma can't tell if a device
* is a PCI device or not. So defaults to the PCI dma tag, which
@ -155,7 +155,7 @@ ixppcib_attach(device_t dev)
sc->sc_io_rman.rm_type = RMAN_ARRAY;
sc->sc_io_rman.rm_descr = "IXP4XX PCI I/O Ports";
if (rman_init(&sc->sc_io_rman) != 0 ||
rman_manage_region(&sc->sc_io_rman, 0,
rman_manage_region(&sc->sc_io_rman, 0,
IXP425_PCI_IO_SIZE) != 0) {
panic("ixppcib_probe: failed to set up I/O rman");
}
@ -259,7 +259,7 @@ ixppcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
static int
ixppcib_setup_intr(device_t dev, device_t child, struct resource *ires,
int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
void **cookiep)
{
@ -318,11 +318,11 @@ ixppcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
static int
ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
struct resource *r)
{
struct ixppcib_softc *sc = device_get_softc(bus);
switch (type) {
case SYS_RES_IOPORT:
rman_set_bustag(r, &sc->sc_pci_iot);
@ -340,7 +340,7 @@ ixppcib_activate_resource(device_t bus, device_t child, int type, int rid,
static int
ixppcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
struct resource *r)
{
device_printf(bus, "%s called deactivate_resource (unexpected)\n",

2
sys/arm/xscale/ixp425/ixp425_pci_space.c
View File

@ -443,7 +443,7 @@ ixp425_pci_mem_bs_alloc(void *t, bus_addr_t rstart, bus_addr_t rend,
panic("ixp425_mem_bs_alloc(): not implemented\n");
}
void
void
ixp425_pci_mem_bs_free(void *t, bus_space_handle_t bsh, bus_size_t size)
{
panic("ixp425_mem_bs_free(): not implemented\n");

46
sys/arm/xscale/ixp425/ixp425_qmgr.c
View File

@ -30,7 +30,7 @@
/*-
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -42,8 +42,8 @@
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -124,7 +124,7 @@ struct qmgrInfo {
#if 0
/* NB: needed only for A0 parts */
u_int statusWordOffset; /* status word offset */
uint32_t statusMask; /* status mask */
uint32_t statusMask; /* status mask */
uint32_t statusCheckValue; /* status check value */
#endif
};
@ -257,7 +257,7 @@ ixpqmgr_attach(device_t dev)
qi->cb = dummyCallback;
qi->priority = IX_QMGR_Q_PRIORITY_0; /* default priority */
/*
/*
* There are two interrupt registers, 32 bits each. One
* for the lower queues(0-31) and one for the upper
* queues(32-63). Therefore need to mod by 32 i.e the
@ -280,17 +280,17 @@ ixpqmgr_attach(device_t dev)
if (i < IX_QMGR_MIN_QUEUPP_QID) {
/* AQM Q underflow/overflow status reg address, per queue */
qi->qUOStatRegAddr = IX_QMGR_QUEUOSTAT0_OFFSET +
((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
((i / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD) *
sizeof(uint32_t));
/* AQM Q underflow status bit masks for status reg per queue */
qi->qUflowStatBitMask =
qi->qUflowStatBitMask =
(IX_QMGR_UNDERFLOW_BIT_OFFSET + 1) <<
((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
(32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
/* AQM Q overflow status bit masks for status reg, per queue */
qi->qOflowStatBitMask =
qi->qOflowStatBitMask =
(IX_QMGR_OVERFLOW_BIT_OFFSET + 1) <<
((i & (IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD - 1)) *
(32 / IX_QMGR_QUEUOSTAT_NUM_QUE_PER_WORD));
@ -302,7 +302,7 @@ ixpqmgr_attach(device_t dev)
/* AQM Q lower-group (0-31) status register bit offset */
qi->qStatBitsOffset =
(i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) *
(i & (IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD - 1)) *
(32 / IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD);
} else { /* AQM Q upper-group (32-63), only */
qi->qUOStatRegAddr = 0; /* XXX */
@ -405,7 +405,7 @@ ixpqmgr_qwrite(int qId, uint32_t entry)
int qPtrs;
/*
* Read the status twice because the status may
* Read the status twice because the status may
* not be immediately ready after the write operation
*/
if ((status & qi->qOflowStatBitMask) ||
@ -432,12 +432,12 @@ ixpqmgr_qwrite(int qId, uint32_t entry)
DPRINTFn(2, sc->sc_dev,
"%s(%u, 0x%x) Q full, no overflow status, qConfig 0x%x\n",
__func__, qId, entry, qPtrs);
qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
qPtrs = (qPtrs - (qPtrs >> 7)) & 0x7f;
if (qPtrs == 0) {
/*
* The queue may be full at the time of the
* snapshot. Next access will check
* The queue may be full at the time of the
* snapshot. Next access will check
* the overflow status again.
*/
qi->qWriteCount = qSize;
@ -460,7 +460,7 @@ ixpqmgr_qread(int qId, uint32_t *entry)
*entry = aqm_reg_read(sc, off);
/*
* Reset the current read count : next access to the read function
* Reset the current read count : next access to the read function
* will force a underflow status check.
*/
qi->qReadCount = 0;
@ -499,7 +499,7 @@ ixpqmgr_qreadm(int qId, uint32_t n, uint32_t *p)
*p = entry;
/*
* Reset the current read count : next access to the read function
* Reset the current read count : next access to the read function
* will force a underflow status check.
*/
qi->qReadCount = 0;
@ -667,7 +667,7 @@ ixpqmgr_rebuild(struct ixpqmgr_softc *sc)
/* low priority q's */
for (q = 0; q < IX_QMGR_MIN_QUEUPP_QID; q++) {
qi = &sc->qinfo[q];
if (qi->priority == pri) {
if (qi->priority == pri) {
/*
* Build the priority table bitmask which match the
* queues of the first half of the priority table.
@ -712,8 +712,8 @@ ixpqmgr_rebuild(struct ixpqmgr_softc *sc)
* 0x00000001 31
* 0x00000000 32
*
* The C version of this function is used as a replacement
* for system not providing the equivalent of the CLZ
* The C version of this function is used as a replacement
* for system not providing the equivalent of the CLZ
* assembly language instruction.
*
* Note that this version is big-endian
@ -819,7 +819,7 @@ aqm_calc_statuscheck(int qId, IxQMgrSourceId srcSel)
{
struct qmgrInfo *qi = &qinfo[qId];
uint32_t shiftVal;
if (qId < IX_QMGR_MIN_QUEUPP_QID) {
switch (srcSel) {
case IX_QMGR_Q_SOURCE_ID_E:
@ -863,7 +863,7 @@ aqm_calc_statuscheck(int qId, IxQMgrSourceId srcSel)
/* One nibble of status per queue so need to shift the
* check value and mask out to the correct position.
*/
shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
shiftVal = (qId % IX_QMGR_QUELOWSTAT_NUM_QUE_PER_WORD) *
IX_QMGR_QUELOWSTAT_BITS_PER_Q;
/* Calculate the which status word to check from the qId,
@ -970,7 +970,7 @@ aqm_qcfg(struct ixpqmgr_softc *sc, int qId, u_int ne, u_int nf)
/* baseAddress, calculated relative to start address */
baseAddress = sc->aqmFreeSramAddress;
/* base address must be word-aligned */
KASSERT((baseAddress % IX_QMGR_BASE_ADDR_16_WORD_ALIGN) == 0,
("address not word-aligned"));
@ -1007,7 +1007,7 @@ aqm_srcsel_write(struct ixpqmgr_softc *sc, int qId, int sourceId)
if (off == IX_QMGR_INT0SRCSELREG0_OFFSET && qId == 0) {
/* Queue 0 at INT0SRCSELREG should not corrupt the value bit-3 */
v |= 0x7;
} else {
} else {
const uint32_t bpq = 32 / IX_QMGR_INTSRC_NUM_QUE_PER_WORD;
uint32_t mask;
int qshift;
@ -1065,7 +1065,7 @@ aqm_reset(struct ixpqmgr_softc *sc)
IX_QMGR_INT0SRCSELREG_RESET_VALUE);
aqm_reg_write(sc, IX_QMGR_INT0SRCSELREG3_OFFSET,
IX_QMGR_INT0SRCSELREG_RESET_VALUE);
/* Reset queue interrupt enable register 0..1 */
aqm_reg_write(sc, IX_QMGR_QUEIEREG0_OFFSET,
IX_QMGR_QUEIEREG_RESET_VALUE);

8
sys/arm/xscale/ixp425/ixp425_qmgr.h
View File

@ -32,7 +32,7 @@
/*-
* Copyright (c) 2001-2005, Intel Corporation.
* All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -44,8 +44,8 @@
* 3. Neither the name of the Intel Corporation nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
*
*
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
@ -148,7 +148,7 @@
(((qId) * (IX_QMGR_QUEACC_SIZE * sizeof(uint32_t)))\
+ IX_QMGR_QUEACC0_OFFSET)
/*
/*
* Bit location of bit-3 of INT0SRCSELREG0 register to enabled
* sticky interrupt register.
*/

4
sys/arm/xscale/ixp425/ixp425reg.h
View File

@ -65,7 +65,7 @@
* 4000 0000 ---------------------------
* SDRAM
* 0000 0000 ---------------------------
*/
*/
/*
* Virtual memory map for the Intel IXP425/IXP435 integrated devices
@ -613,7 +613,7 @@
#define PMNC_EVCNT2_SHIFT 16
#define PMNC_EVCNT3_SHIFT 24
/*
/*
* Queue Manager
*/
#define IXP425_QMGR_HWBASE 0x60000000UL

2
sys/arm/xscale/pxa/if_smc_smi.c
View File

@ -37,7 +37,7 @@ __FBSDID("$FreeBSD$");
#include <machine/bus.h>
#include <machine/resource.h>
#include <net/ethernet.h>
#include <net/ethernet.h>
#include <net/if.h>
#include <net/if_arp.h>
#include <net/if_media.h>

11
sys/arm/xscale/pxa/pxa_machdep.c
View File

@ -40,7 +40,7 @@
*
* Machine dependant functions for kernel setup
*
* This file needs a lot of work.
* This file needs a lot of work.
*
* Created : 17/09/94
*/
@ -141,7 +141,7 @@ static void pxa_probe_sdram(bus_space_tag_t, bus_space_handle_t,
/* Static device mappings. */
static const struct pmap_devmap pxa_devmap[] = {
/*
/*
* Map the on-board devices up into the KVA region so we don't muck
* up user-space.
*/
@ -174,9 +174,8 @@ initarm(struct arm_boot_params *abp)
int i, j;
uint32_t memsize[PXA2X0_SDRAM_BANKS], memstart[PXA2X0_SDRAM_BANKS];
lastaddr = parse_boot_param(abp);
set_cpufuncs();
lastaddr = fake_preload_metadata();
pcpu_init(pcpup, 0, sizeof(struct pcpu));
PCPU_SET(curthread, &thread0);
@ -205,7 +204,7 @@ initarm(struct arm_boot_params *abp)
kernel_pt_table[loop].pv_pa = freemempos +
(loop % (PAGE_SIZE / L2_TABLE_SIZE_REAL)) *
L2_TABLE_SIZE_REAL;
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_va =
kernel_pt_table[loop].pv_pa + 0x20000000;
}
}
@ -280,7 +279,7 @@ initarm(struct arm_boot_params *abp)
pmap_link_l2pt(l1pagetable, afterkern + i * 0x00100000,
&kernel_pt_table[KERNEL_PT_AFKERNEL + i]);
}
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
pmap_map_entry(l1pagetable, afterkern, minidataclean.pv_pa,
VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
#ifdef ARM_USE_SMALL_ALLOC

4
sys/arm/xscale/pxa/pxareg.h
View File

@ -16,7 +16,7 @@
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Genetec Corporation.
* 4. The name of Genetec Corporation may not be used to endorse or
* 4. The name of Genetec Corporation may not be used to endorse or
* promote products derived from this software without specific prior
* written permission.
*
@ -139,7 +139,7 @@
/* width of interrupt controller */
#define ICU_LEN 32 /* but [0..7,15,16] is not used */
#define ICU_INT_HWMASK 0xffffff00
#define PXA250_IRQ_MIN 8 /* 0..7 are not used by integrated
#define PXA250_IRQ_MIN 8 /* 0..7 are not used by integrated
peripherals */
#define PXA270_IRQ_MIN 0