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Overhaul MII register access routine and remove unnecessary
BGE_MI_MODE register accesses. Previously bge(4) used to read BGE_MI_MODE register to detect whether it needs to disable autopolling feature or not. Because we don't touch autopolling in other part of driver there is no reason to read BGE_MI_MODE register given that we know default value in advance. In order to achieve the goal, check whether the controller has CPMU(Central Power Mangement Unit) capability. If controller has CPMU feature, use 500KHz MII management interface(mdio/mdc) frequency regardless core clock frequency. Otherwise use default MII clock. While I'm here, add CPMU register definition. In bge_miibus_readreg(), rearrange code a bit and remove goto statement. In bge_miibus_writereg(), make sure to restore autopolling even if MII write failed. The delay time inserted after accessing BGE_MI_MODE register increased from 40us to 80us. The default PHY address is now stored in softc. All PHYs supported by bge(4) currently uses PHY address 1 but it will be changed when we add newer controllers. This change will make it easier to change default PHY address depending on PHY models. Submitted by: davidch
This commit is contained in:
Pyun YongHyeon
parent
8d4380adbf
commit
a813ed787f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=213485
@ -768,38 +768,34 @@ static int
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bge_miibus_readreg(device_t dev, int phy, int reg)
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{
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struct bge_softc *sc;
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uint32_t val, autopoll;
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uint32_t val;
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int i;
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sc = device_get_softc(dev);
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/*
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* Broadcom's own driver always assumes the internal
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* PHY is at GMII address 1. On some chips, the PHY responds
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* to accesses at all addresses, which could cause us to
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* bogusly attach the PHY 32 times at probe type. Always
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* restricting the lookup to address 1 is simpler than
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* trying to figure out which chips revisions should be
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* special-cased.
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*/
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if (phy != 1)
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/* Prevent the probe from finding incorrect devices. */
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if (phy != sc->bge_phy_addr)
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return (0);
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/* Reading with autopolling on may trigger PCI errors */
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autopoll = CSR_READ_4(sc, BGE_MI_MODE);
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if (autopoll & BGE_MIMODE_AUTOPOLL) {
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BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
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DELAY(40);
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/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
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if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
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CSR_WRITE_4(sc, BGE_MI_MODE,
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sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
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DELAY(80);
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}
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CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
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BGE_MIPHY(phy) | BGE_MIREG(reg));
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/* Poll for the PHY register access to complete. */
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for (i = 0; i < BGE_TIMEOUT; i++) {
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DELAY(10);
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val = CSR_READ_4(sc, BGE_MI_COMM);
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if (!(val & BGE_MICOMM_BUSY))
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if ((val & BGE_MICOMM_BUSY) == 0) {
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DELAY(5);
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val = CSR_READ_4(sc, BGE_MI_COMM);
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break;
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}
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}
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if (i == BGE_TIMEOUT) {
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@ -807,16 +803,12 @@ bge_miibus_readreg(device_t dev, int phy, int reg)
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"PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
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phy, reg, val);
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val = 0;
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goto done;
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}
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DELAY(5);
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val = CSR_READ_4(sc, BGE_MI_COMM);
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done:
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if (autopoll & BGE_MIMODE_AUTOPOLL) {
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BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
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DELAY(40);
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/* Restore the autopoll bit if necessary. */
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if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
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CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
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DELAY(80);
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}
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if (val & BGE_MICOMM_READFAIL)
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@ -829,7 +821,6 @@ static int
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bge_miibus_writereg(device_t dev, int phy, int reg, int val)
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{
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struct bge_softc *sc;
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uint32_t autopoll;
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int i;
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sc = device_get_softc(dev);
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@ -838,11 +829,11 @@ bge_miibus_writereg(device_t dev, int phy, int reg, int val)
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(reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
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return (0);
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/* Reading with autopolling on may trigger PCI errors */
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autopoll = CSR_READ_4(sc, BGE_MI_MODE);
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if (autopoll & BGE_MIMODE_AUTOPOLL) {
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BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
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DELAY(40);
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/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
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if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
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CSR_WRITE_4(sc, BGE_MI_MODE,
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sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
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DELAY(80);
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}
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CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
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@ -857,17 +848,16 @@ bge_miibus_writereg(device_t dev, int phy, int reg, int val)
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}
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}
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if (i == BGE_TIMEOUT) {
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/* Restore the autopoll bit if necessary. */
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if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
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CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
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DELAY(80);
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}
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if (i == BGE_TIMEOUT)
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device_printf(sc->bge_dev,
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"PHY write timed out (phy %d, reg %d, val %d)\n",
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phy, reg, val);
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return (0);
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}
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if (autopoll & BGE_MIMODE_AUTOPOLL) {
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BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
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DELAY(40);
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}
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return (0);
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}
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@ -2502,6 +2492,9 @@ bge_attach(device_t dev)
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sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
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sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
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/* Set default PHY address. */
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sc->bge_phy_addr = 1;
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/*
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* Don't enable Ethernet@WireSpeed for the 5700, 5906, or the
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* 5705 A0 and A1 chips.
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@ -2575,6 +2568,17 @@ bge_attach(device_t dev)
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sc->bge_phy_flags |= BGE_PHY_BER_BUG;
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}
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/* Identify the chips that use an CPMU. */
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if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
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sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
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sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
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sc->bge_asicrev == BGE_ASICREV_BCM57780)
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sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
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if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
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sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
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else
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sc->bge_mi_mode = BGE_MIMODE_BASE;
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/*
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* All controllers that are not 5755 or higher have 4GB
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* boundary DMA bug.
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@ -863,9 +863,12 @@
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#define BGE_MISTS_LINK 0x00000001
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#define BGE_MISTS_10MBPS 0x00000002
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#define BGE_MIMODE_CLK_10MHZ 0x00000001
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#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
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#define BGE_MIMODE_AUTOPOLL 0x00000010
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#define BGE_MIMODE_CLKCNT 0x001F0000
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#define BGE_MIMODE_500KHZ_CONST 0x00008000
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#define BGE_MIMODE_BASE 0x000C0000
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/*
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@ -1221,6 +1224,51 @@
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/* Receive List Selector Status register */
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#define BGE_RXLSSTAT_ERROR 0x00000004
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#define BGE_CPMU_CTRL 0x3600
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#define BGE_CPMU_LSPD_10MB_CLK 0x3604
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#define BGE_CPMU_LSPD_1000MB_CLK 0x360C
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#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610
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#define BGE_CPMU_HST_ACC 0x361C
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#define BGE_CPMU_CLCK_STAT 0x3630
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#define BGE_CPMU_MUTEX_REQ 0x365C
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#define BGE_CPMU_MUTEX_GNT 0x3660
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#define BGE_CPMU_PHY_STRAP 0x3664
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/* Central Power Management Unit (CPMU) register */
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#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200
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#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400
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#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000
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#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
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/* Link Speed 10MB/No Link Power Mode Clock Policy register */
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#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000
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#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
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/* Link Speed 1000MB Power Mode Clock Policy register */
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#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
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#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
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#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000
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/* Link Aware Power Mode Clock Policy register */
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#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000
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#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
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#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000
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#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000
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/* CPMU Clock Status register */
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#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000
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#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
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#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
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#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
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/* CPMU Mutex Request register */
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#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000
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#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000
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/* CPMU GPHY Strap register */
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#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020
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/*
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* Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
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*/
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@ -2665,6 +2713,7 @@ struct bge_softc {
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#define BGE_FLAG_JUMBO 0x00000002
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#define BGE_FLAG_EADDR 0x00000008
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#define BGE_FLAG_MII_SERDES 0x00000010
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#define BGE_FLAG_CPMU_PRESENT 0x00000020
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#define BGE_FLAG_MSI 0x00000100
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#define BGE_FLAG_PCIX 0x00000200
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#define BGE_FLAG_PCIE 0x00000400
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@ -2707,7 +2756,9 @@ struct bge_softc {
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uint32_t bge_rx_max_coal_bds;
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uint32_t bge_tx_max_coal_bds;
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uint32_t bge_tx_buf_ratio;
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uint32_t bge_mi_mode;
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int bge_if_flags;
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int bge_phy_addr;
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int bge_txcnt;
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int bge_link; /* link state */
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int bge_link_evt; /* pending link event */
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