mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-30 16:51:41 +00:00
Merge ^/head r279759 through r279892.
This commit is contained in:
Dimitry Andric
commit
a857c4c833
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang360-import/; revision=279893
@ -41,7 +41,7 @@
|
||||
|
||||
dtrace:::BEGIN
|
||||
{
|
||||
printf("%-22s %8s %6s\n", "TIME", "LASTPID", "PID/s");
|
||||
printf("%-22s %6s\n", "TIME", "PID/s");
|
||||
pids = 0;
|
||||
}
|
||||
|
||||
@ -52,6 +52,6 @@ proc:::exec-success
|
||||
|
||||
profile:::tick-1sec
|
||||
{
|
||||
printf("%-22Y %8d %6d\n", walltimestamp, `mpid, pids);
|
||||
printf("%-22Y %6d\n", walltimestamp, pids);
|
||||
pids = 0;
|
||||
}
|
||||
|
||||
@ -583,10 +583,10 @@ ctf_discard(ctf_file_t *fp)
|
||||
return (0); /* no update required */
|
||||
|
||||
for (dtd = ctf_list_prev(&fp->ctf_dtdefs); dtd != NULL; dtd = ntd) {
|
||||
if (dtd->dtd_type <= fp->ctf_dtoldid)
|
||||
ntd = ctf_list_prev(dtd);
|
||||
if (CTF_TYPE_TO_INDEX(dtd->dtd_type) <= fp->ctf_dtoldid)
|
||||
continue; /* skip types that have been committed */
|
||||
|
||||
ntd = ctf_list_prev(dtd);
|
||||
ctf_dtd_delete(fp, dtd);
|
||||
}
|
||||
|
||||
@ -1313,10 +1313,13 @@ ctf_add_type(ctf_file_t *dst_fp, ctf_file_t *src_fp, ctf_id_t src_type)
|
||||
* unless dst_type is a forward declaration and src_type is a struct,
|
||||
* union, or enum (i.e. the definition of the previous forward decl).
|
||||
*/
|
||||
if (dst_type != CTF_ERR && dst_kind != kind && (
|
||||
dst_kind != CTF_K_FORWARD || (kind != CTF_K_ENUM &&
|
||||
kind != CTF_K_STRUCT && kind != CTF_K_UNION)))
|
||||
return (ctf_set_errno(dst_fp, ECTF_CONFLICT));
|
||||
if (dst_type != CTF_ERR && dst_kind != kind) {
|
||||
if (dst_kind != CTF_K_FORWARD || (kind != CTF_K_ENUM &&
|
||||
kind != CTF_K_STRUCT && kind != CTF_K_UNION))
|
||||
return (ctf_set_errno(dst_fp, ECTF_CONFLICT));
|
||||
else
|
||||
dst_type = CTF_ERR;
|
||||
}
|
||||
|
||||
/*
|
||||
* If the non-empty name was not found in the appropriate hash, search
|
||||
@ -1328,7 +1331,7 @@ ctf_add_type(ctf_file_t *dst_fp, ctf_file_t *src_fp, ctf_id_t src_type)
|
||||
*/
|
||||
if (dst_type == CTF_ERR && name[0] != '\0') {
|
||||
for (dtd = ctf_list_prev(&dst_fp->ctf_dtdefs); dtd != NULL &&
|
||||
dtd->dtd_type > dst_fp->ctf_dtoldid;
|
||||
CTF_TYPE_TO_INDEX(dtd->dtd_type) > dst_fp->ctf_dtoldid;
|
||||
dtd = ctf_list_prev(dtd)) {
|
||||
if (CTF_INFO_KIND(dtd->dtd_data.ctt_info) == kind &&
|
||||
dtd->dtd_name != NULL &&
|
||||
|
||||
@ -23,8 +23,6 @@
|
||||
* Use is subject to license terms.
|
||||
*/
|
||||
|
||||
#pragma ident "%Z%%M% %I% %E% SMI"
|
||||
|
||||
/*
|
||||
* Routines for preparing tdata trees for conversion into CTF data, and
|
||||
* for placing the resulting data into an output file.
|
||||
|
||||
@ -383,6 +383,9 @@ sctp_opt_info(int sd, sctp_assoc_t id, int opt, void *arg, socklen_t * size)
|
||||
case SCTP_PR_ASSOC_STATUS:
|
||||
((struct sctp_prstatus *)arg)->sprstat_assoc_id = id;
|
||||
break;
|
||||
case SCTP_MAX_CWND:
|
||||
((struct sctp_assoc_value *)arg)->assoc_id = id;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
@ -56,12 +56,54 @@ ENTRY(_setjmp)
|
||||
mr %r10,%r1
|
||||
mr %r9,%r2
|
||||
stmw %r9,20(%r3)
|
||||
|
||||
/* FPRs */
|
||||
stfd %f14,92+0*8(%r3)
|
||||
stfd %f15,92+1*8(%r3)
|
||||
stfd %f16,92+2*8(%r3)
|
||||
stfd %f17,92+3*8(%r3)
|
||||
stfd %f18,92+4*8(%r3)
|
||||
stfd %f19,92+5*8(%r3)
|
||||
stfd %f20,92+6*8(%r3)
|
||||
stfd %f21,92+7*8(%r3)
|
||||
stfd %f22,92+8*8(%r3)
|
||||
stfd %f23,92+9*8(%r3)
|
||||
stfd %f24,92+10*8(%r3)
|
||||
stfd %f25,92+11*8(%r3)
|
||||
stfd %f26,92+12*8(%r3)
|
||||
stfd %f27,92+13*8(%r3)
|
||||
stfd %f28,93+13*8(%r3)
|
||||
stfd %f29,93+14*8(%r3)
|
||||
stfd %f30,93+15*8(%r3)
|
||||
stfd %f31,93+16*8(%r3)
|
||||
|
||||
li %r3,0
|
||||
blr
|
||||
END(_setjmp)
|
||||
|
||||
ENTRY(_longjmp)
|
||||
lmw %r9,20(%r3)
|
||||
|
||||
/* FPRs */
|
||||
lfd %f14,92+0*8(%r3)
|
||||
lfd %f15,92+1*8(%r3)
|
||||
lfd %f16,92+2*8(%r3)
|
||||
lfd %f17,92+3*8(%r3)
|
||||
lfd %f18,92+4*8(%r3)
|
||||
lfd %f19,92+5*8(%r3)
|
||||
lfd %f20,92+6*8(%r3)
|
||||
lfd %f21,92+7*8(%r3)
|
||||
lfd %f22,92+8*8(%r3)
|
||||
lfd %f23,92+9*8(%r3)
|
||||
lfd %f24,92+10*8(%r3)
|
||||
lfd %f25,92+11*8(%r3)
|
||||
lfd %f26,92+12*8(%r3)
|
||||
lfd %f27,92+13*8(%r3)
|
||||
lfd %f28,93+13*8(%r3)
|
||||
lfd %f29,93+14*8(%r3)
|
||||
lfd %f30,93+15*8(%r3)
|
||||
lfd %f31,93+16*8(%r3)
|
||||
|
||||
mtlr %r11
|
||||
mtcr %r12
|
||||
mr %r1,%r10
|
||||
|
||||
@ -66,6 +66,27 @@ ENTRY(setjmp)
|
||||
mr %r10,%r1 /* r10 <- stackptr */
|
||||
mr %r9,%r2 /* r9 <- global ptr */
|
||||
stmw %r9,20(%r6)
|
||||
|
||||
/* FPRs */
|
||||
stfd %f14,92+0*8(%r6)
|
||||
stfd %f15,92+1*8(%r6)
|
||||
stfd %f16,92+2*8(%r6)
|
||||
stfd %f17,92+3*8(%r6)
|
||||
stfd %f18,92+4*8(%r6)
|
||||
stfd %f19,92+5*8(%r6)
|
||||
stfd %f20,92+6*8(%r6)
|
||||
stfd %f21,92+7*8(%r6)
|
||||
stfd %f22,92+8*8(%r6)
|
||||
stfd %f23,92+9*8(%r6)
|
||||
stfd %f24,92+10*8(%r6)
|
||||
stfd %f25,92+11*8(%r6)
|
||||
stfd %f26,92+12*8(%r6)
|
||||
stfd %f27,92+13*8(%r6)
|
||||
stfd %f28,93+13*8(%r6)
|
||||
stfd %f29,93+14*8(%r6)
|
||||
stfd %f30,93+15*8(%r6)
|
||||
stfd %f31,93+16*8(%r6)
|
||||
|
||||
li %r3,0 /* return (0) */
|
||||
blr
|
||||
END(setjmp)
|
||||
@ -73,6 +94,27 @@ END(setjmp)
|
||||
WEAK_REFERENCE(CNAME(__longjmp), longjmp)
|
||||
ENTRY(__longjmp)
|
||||
lmw %r9,20(%r3) /* restore regs */
|
||||
|
||||
/* FPRs */
|
||||
lfd %f14,92+0*8(%r3)
|
||||
lfd %f15,92+1*8(%r3)
|
||||
lfd %f16,92+2*8(%r3)
|
||||
lfd %f17,92+3*8(%r3)
|
||||
lfd %f18,92+4*8(%r3)
|
||||
lfd %f19,92+5*8(%r3)
|
||||
lfd %f20,92+6*8(%r3)
|
||||
lfd %f21,92+7*8(%r3)
|
||||
lfd %f22,92+8*8(%r3)
|
||||
lfd %f23,92+9*8(%r3)
|
||||
lfd %f24,92+10*8(%r3)
|
||||
lfd %f25,92+11*8(%r3)
|
||||
lfd %f26,92+12*8(%r3)
|
||||
lfd %f27,92+13*8(%r3)
|
||||
lfd %f28,93+13*8(%r3)
|
||||
lfd %f29,93+14*8(%r3)
|
||||
lfd %f30,93+15*8(%r3)
|
||||
lfd %f31,93+16*8(%r3)
|
||||
|
||||
mr %r6,%r4 /* save val param */
|
||||
mtlr %r11 /* r11 -> link reg */
|
||||
mtcr %r12 /* r12 -> condition reg */
|
||||
|
||||
@ -71,12 +71,54 @@ ENTRY(sigsetjmp)
|
||||
mr %r10,%r1
|
||||
mr %r9,%r2
|
||||
stmw %r9,20(%r6)
|
||||
|
||||
/* FPRs */
|
||||
stfd %f14,92+0*8(%r6)
|
||||
stfd %f15,92+1*8(%r6)
|
||||
stfd %f16,92+2*8(%r6)
|
||||
stfd %f17,92+3*8(%r6)
|
||||
stfd %f18,92+4*8(%r6)
|
||||
stfd %f19,92+5*8(%r6)
|
||||
stfd %f20,92+6*8(%r6)
|
||||
stfd %f21,92+7*8(%r6)
|
||||
stfd %f22,92+8*8(%r6)
|
||||
stfd %f23,92+9*8(%r6)
|
||||
stfd %f24,92+10*8(%r6)
|
||||
stfd %f25,92+11*8(%r6)
|
||||
stfd %f26,92+12*8(%r6)
|
||||
stfd %f27,92+13*8(%r6)
|
||||
stfd %f28,93+13*8(%r6)
|
||||
stfd %f29,93+14*8(%r6)
|
||||
stfd %f30,93+15*8(%r6)
|
||||
stfd %f31,93+16*8(%r6)
|
||||
|
||||
li %r3,0
|
||||
blr
|
||||
END(sigsetjmp)
|
||||
|
||||
ENTRY(siglongjmp)
|
||||
lmw %r9,20(%r3)
|
||||
|
||||
/* FPRs */
|
||||
lfd %f14,92+0*8(%r3)
|
||||
lfd %f15,92+1*8(%r3)
|
||||
lfd %f16,92+2*8(%r3)
|
||||
lfd %f17,92+3*8(%r3)
|
||||
lfd %f18,92+4*8(%r3)
|
||||
lfd %f19,92+5*8(%r3)
|
||||
lfd %f20,92+6*8(%r3)
|
||||
lfd %f21,92+7*8(%r3)
|
||||
lfd %f22,92+8*8(%r3)
|
||||
lfd %f23,92+9*8(%r3)
|
||||
lfd %f24,92+10*8(%r3)
|
||||
lfd %f25,92+11*8(%r3)
|
||||
lfd %f26,92+12*8(%r3)
|
||||
lfd %f27,92+13*8(%r3)
|
||||
lfd %f28,93+13*8(%r3)
|
||||
lfd %f29,93+14*8(%r3)
|
||||
lfd %f30,93+15*8(%r3)
|
||||
lfd %f31,93+16*8(%r3)
|
||||
|
||||
lwz %r7,0(%r3)
|
||||
mr %r6,%r4
|
||||
mtlr %r11
|
||||
|
||||
@ -56,23 +56,41 @@ ENTRY(_setjmp)
|
||||
mr %r10,%r1
|
||||
mr %r9,%r2
|
||||
std %r9,40 + 0*8(%r3)
|
||||
stfd %f14,40 + 23*8(%r3)
|
||||
std %r10,40 + 1*8(%r3)
|
||||
stfd %f15,40 + 24*8(%r3)
|
||||
std %r11,40 + 2*8(%r3)
|
||||
stfd %f16,40 + 25*8(%r3)
|
||||
std %r12,40 + 3*8(%r3)
|
||||
stfd %f17,40 + 26*8(%r3)
|
||||
std %r13,40 + 4*8(%r3)
|
||||
stfd %f18,40 + 27*8(%r3)
|
||||
std %r14,40 + 5*8(%r3)
|
||||
stfd %f19,40 + 28*8(%r3)
|
||||
std %r15,40 + 6*8(%r3)
|
||||
stfd %f20,40 + 29*8(%r3)
|
||||
std %r16,40 + 7*8(%r3)
|
||||
stfd %f21,40 + 30*8(%r3)
|
||||
std %r17,40 + 8*8(%r3)
|
||||
stfd %f22,40 + 31*8(%r3)
|
||||
std %r18,40 + 9*8(%r3)
|
||||
stfd %f23,40 + 32*8(%r3)
|
||||
std %r19,40 + 10*8(%r3)
|
||||
stfd %f24,40 + 33*8(%r3)
|
||||
std %r20,40 + 11*8(%r3)
|
||||
stfd %f25,40 + 34*8(%r3)
|
||||
std %r21,40 + 12*8(%r3)
|
||||
stfd %f26,40 + 35*8(%r3)
|
||||
std %r22,40 + 13*8(%r3)
|
||||
stfd %f27,40 + 36*8(%r3)
|
||||
std %r23,40 + 14*8(%r3)
|
||||
stfd %f28,40 + 37*8(%r3)
|
||||
std %r24,40 + 15*8(%r3)
|
||||
stfd %f29,40 + 38*8(%r3)
|
||||
std %r25,40 + 16*8(%r3)
|
||||
stfd %f30,40 + 39*8(%r3)
|
||||
std %r26,40 + 17*8(%r3)
|
||||
stfd %f31,40 + 40*8(%r3)
|
||||
std %r27,40 + 18*8(%r3)
|
||||
std %r28,40 + 19*8(%r3)
|
||||
std %r29,40 + 20*8(%r3)
|
||||
@ -84,23 +102,41 @@ END(_setjmp)
|
||||
|
||||
ENTRY(_longjmp)
|
||||
ld %r9,40 + 0*8(%r3)
|
||||
lfd %f14,40 + 23*8(%r3)
|
||||
ld %r10,40 + 1*8(%r3)
|
||||
lfd %f15,40 + 24*8(%r3)
|
||||
ld %r11,40 + 2*8(%r3)
|
||||
lfd %f16,40 + 25*8(%r3)
|
||||
ld %r12,40 + 3*8(%r3)
|
||||
lfd %f17,40 + 26*8(%r3)
|
||||
ld %r14,40 + 5*8(%r3)
|
||||
lfd %f18,40 + 27*8(%r3)
|
||||
ld %r15,40 + 6*8(%r3)
|
||||
lfd %f19,40 + 28*8(%r3)
|
||||
ld %r16,40 + 7*8(%r3)
|
||||
lfd %f20,40 + 29*8(%r3)
|
||||
ld %r17,40 + 8*8(%r3)
|
||||
lfd %f21,40 + 30*8(%r3)
|
||||
ld %r18,40 + 9*8(%r3)
|
||||
lfd %f22,40 + 31*8(%r3)
|
||||
ld %r19,40 + 10*8(%r3)
|
||||
lfd %f23,40 + 32*8(%r3)
|
||||
ld %r20,40 + 11*8(%r3)
|
||||
lfd %f24,40 + 33*8(%r3)
|
||||
ld %r21,40 + 12*8(%r3)
|
||||
lfd %f25,40 + 34*8(%r3)
|
||||
ld %r22,40 + 13*8(%r3)
|
||||
lfd %f26,40 + 35*8(%r3)
|
||||
ld %r23,40 + 14*8(%r3)
|
||||
lfd %f27,40 + 36*8(%r3)
|
||||
ld %r24,40 + 15*8(%r3)
|
||||
lfd %f28,40 + 37*8(%r3)
|
||||
ld %r25,40 + 16*8(%r3)
|
||||
lfd %f29,40 + 38*8(%r3)
|
||||
ld %r26,40 + 17*8(%r3)
|
||||
lfd %f30,40 + 39*8(%r3)
|
||||
ld %r27,40 + 18*8(%r3)
|
||||
lfd %f31,40 + 40*8(%r3)
|
||||
ld %r28,40 + 19*8(%r3)
|
||||
ld %r29,40 + 20*8(%r3)
|
||||
ld %r30,40 + 21*8(%r3)
|
||||
|
||||
@ -67,29 +67,49 @@ ENTRY(setjmp)
|
||||
mr %r9,%r2 /* r9 <- global ptr */
|
||||
|
||||
std %r9,40 + 0*8(%r6)
|
||||
stfd %f14,40 + 23*8(%r6)
|
||||
std %r10,40 + 1*8(%r6)
|
||||
stfd %f15,40 + 24*8(%r6)
|
||||
std %r11,40 + 2*8(%r6)
|
||||
stfd %f16,40 + 25*8(%r6)
|
||||
std %r12,40 + 3*8(%r6)
|
||||
stfd %f17,40 + 26*8(%r6)
|
||||
std %r13,40 + 4*8(%r6)
|
||||
stfd %f18,40 + 27*8(%r6)
|
||||
std %r14,40 + 5*8(%r6)
|
||||
stfd %f19,40 + 28*8(%r6)
|
||||
std %r15,40 + 6*8(%r6)
|
||||
stfd %f20,40 + 29*8(%r6)
|
||||
std %r16,40 + 7*8(%r6)
|
||||
stfd %f21,40 + 30*8(%r6)
|
||||
std %r17,40 + 8*8(%r6)
|
||||
stfd %f22,40 + 31*8(%r6)
|
||||
std %r18,40 + 9*8(%r6)
|
||||
stfd %f23,40 + 32*8(%r6)
|
||||
std %r19,40 + 10*8(%r6)
|
||||
stfd %f24,40 + 33*8(%r6)
|
||||
std %r20,40 + 11*8(%r6)
|
||||
stfd %f25,40 + 34*8(%r6)
|
||||
std %r21,40 + 12*8(%r6)
|
||||
stfd %f26,40 + 35*8(%r6)
|
||||
std %r22,40 + 13*8(%r6)
|
||||
stfd %f27,40 + 36*8(%r6)
|
||||
std %r23,40 + 14*8(%r6)
|
||||
stfd %f28,40 + 37*8(%r6)
|
||||
std %r24,40 + 15*8(%r6)
|
||||
stfd %f29,40 + 38*8(%r6)
|
||||
std %r25,40 + 16*8(%r6)
|
||||
stfd %f30,40 + 39*8(%r6)
|
||||
std %r26,40 + 17*8(%r6)
|
||||
stfd %f31,40 + 40*8(%r6)
|
||||
std %r27,40 + 18*8(%r6)
|
||||
std %r28,40 + 19*8(%r6)
|
||||
std %r29,40 + 20*8(%r6)
|
||||
std %r30,40 + 21*8(%r6)
|
||||
std %r31,40 + 22*8(%r6)
|
||||
|
||||
/* XXX Altivec regs */
|
||||
|
||||
li %r3,0 /* return (0) */
|
||||
blr
|
||||
END(setjmp)
|
||||
@ -97,23 +117,41 @@ END(setjmp)
|
||||
WEAK_REFERENCE(__longjmp, longjmp)
|
||||
ENTRY(__longjmp)
|
||||
ld %r9,40 + 0*8(%r3)
|
||||
lfd %f14,40 + 23*8(%r3)
|
||||
ld %r10,40 + 1*8(%r3)
|
||||
lfd %f15,40 + 24*8(%r3)
|
||||
ld %r11,40 + 2*8(%r3)
|
||||
lfd %f16,40 + 25*8(%r3)
|
||||
ld %r12,40 + 3*8(%r3)
|
||||
lfd %f17,40 + 26*8(%r3)
|
||||
ld %r14,40 + 5*8(%r3)
|
||||
lfd %f18,40 + 27*8(%r3)
|
||||
ld %r15,40 + 6*8(%r3)
|
||||
lfd %f19,40 + 28*8(%r3)
|
||||
ld %r16,40 + 7*8(%r3)
|
||||
lfd %f20,40 + 29*8(%r3)
|
||||
ld %r17,40 + 8*8(%r3)
|
||||
lfd %f21,40 + 30*8(%r3)
|
||||
ld %r18,40 + 9*8(%r3)
|
||||
lfd %f22,40 + 31*8(%r3)
|
||||
ld %r19,40 + 10*8(%r3)
|
||||
lfd %f23,40 + 32*8(%r3)
|
||||
ld %r20,40 + 11*8(%r3)
|
||||
lfd %f24,40 + 33*8(%r3)
|
||||
ld %r21,40 + 12*8(%r3)
|
||||
lfd %f25,40 + 34*8(%r3)
|
||||
ld %r22,40 + 13*8(%r3)
|
||||
lfd %f26,40 + 35*8(%r3)
|
||||
ld %r23,40 + 14*8(%r3)
|
||||
lfd %f27,40 + 36*8(%r3)
|
||||
ld %r24,40 + 15*8(%r3)
|
||||
lfd %f28,40 + 37*8(%r3)
|
||||
ld %r25,40 + 16*8(%r3)
|
||||
lfd %f29,40 + 38*8(%r3)
|
||||
ld %r26,40 + 17*8(%r3)
|
||||
lfd %f30,40 + 39*8(%r3)
|
||||
ld %r27,40 + 18*8(%r3)
|
||||
lfd %f31,40 + 40*8(%r3)
|
||||
ld %r28,40 + 19*8(%r3)
|
||||
ld %r29,40 + 20*8(%r3)
|
||||
ld %r30,40 + 21*8(%r3)
|
||||
|
||||
@ -72,23 +72,41 @@ ENTRY(sigsetjmp)
|
||||
mr %r9,%r2
|
||||
|
||||
std %r9,40 + 0*8(%r6)
|
||||
stfd %f14,40 + 23*8(%r6)
|
||||
std %r10,40 + 1*8(%r6)
|
||||
stfd %f15,40 + 24*8(%r6)
|
||||
std %r11,40 + 2*8(%r6)
|
||||
stfd %f16,40 + 25*8(%r6)
|
||||
std %r12,40 + 3*8(%r6)
|
||||
stfd %f17,40 + 26*8(%r6)
|
||||
std %r13,40 + 4*8(%r6)
|
||||
stfd %f18,40 + 27*8(%r6)
|
||||
std %r14,40 + 5*8(%r6)
|
||||
stfd %f19,40 + 28*8(%r6)
|
||||
std %r15,40 + 6*8(%r6)
|
||||
stfd %f20,40 + 29*8(%r6)
|
||||
std %r16,40 + 7*8(%r6)
|
||||
stfd %f21,40 + 30*8(%r6)
|
||||
std %r17,40 + 8*8(%r6)
|
||||
stfd %f22,40 + 31*8(%r6)
|
||||
std %r18,40 + 9*8(%r6)
|
||||
stfd %f23,40 + 32*8(%r6)
|
||||
std %r19,40 + 10*8(%r6)
|
||||
stfd %f24,40 + 33*8(%r6)
|
||||
std %r20,40 + 11*8(%r6)
|
||||
stfd %f25,40 + 34*8(%r6)
|
||||
std %r21,40 + 12*8(%r6)
|
||||
stfd %f26,40 + 35*8(%r6)
|
||||
std %r22,40 + 13*8(%r6)
|
||||
stfd %f27,40 + 36*8(%r6)
|
||||
std %r23,40 + 14*8(%r6)
|
||||
stfd %f28,40 + 37*8(%r6)
|
||||
std %r24,40 + 15*8(%r6)
|
||||
stfd %f29,40 + 38*8(%r6)
|
||||
std %r25,40 + 16*8(%r6)
|
||||
stfd %f30,40 + 39*8(%r6)
|
||||
std %r26,40 + 17*8(%r6)
|
||||
stfd %f31,40 + 40*8(%r6)
|
||||
std %r27,40 + 18*8(%r6)
|
||||
std %r28,40 + 19*8(%r6)
|
||||
std %r29,40 + 20*8(%r6)
|
||||
@ -101,23 +119,41 @@ END(sigsetjmp)
|
||||
|
||||
ENTRY(siglongjmp)
|
||||
ld %r9,40 + 0*8(%r3)
|
||||
lfd %f14,40 + 23*8(%r3)
|
||||
ld %r10,40 + 1*8(%r3)
|
||||
lfd %f15,40 + 24*8(%r3)
|
||||
ld %r11,40 + 2*8(%r3)
|
||||
lfd %f16,40 + 25*8(%r3)
|
||||
ld %r12,40 + 3*8(%r3)
|
||||
lfd %f17,40 + 26*8(%r3)
|
||||
ld %r14,40 + 5*8(%r3)
|
||||
lfd %f18,40 + 27*8(%r3)
|
||||
ld %r15,40 + 6*8(%r3)
|
||||
lfd %f19,40 + 28*8(%r3)
|
||||
ld %r16,40 + 7*8(%r3)
|
||||
lfd %f20,40 + 29*8(%r3)
|
||||
ld %r17,40 + 8*8(%r3)
|
||||
lfd %f21,40 + 30*8(%r3)
|
||||
ld %r18,40 + 9*8(%r3)
|
||||
lfd %f22,40 + 31*8(%r3)
|
||||
ld %r19,40 + 10*8(%r3)
|
||||
lfd %f23,40 + 32*8(%r3)
|
||||
ld %r20,40 + 11*8(%r3)
|
||||
lfd %f24,40 + 33*8(%r3)
|
||||
ld %r21,40 + 12*8(%r3)
|
||||
lfd %f25,40 + 34*8(%r3)
|
||||
ld %r22,40 + 13*8(%r3)
|
||||
lfd %f26,40 + 35*8(%r3)
|
||||
ld %r23,40 + 14*8(%r3)
|
||||
lfd %f27,40 + 36*8(%r3)
|
||||
ld %r24,40 + 15*8(%r3)
|
||||
lfd %f28,40 + 37*8(%r3)
|
||||
ld %r25,40 + 16*8(%r3)
|
||||
lfd %f29,40 + 38*8(%r3)
|
||||
ld %r26,40 + 17*8(%r3)
|
||||
lfd %f30,40 + 39*8(%r3)
|
||||
ld %r27,40 + 18*8(%r3)
|
||||
lfd %f31,40 + 40*8(%r3)
|
||||
ld %r28,40 + 19*8(%r3)
|
||||
ld %r29,40 + 20*8(%r3)
|
||||
ld %r30,40 + 21*8(%r3)
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
.\"
|
||||
.\" $FreeBSD$
|
||||
.\"
|
||||
.Dd November 17, 2014
|
||||
.Dd March 8, 2015
|
||||
.Dt GPIO 3
|
||||
.Os
|
||||
.Sh NAME
|
||||
@ -43,41 +43,43 @@
|
||||
.Ft void
|
||||
.Fn gpio_close "gpio_handle_t handle"
|
||||
.Ft int
|
||||
.Fn gpio_pin_list "gpio_handle_t handle, gpio_config_t **pcfgs"
|
||||
.Fn gpio_pin_list "gpio_handle_t handle" "gpio_config_t **pcfgs"
|
||||
.Ft int
|
||||
.Fn gpio_pin_config "gpio_handle_t handle, gpio_config *cfg"
|
||||
.Fn gpio_pin_config "gpio_handle_t handle" "gpio_config_t *cfg"
|
||||
.Ft int
|
||||
.Fn gpio_pin_set_flags "gpio_handle_t handle, gpio_config_t *cfg"
|
||||
.Fn gpio_pin_set_name "gpio_handle_t handle" "gpio_pin_t pin" "char *name"
|
||||
.Ft int
|
||||
.Fn gpio_pin_set_flags "gpio_handle_t handle" "gpio_config_t *cfg"
|
||||
.Ft gpio_value_t
|
||||
.Fn gpio_pin_get "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_get "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_set "gpio_handle_t handle, gpio_pin_t pin, gpio_value_t value"
|
||||
.Fn gpio_pin_set "gpio_handle_t handle" "gpio_pin_t pin" "gpio_value_t value"
|
||||
.Ft int
|
||||
.Fn gpio_pin_toggle "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_toggle "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_low "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_low "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_high "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_high "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_input "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_input "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_output "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_output "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_opendrain "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_opendrain "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_pushpull "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_pushpull "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_tristate "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_tristate "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_pullup "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_pullup "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_pulldown "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_pulldown "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_invin "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_invin "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_invout "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_invout "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Ft int
|
||||
.Fn gpio_pin_pulsate "gpio_handle_t handle, gpio_pin_t pin"
|
||||
.Fn gpio_pin_pulsate "gpio_handle_t handle" "gpio_pin_t pin"
|
||||
.Sh DESCRIPTION
|
||||
The
|
||||
.Nm libgpio
|
||||
@ -99,7 +101,7 @@ This function takes a pointer to a
|
||||
which is dynamically allocated.
|
||||
This pointer should be freed with
|
||||
.Xr free 3
|
||||
when it's no longer necessary.
|
||||
when it is no longer necessary.
|
||||
.Pp
|
||||
The function
|
||||
.Fn gpio_pin_config
|
||||
@ -111,6 +113,10 @@ variable which is part of the
|
||||
structure.
|
||||
.Pp
|
||||
The function
|
||||
.Fn gpio_pin_set_name
|
||||
sets the name used to describe a pin.
|
||||
.Pp
|
||||
The function
|
||||
.Fn gpio_pin_set_flags
|
||||
configures a pin with the flags passed in by the
|
||||
.Ft gpio_config_t
|
||||
|
||||
@ -118,6 +118,22 @@ gpio_pin_config(gpio_handle_t handle, gpio_config_t *cfg)
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
gpio_pin_set_name(gpio_handle_t handle, gpio_pin_t pin, char *name)
|
||||
{
|
||||
struct gpio_pin gppin;
|
||||
|
||||
if (name == NULL)
|
||||
return (-1);
|
||||
bzero(&gppin, sizeof(gppin));
|
||||
gppin.gp_pin = pin;
|
||||
strlcpy(gppin.gp_name, name, GPIOMAXNAME);
|
||||
if (ioctl(handle, GPIOSETNAME, &gppin) < 0)
|
||||
return (-1);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
gpio_pin_set_flags(gpio_handle_t handle, gpio_config_t *cfg)
|
||||
{
|
||||
|
||||
@ -70,6 +70,11 @@ int gpio_pin_list(gpio_handle_t, gpio_config_t **);
|
||||
* passed through the gpio_config_t structure.
|
||||
*/
|
||||
int gpio_pin_config(gpio_handle_t, gpio_config_t *);
|
||||
/*
|
||||
* Sets the GPIO pin name. The pin number and pin name to be set are passed
|
||||
* as parameters.
|
||||
*/
|
||||
int gpio_pin_set_name(gpio_handle_t, gpio_pin_t, char *);
|
||||
/*
|
||||
* Sets the GPIO flags on a specific GPIO pin. The pin number and the flags
|
||||
* to be set are passed through the gpio_config_t structure.
|
||||
|
||||
@ -450,7 +450,7 @@ ATF_TEST_CASE_BODY(dnvlist_take_nvlist__empty)
|
||||
nvl = nvlist_create(0);
|
||||
|
||||
actual_val = dnvlist_take_nvlist(nvl, "123", NULL);
|
||||
ATF_REQUIRE_EQ(actual_val, NULL);
|
||||
ATF_REQUIRE_EQ(actual_val, static_cast<nvlist_t *>(NULL));
|
||||
|
||||
free(actual_val);
|
||||
nvlist_destroy(nvl);
|
||||
|
||||
@ -54,7 +54,7 @@ ATF_TEST_CASE_BODY(nvlist_create__is_empty)
|
||||
ATF_REQUIRE(nvlist_empty(nvl));
|
||||
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(nvl);
|
||||
}
|
||||
@ -85,7 +85,7 @@ ATF_TEST_CASE_BODY(nvlist_add_null__single_insert)
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(nvl);
|
||||
}
|
||||
@ -118,7 +118,7 @@ ATF_TEST_CASE_BODY(nvlist_add_bool__single_insert)
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_BOOL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(nvl);
|
||||
}
|
||||
@ -153,7 +153,7 @@ ATF_TEST_CASE_BODY(nvlist_add_number__single_insert)
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_NUMBER);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(nvl);
|
||||
}
|
||||
@ -191,7 +191,7 @@ ATF_TEST_CASE_BODY(nvlist_add_string__single_insert)
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_STRING);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(nvl);
|
||||
}
|
||||
@ -237,7 +237,7 @@ ATF_TEST_CASE_BODY(nvlist_add_nvlist__single_insert)
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_NVLIST);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(sublist);
|
||||
nvlist_destroy(nvl);
|
||||
@ -303,7 +303,7 @@ ATF_TEST_CASE_BODY(nvlist_add_binary__single_insert)
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it), key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_BINARY);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type,&it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(nvl);
|
||||
free(value);
|
||||
@ -352,7 +352,7 @@ ATF_TEST_CASE_BODY(nvlist_clone__nonempty_nvlist)
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(clone, &type, &it), key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_NUMBER);
|
||||
ATF_REQUIRE_EQ(nvlist_next(clone, &type, &it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(clone, &type, &it), static_cast<const char *>(NULL));
|
||||
|
||||
nvlist_destroy(clone);
|
||||
nvlist_destroy(nvl);
|
||||
@ -400,13 +400,13 @@ verify_test_nvlist(const nvlist_t *nvl)
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(value, &type, &it),
|
||||
test_string_key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_STRING);
|
||||
ATF_REQUIRE_EQ(nvlist_next(value, &type, &it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(value, &type, &it), static_cast<const char *>(NULL));
|
||||
|
||||
it = NULL;
|
||||
ATF_REQUIRE_EQ(strcmp(nvlist_next(nvl, &type, &it),
|
||||
test_subnvlist_key), 0);
|
||||
ATF_REQUIRE_EQ(type, NV_TYPE_NVLIST);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), NULL);
|
||||
ATF_REQUIRE_EQ(nvlist_next(nvl, &type, &it), static_cast<const char *>(NULL));
|
||||
}
|
||||
|
||||
ATF_TEST_CASE_WITHOUT_HEAD(nvlist_clone__nested_nvlist);
|
||||
|
||||
@ -325,7 +325,7 @@ PMC_CLASS_TABLE_DESC(core2, IAP, core2, iap);
|
||||
PMC_CLASS_TABLE_DESC(corei7, IAP, corei7, iap);
|
||||
PMC_CLASS_TABLE_DESC(nehalem_ex, IAP, nehalem_ex, iap);
|
||||
PMC_CLASS_TABLE_DESC(haswell, IAP, haswell, iap);
|
||||
PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell, iap);
|
||||
PMC_CLASS_TABLE_DESC(haswell_xeon, IAP, haswell_xeon, iap);
|
||||
PMC_CLASS_TABLE_DESC(ivybridge, IAP, ivybridge, iap);
|
||||
PMC_CLASS_TABLE_DESC(ivybridge_xeon, IAP, ivybridge_xeon, iap);
|
||||
PMC_CLASS_TABLE_DESC(sandybridge, IAP, sandybridge, iap);
|
||||
|
||||
@ -527,6 +527,7 @@ API is
|
||||
.Xr pmc.core2 3 ,
|
||||
.Xr pmc.haswell 3 ,
|
||||
.Xr pmc.haswelluc 3 ,
|
||||
.Xr pmc.haswellxeon 3 ,
|
||||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.ivybridge 3 ,
|
||||
.Xr pmc.ivybridgexeon 3 ,
|
||||
|
||||
@ -529,73 +529,60 @@ instruction.
|
||||
.It Li ILD_STALL.IQ_FULL
|
||||
.Pq Event 87H , Umask 04H
|
||||
Stall cycles due to IQ is full.
|
||||
.It Li BR_INST_EXEC.COND
|
||||
.Pq Event 88H , Umask 01H
|
||||
Qualify conditional near branch instructions
|
||||
executed, but not necessarily retired.
|
||||
.It Li BR_INST_EXEC.NONTAKEN_COND
|
||||
.Pq Event 88H , Umask 41H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and not taken.
|
||||
.It Li BR_INST_EXEC.TAKEN_COND
|
||||
.Pq Event 88H , Umask 81H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and taken.
|
||||
.It Li BR_INST_EXEC.DIRECT_JMP
|
||||
.Pq Event 88H , Umask 02H
|
||||
Qualify all unconditional near branch instructions
|
||||
excluding calls and indirect branches.
|
||||
.Pq Event 88H , Umask 82H
|
||||
Count all unconditional near branch instructions excluding calls and
|
||||
indirect branches.
|
||||
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 88H , Umask 04H
|
||||
Qualify executed indirect near branch instructions
|
||||
that are not calls nor returns.
|
||||
.Pq Event 88H , Umask 84H
|
||||
Count executed indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
.It Li BR_INST_EXEC.RETURN_NEAR
|
||||
.Pq Event 88H , Umask 08H
|
||||
Qualify indirect near branches that have a return
|
||||
mnemonic.
|
||||
.Pq Event 88H , Umask 88H
|
||||
Count indirect near branches that have a return mnemonic.
|
||||
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 10H
|
||||
Qualify unconditional near call branch instructions,
|
||||
excluding non call branch, executed.
|
||||
.Pq Event 88H , Umask 90H
|
||||
Count unconditional near call branch instructions, excluding non call
|
||||
branch, executed.
|
||||
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 20H
|
||||
Qualify indirect near calls, including both register and
|
||||
memory indirect, executed.
|
||||
.It Li BR_INST_EXEC.NONTAKEN
|
||||
.Pq Event 88H , Umask 40H
|
||||
Qualify non-taken near branches executed.
|
||||
.It Li BR_INST_EXEC.TAKEN
|
||||
.Pq Event 88H , Umask 80H
|
||||
Qualify taken near branches executed. Must combine
|
||||
with 01H,02H, 04H, 08H, 10H, 20H.
|
||||
.Pq Event 88H , Umask A0H
|
||||
Count indirect near calls, including both register and memory indirect,
|
||||
executed.
|
||||
.It Li BR_INST_EXEC.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask FFH
|
||||
Counts all near executed branches (not necessarily
|
||||
retired).
|
||||
.It Li BR_MISP_EXEC.COND
|
||||
.Pq Event 89H , Umask 01H
|
||||
Qualify conditional near branch instructions
|
||||
mispredicted.
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li BR_MISP_EXEC.NONTAKEN_COND
|
||||
.Pq Event 89H , Umask 41H
|
||||
Count conditional near branch instructions mispredicted as nontaken.
|
||||
.It Li BR_MISP_EXEC.TAKEN_COND
|
||||
.Pq Event 89H , Umask 81H
|
||||
Count conditional near branch instructions mispredicted as taken.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 89H , Umask 04H
|
||||
Qualify mispredicted indirect near branch
|
||||
instructions that are not calls nor returns.
|
||||
.Pq Event 89H , Umask 84H
|
||||
Count mispredicted indirect near branch instructions that are not calls
|
||||
nor returns.
|
||||
.It Li BR_MISP_EXEC.RETURN_NEAR
|
||||
.Pq Event 89H , Umask 08H
|
||||
Qualify mispredicted indirect near branches that
|
||||
have a return mnemonic.
|
||||
.Pq Event 89H , Umask 88H
|
||||
Count mispredicted indirect near branches that have a return mnemonic.
|
||||
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 10H
|
||||
Qualify mispredicted unconditional near call branch
|
||||
instructions, excluding non call branch, executed.
|
||||
.Pq Event 89H , Umask 90H
|
||||
Count mispredicted unconditional near call branch instructions, excluding
|
||||
non call branch, executed.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 20H
|
||||
Qualify mispredicted indirect near calls, including
|
||||
both register and memory indirect, executed.
|
||||
.It Li BR_MISP_EXEC.NONTAKEN
|
||||
.Pq Event 89H , Umask 40H
|
||||
Qualify mispredicted non-taken near branches
|
||||
executed.
|
||||
.It Li BR_MISP_EXEC.TAKEN
|
||||
.Pq Event 89H , Umask 80H
|
||||
Qualify mispredicted taken near branches executed.
|
||||
Must combine with 01H,02H, 04H, 08H, 10H, 20H.
|
||||
.Pq Event 89H , Umask A0H
|
||||
Count mispredicted indirect near calls, including both register and memory
|
||||
indirect, executed.
|
||||
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
||||
.Pq Event 89H , Umask FFH
|
||||
Counts all near executed branches (not necessarily
|
||||
retired).
|
||||
Counts all mispredicted near executed branches (not necessarily retired).
|
||||
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
||||
.Pq Event 9CH , Umask 01H
|
||||
Count number of non-delivered uops to RAT per
|
||||
@ -821,30 +808,24 @@ Count cases of saving new LBR records by hardware.
|
||||
Randomly sampled loads whose latency is above a
|
||||
user defined threshold. A small fraction of the overall
|
||||
loads are sampled due to randomization.
|
||||
.It Li MEM_UOP_RETIRED.LOADS
|
||||
.Pq Event D0H , Umask 01H
|
||||
Qualify retired memory uops that are loads. Combine Supports PEBS and
|
||||
with umask 10H, 20H, 40H, 80H.
|
||||
.It Li MEM_UOP_RETIRED.STORES
|
||||
.Pq Event D0H , Umask 02H
|
||||
Qualify retired memory uops that are stores.
|
||||
Combine with umask 10H, 20H, 40H, 80H.
|
||||
.It Li MEM_UOP_RETIRED.STLB_MISS
|
||||
.Pq Event D0H , Umask 10H
|
||||
Qualify retired memory uops with STLB miss. Must
|
||||
combine with umask 01H, 02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.LOCK
|
||||
.Pq Event D0H , Umask 20H
|
||||
Qualify retired memory uops with lock. Must combine Supports PEBS and
|
||||
with umask 01H, 02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.SPLIT
|
||||
.Pq Event D0H , Umask 40H
|
||||
Qualify retired memory uops with line split. Must
|
||||
combine with umask 01H, 02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.ALL
|
||||
.Pq Event D0H , Umask 80H
|
||||
Qualify any retired memory uops. Must combine with Supports PEBS and
|
||||
umask 01H, 02H, to produce counts.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
|
||||
.Pq Event D0H , Umask 11H
|
||||
Count retired load uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
|
||||
.Pq Event D0H , Umask 12H
|
||||
Count retired store uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
|
||||
.Pq Event D0H , Umask 41H
|
||||
Count retired load uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_STORES
|
||||
.Pq Event D0H , Umask 42H
|
||||
Count retired store uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_LOADS
|
||||
.Pq Event D0H , Umask 81H
|
||||
Count all retired load uops.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_STORES
|
||||
.Pq Event D0H , Umask 82H
|
||||
Count all retired store uops.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.Pq Event D1H , Umask 01H
|
||||
Retired load uops with L1 cache hits as data sources.
|
||||
|
||||
956
lib/libpmc/pmc.haswellxeon.3
Normal file
956
lib/libpmc/pmc.haswellxeon.3
Normal file
@ -0,0 +1,956 @@
|
||||
.\"
|
||||
.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
|
||||
.\" All rights reserved.
|
||||
.\"
|
||||
.\" Redistribution and use in source and binary forms, with or without
|
||||
.\" modification, are permitted provided that the following conditions
|
||||
.\" are met:
|
||||
.\" 1. Redistributions of source code must retain the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer.
|
||||
.\" 2. Redistributions in binary form must reproduce the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer in the
|
||||
.\" documentation and/or other materials provided with the distribution.
|
||||
.\"
|
||||
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
.\" SUCH DAMAGE.
|
||||
.\"
|
||||
.\" $FreeBSD$
|
||||
.\"
|
||||
.Dd 21 November, 2014
|
||||
.Dt PMC.HASWELLXEON 3
|
||||
.Os
|
||||
.Sh NAME
|
||||
.Nm pmc.haswellxeon
|
||||
.Nd measurement events for
|
||||
.Tn Intel
|
||||
.Tn Haswell Xeon
|
||||
family CPUs
|
||||
.Sh LIBRARY
|
||||
.Lb libpmc
|
||||
.Sh SYNOPSIS
|
||||
.In pmc.h
|
||||
.Sh DESCRIPTION
|
||||
.Tn Intel
|
||||
.Tn "Haswell"
|
||||
CPUs contain PMCs conforming to version 2 of the
|
||||
.Tn Intel
|
||||
performance measurement architecture.
|
||||
These CPUs may contain up to two classes of PMCs:
|
||||
.Bl -tag -width "Li PMC_CLASS_IAP"
|
||||
.It Li PMC_CLASS_IAF
|
||||
Fixed-function counters that count only one hardware event per counter.
|
||||
.It Li PMC_CLASS_IAP
|
||||
Programmable counters that may be configured to count one of a defined
|
||||
set of hardware events.
|
||||
.El
|
||||
.Pp
|
||||
The number of PMCs available in each class and their widths need to be
|
||||
determined at run time by calling
|
||||
.Xr pmc_cpuinfo 3 .
|
||||
.Pp
|
||||
Intel Haswell Xeon PMCs are documented in
|
||||
.Rs
|
||||
.%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual"
|
||||
.%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C"
|
||||
.%N "Order Number: 325462-052US"
|
||||
.%D September 2014
|
||||
.%Q "Intel Corporation"
|
||||
.Re
|
||||
.Ss HASWELL FIXED FUNCTION PMCS
|
||||
These PMCs and their supported events are documented in
|
||||
.Xr pmc.iaf 3 .
|
||||
.Ss HASWELL PROGRAMMABLE PMCS
|
||||
The programmable PMCs support the following capabilities:
|
||||
.Bl -column "PMC_CAP_INTERRUPT" "Support"
|
||||
.It Em Capability Ta Em Support
|
||||
.It PMC_CAP_CASCADE Ta \&No
|
||||
.It PMC_CAP_EDGE Ta Yes
|
||||
.It PMC_CAP_INTERRUPT Ta Yes
|
||||
.It PMC_CAP_INVERT Ta Yes
|
||||
.It PMC_CAP_READ Ta Yes
|
||||
.It PMC_CAP_PRECISE Ta \&No
|
||||
.It PMC_CAP_SYSTEM Ta Yes
|
||||
.It PMC_CAP_TAGGING Ta \&No
|
||||
.It PMC_CAP_THRESHOLD Ta Yes
|
||||
.It PMC_CAP_USER Ta Yes
|
||||
.It PMC_CAP_WRITE Ta Yes
|
||||
.El
|
||||
.Ss Event Qualifiers
|
||||
Event specifiers for these PMCs support the following common
|
||||
qualifiers:
|
||||
.Bl -tag -width indent
|
||||
.It Li rsp= Ns Ar value
|
||||
Configure the Off-core Response bits.
|
||||
.Bl -tag -width indent
|
||||
.It Li DMND_DATA_RD
|
||||
Counts the number of demand and DCU prefetch data reads of full
|
||||
and partial cachelines as well as demand data page table entry
|
||||
cacheline reads. Does not count L2 data read prefetches or
|
||||
instruction fetches.
|
||||
.It Li REQ_DMND_RFO
|
||||
Counts the number of demand and DCU prefetch reads for ownership (RFO)
|
||||
requests generated by a write to data cacheline. Does not count L2 RFO
|
||||
prefetches.
|
||||
.It Li REQ_DMND_IFETCH
|
||||
Counts the number of demand and DCU prefetch instruction cacheline reads.
|
||||
Does not count L2 code read prefetches.
|
||||
.It Li REQ_WB
|
||||
Counts the number of writeback (modified to exclusive) transactions.
|
||||
.It Li REQ_PF_DATA_RD
|
||||
Counts the number of data cacheline reads generated by L2 prefetchers.
|
||||
.It Li REQ_PF_RFO
|
||||
Counts the number of RFO requests generated by L2 prefetchers.
|
||||
.It Li REQ_PF_IFETCH
|
||||
Counts the number of code reads generated by L2 prefetchers.
|
||||
.It Li REQ_PF_LLC_DATA_RD
|
||||
L2 prefetcher to L3 for loads.
|
||||
.It Li REQ_PF_LLC_RFO
|
||||
RFO requests generated by L2 prefetcher
|
||||
.It Li REQ_PF_LLC_IFETCH
|
||||
L2 prefetcher to L3 for instruction fetches.
|
||||
.It Li REQ_BUS_LOCKS
|
||||
Bus lock and split lock requests.
|
||||
.It Li REQ_STRM_ST
|
||||
Streaming store requests.
|
||||
.It Li REQ_OTHER
|
||||
Any other request that crosses IDI, including I/O.
|
||||
.It Li RES_ANY
|
||||
Catch all value for any response types.
|
||||
.It Li RES_SUPPLIER_NO_SUPP
|
||||
No Supplier Information available.
|
||||
.It Li RES_SUPPLIER_LLC_HITM
|
||||
M-state initial lookup stat in L3.
|
||||
.It Li RES_SUPPLIER_LLC_HITE
|
||||
E-state.
|
||||
.It Li RES_SUPPLIER_LLC_HITS
|
||||
S-state.
|
||||
.It Li RES_SUPPLIER_LLC_HITF
|
||||
F-state.
|
||||
.It Li RES_SUPPLIER_LOCAL
|
||||
Local DRAM Controller.
|
||||
.It Li RES_SNOOP_SNP_NONE
|
||||
No details on snoop-related information.
|
||||
.It Li RES_SNOOP_SNP_NO_NEEDED
|
||||
No snoop was needed to satisfy the request.
|
||||
.It Li RES_SNOOP_SNP_MISS
|
||||
A snoop was needed and it missed all snooped caches:
|
||||
-For LLC Hit, ReslHitl was returned by all cores
|
||||
-For LLC Miss, Rspl was returned by all sockets and data was returned from
|
||||
DRAM.
|
||||
.It Li RES_SNOOP_HIT_NO_FWD
|
||||
A snoop was needed and it hits in at least one snooped cache. Hit denotes a
|
||||
cache-line was valid before snoop effect. This includes:
|
||||
-Snoop Hit w/ Invalidation (LLC Hit, RFO)
|
||||
-Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD)
|
||||
-Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S)
|
||||
In the LLC Miss case, data is returned from DRAM.
|
||||
.It Li RES_SNOOP_HIT_FWD
|
||||
A snoop was needed and data was forwarded from a remote socket.
|
||||
This includes:
|
||||
-Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).
|
||||
.It Li RES_SNOOP_HITM
|
||||
A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a
|
||||
cache-line was in modified state before effect as a results of snoop. This
|
||||
includes:
|
||||
-Snoop HitM w/ WB (LLC miss, IFetch/Data_RD)
|
||||
-Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO)
|
||||
-Snoop MtoS (LLC Hit, IFetch/Data_RD).
|
||||
.It Li RES_NON_DRAM
|
||||
Target was non-DRAM system address. This includes MMIO transactions.
|
||||
.El
|
||||
.It Li cmask= Ns Ar value
|
||||
Configure the PMC to increment only if the number of configured
|
||||
events measured in a cycle is greater than or equal to
|
||||
.Ar value .
|
||||
.It Li edge
|
||||
Configure the PMC to count the number of de-asserted to asserted
|
||||
transitions of the conditions expressed by the other qualifiers.
|
||||
If specified, the counter will increment only once whenever a
|
||||
condition becomes true, irrespective of the number of clocks during
|
||||
which the condition remains true.
|
||||
.It Li inv
|
||||
Invert the sense of comparison when the
|
||||
.Dq Li cmask
|
||||
qualifier is present, making the counter increment when the number of
|
||||
events per cycle is less than the value specified by the
|
||||
.Dq Li cmask
|
||||
qualifier.
|
||||
.It Li os
|
||||
Configure the PMC to count events happening at processor privilege
|
||||
level 0.
|
||||
.It Li usr
|
||||
Configure the PMC to count events occurring at privilege levels 1, 2
|
||||
or 3.
|
||||
.El
|
||||
.Pp
|
||||
If neither of the
|
||||
.Dq Li os
|
||||
or
|
||||
.Dq Li usr
|
||||
qualifiers are specified, the default is to enable both.
|
||||
.Ss Event Specifiers (Programmable PMCs)
|
||||
Haswell programmable PMCs support the following events:
|
||||
.Bl -tag -width indent
|
||||
.It Li LD_BLOCKS.STORE_FORWARD
|
||||
.Pq Event 03H , Umask 02H
|
||||
Loads blocked by overlapping with store buffer that
|
||||
cannot be forwarded.
|
||||
.It Li MISALIGN_MEM_REF.LOADS
|
||||
.Pq Event 05H , Umask 01H
|
||||
Speculative cache-line split load uops dispatched to
|
||||
L1D.
|
||||
.It Li MISALIGN_MEM_REF.STORES
|
||||
.Pq Event 05H , Umask 02H
|
||||
Speculative cache-line split Store-address uops
|
||||
dispatched to L1D.
|
||||
.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
|
||||
.Pq Event 07H , Umask 01H
|
||||
False dependencies in MOB due to partial compare
|
||||
on address.
|
||||
.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
|
||||
.Pq Event 08H , Umask 01H
|
||||
Misses in all TLB levels that cause a page walk of any
|
||||
page size.
|
||||
.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K
|
||||
.Pq Event 08H , Umask 02H
|
||||
Completed page walks due to demand load misses
|
||||
that caused 4K page walks in any TLB levels.
|
||||
.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K
|
||||
.Pq Event 08H , Umask 02H
|
||||
Completed page walks due to demand load misses
|
||||
that caused 2M/4M page walks in any TLB levels.
|
||||
.It Li DTLB_LOAD_MISSES.WALK_COMPLETED
|
||||
.Pq Event 08H , Umask 0EH
|
||||
Completed page walks in any TLB of any page size
|
||||
due to demand load misses
|
||||
.It Li DTLB_LOAD_MISSES.WALK_DURATION
|
||||
.Pq Event 08H , Umask 10H
|
||||
Cycle PMH is busy with a walk.
|
||||
.It Li DTLB_LOAD_MISSES.STLB_HIT_4K
|
||||
.Pq Event 08H , Umask 20H
|
||||
Load misses that missed DTLB but hit STLB (4K).
|
||||
.It Li DTLB_LOAD_MISSES.STLB_HIT_2M
|
||||
.Pq Event 08H , Umask 40H
|
||||
Load misses that missed DTLB but hit STLB (2M).
|
||||
.It Li DTLB_LOAD_MISSES.STLB_HIT
|
||||
.Pq Event 08H , Umask 60H
|
||||
Number of cache load STLB hits. No page walk.
|
||||
.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS
|
||||
.Pq Event 08H , Umask 80H
|
||||
DTLB demand load misses with low part of linear-to-
|
||||
physical address translation missed
|
||||
.It Li INT_MISC.RECOVERY_CYCLES
|
||||
.Pq Event 0DH , Umask 03H
|
||||
Cycles waiting to recover after Machine Clears
|
||||
except JEClear. Set Cmask= 1.
|
||||
.It Li UOPS_ISSUED.ANY
|
||||
.Pq Event 0EH , Umask 01H
|
||||
ncrements each cycle the # of Uops issued by the
|
||||
RAT to RS.
|
||||
Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
|
||||
of this core.
|
||||
.It Li UOPS_ISSUED.FLAGS_MERGE
|
||||
.Pq Event 0EH , Umask 10H
|
||||
Number of flags-merge uops allocated. Such uops
|
||||
adds delay.
|
||||
.It Li UOPS_ISSUED.SLOW_LEA
|
||||
.Pq Event 0EH , Umask 20H
|
||||
Number of slow LEA or similar uops allocated. Such
|
||||
uop has 3 sources (e.g. 2 sources + immediate)
|
||||
regardless if as a result of LEA instruction or not.
|
||||
.It Li UOPS_ISSUED.SiNGLE_MUL
|
||||
.Pq Event 0EH , Umask 40H
|
||||
Number of multiply packed/scalar single precision
|
||||
uops allocated.
|
||||
.It Li L2_RQSTS.DEMAND_DATA_RD_MISS
|
||||
.Pq Event 24H , Umask 21H
|
||||
Demand Data Read requests that missed L2, no
|
||||
rejects.
|
||||
.It Li L2_RQSTS.DEMAND_DATA_RD_HIT
|
||||
.Pq Event 24H , Umask 41H
|
||||
Demand Data Read requests that hit L2 cache.
|
||||
.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
|
||||
.Pq Event 24H , Umask E1H
|
||||
Counts any demand and L1 HW prefetch data load
|
||||
requests to L2.
|
||||
.It Li L2_RQSTS.RFO_HIT
|
||||
.Pq Event 24H , Umask 42H
|
||||
Counts the number of store RFO requests that hit
|
||||
the L2 cache.
|
||||
.It Li L2_RQSTS.RFO_MISS
|
||||
.Pq Event 24H , Umask 22H
|
||||
Counts the number of store RFO requests that miss
|
||||
the L2 cache.
|
||||
.It Li L2_RQSTS.ALL_RFO
|
||||
.Pq Event 24H , Umask E2H
|
||||
Counts all L2 store RFO requests.
|
||||
.It Li L2_RQSTS.CODE_RD_HIT
|
||||
.Pq Event 24H , Umask 44H
|
||||
Number of instruction fetches that hit the L2 cache.
|
||||
.It Li L2_RQSTS.CODE_RD_MISS
|
||||
.Pq Event 24H , Umask 24H
|
||||
Number of instruction fetches that missed the L2
|
||||
cache.
|
||||
.It Li L2_RQSTS.ALL_DEMAND_MISS
|
||||
.Pq Event 24H , Umask 27H
|
||||
Demand requests that miss L2 cache.
|
||||
.It Li L2_RQSTS.ALL_DEMAND_REFERENCES
|
||||
.Pq Event 24H , Umask E7H
|
||||
Demand requests to L2 cache.
|
||||
.It Li L2_RQSTS.ALL_CODE_RD
|
||||
.Pq Event 24H , Umask E4H
|
||||
Counts all L2 code requests.
|
||||
.It Li L2_RQSTS.L2_PF_HIT
|
||||
.Pq Event 24H , Umask 50H
|
||||
Counts all L2 HW prefetcher requests that hit L2.
|
||||
.It Li L2_RQSTS.L2_PF_MISS
|
||||
.Pq Event 24H , Umask 30H
|
||||
Counts all L2 HW prefetcher requests that missed
|
||||
L2.
|
||||
.It Li L2_RQSTS.ALL_PF
|
||||
.Pq Event 24H , Umask F8H
|
||||
Counts all L2 HW prefetcher requests.
|
||||
.It Li L2_RQSTS.MISS
|
||||
.Pq Event 24H , Umask 3FH
|
||||
All requests that missed L2.
|
||||
.It Li L2_RQSTS.REFERENCES
|
||||
.Pq Event 24H , Umask FFH
|
||||
All requests to L2 cache.
|
||||
.It Li L2_DEMAND_RQSTS.WB_HIT
|
||||
.Pq Event 27H , Umask 50H
|
||||
Not rejected writebacks that hit L2 cache
|
||||
.It Li LONGEST_LAT_CACHE.REFERENCE
|
||||
.Pq Event 2EH , Umask 4FH
|
||||
This event counts requests originating from the core
|
||||
that reference a cache line in the last level cache.
|
||||
.It Li LONGEST_LAT_CACHE.MISS
|
||||
.Pq Event 2EH , Umask 41H
|
||||
This event counts each cache miss condition for
|
||||
references to the last level cache.
|
||||
.It Li CPU_CLK_UNHALTED.THREAD_P
|
||||
.Pq Event 3CH , Umask 00H
|
||||
Counts the number of thread cycles while the thread
|
||||
is not in a halt state. The thread enters the halt state
|
||||
when it is running the HLT instruction. The core
|
||||
frequency may change from time to time due to
|
||||
power or thermal throttling.
|
||||
.It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK
|
||||
.Pq Event 3CH , Umask 01H
|
||||
Increments at the frequency of XCLK (100 MHz)
|
||||
when not halted.
|
||||
.It Li L1D_PEND_MISS.PENDING
|
||||
.Pq Event 48H , Umask 01H
|
||||
Increments the number of outstanding L1D misses
|
||||
every cycle. Set Cmaks = 1 and Edge =1 to count
|
||||
occurrences.
|
||||
.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
|
||||
.Pq Event 49H , Umask 01H
|
||||
Miss in all TLB levels causes an page walk of any
|
||||
page size (4K/2M/4M/1G).
|
||||
.It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K
|
||||
.Pq Event 49H , Umask 02H
|
||||
Completed page walks due to store misses in one or
|
||||
more TLB levels of 4K page structure.
|
||||
.It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M
|
||||
.Pq Event 49H , Umask 04H
|
||||
Completed page walks due to store misses in one or
|
||||
more TLB levels of 2M/4M page structure.
|
||||
.It Li DTLB_STORE_MISSES.WALK_COMPLETED
|
||||
.Pq Event 49H , Umask 0EH
|
||||
Completed page walks due to store miss in any TLB
|
||||
levels of any page size (4K/2M/4M/1G).
|
||||
.It Li DTLB_STORE_MISSES.WALK_DURATION
|
||||
.Pq Event 49H , Umask 10H
|
||||
Cycles PMH is busy with this walk.
|
||||
.It Li DTLB_STORE_MISSES.STLB_HIT_4K
|
||||
.Pq Event 49H , Umask 20H
|
||||
Store misses that missed DTLB but hit STLB (4K).
|
||||
.It Li DTLB_STORE_MISSES.STLB_HIT_2M
|
||||
.Pq Event 49H , Umask 40H
|
||||
Store misses that missed DTLB but hit STLB (2M).
|
||||
.It Li DTLB_STORE_MISSES.STLB_HIT
|
||||
.Pq Event 49H , Umask 60H
|
||||
Store operations that miss the first TLB level but hit
|
||||
the second and do not cause page walks.
|
||||
.It Li DTLB_STORE_MISSES.PDE_CACHE_MISS
|
||||
.Pq Event 49H , Umask 80H
|
||||
DTLB store misses with low part of linear-to-physical
|
||||
address translation missed.
|
||||
.It Li LOAD_HIT_PRE.SW_PF
|
||||
.Pq Event 4CH , Umask 01H
|
||||
Non-SW-prefetch load dispatches that hit fill buffer
|
||||
allocated for S/W prefetch.
|
||||
.It Li LOAD_HIT_PRE.HW_PF
|
||||
.Pq Event 4CH , Umask 02H
|
||||
Non-SW-prefetch load dispatches that hit fill buffer
|
||||
allocated for H/W prefetch.
|
||||
.It Li L1D.REPLACEMENT
|
||||
.Pq Event 51H , Umask 01H
|
||||
Counts the number of lines brought into the L1 data
|
||||
cache.
|
||||
.It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED
|
||||
.Pq Event 58H , Umask 04H
|
||||
Number of integer Move Elimination candidate uops
|
||||
that were not eliminated.
|
||||
.It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED
|
||||
.Pq Event 58H , Umask 08H
|
||||
Number of SIMD Move Elimination candidate uops
|
||||
that were not eliminated.
|
||||
.It Li MOVE_ELIMINATION.INT_ELIMINATED
|
||||
.Pq Event 58H , Umask 01H
|
||||
Unhalted core cycles when the thread is in ring 0.
|
||||
.It Li MOVE_ELIMINATION.SMID_ELIMINATED
|
||||
.Pq Event 58H , Umask 02H
|
||||
Number of SIMD Move Elimination candidate uops
|
||||
that were eliminated.
|
||||
.It Li CPL_CYCLES.RING0
|
||||
.Pq Event 5CH , Umask 02H
|
||||
Unhalted core cycles when the thread is in ring 0.
|
||||
.It Li CPL_CYCLES.RING123
|
||||
.Pq Event 5CH , Umask 01H
|
||||
Unhalted core cycles when the thread is not in ring 0.
|
||||
.It Li RS_EVENTS.EMPTY_CYCLES
|
||||
.Pq Event 5EH , Umask 01H
|
||||
Cycles the RS is empty for the thread.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
|
||||
.Pq Event 60H , Umask 01H
|
||||
Offcore outstanding Demand Data Read transactions
|
||||
in SQ to uncore. Set Cmask=1 to count cycles.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD
|
||||
.Pq Event 60H , Umask 02H
|
||||
Offcore outstanding Demand code Read transactions
|
||||
in SQ to uncore. Set Cmask=1 to count cycles.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
|
||||
.Pq Event 60H , Umask 04H
|
||||
Offcore outstanding RFO store transactions in SQ to
|
||||
uncore. Set Cmask=1 to count cycles.
|
||||
.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
|
||||
.Pq Event 60H , Umask 08H
|
||||
Offcore outstanding cacheable data read
|
||||
transactions in SQ to uncore. Set Cmask=1 to count
|
||||
cycles.
|
||||
.It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION
|
||||
.Pq Event 63H , Umask 01H
|
||||
Cycles in which the L1D and L2 are locked, due to a
|
||||
UC lock or split lock.
|
||||
.It Li LOCK_CYCLES.CACHE_LOCK_DURATION
|
||||
.Pq Event 63H , Umask 02H
|
||||
Cycles in which the L1D is locked.
|
||||
.It Li IDQ.EMPTY
|
||||
.Pq Event 79H , Umask 02H
|
||||
Counts cycles the IDQ is empty.
|
||||
.It Li IDQ.MITE_UOPS
|
||||
.Pq Event 79H , Umask 04H
|
||||
Increment each cycle # of uops delivered to IDQ from
|
||||
MITE path.
|
||||
Set Cmask = 1 to count cycles.
|
||||
.It Li IDQ.DSB_UOPS
|
||||
.Pq Event 79H , Umask 08H
|
||||
Increment each cycle. # of uops delivered to IDQ
|
||||
from DSB path.
|
||||
Set Cmask = 1 to count cycles.
|
||||
.It Li IDQ.MS_DSB_UOPS
|
||||
.Pq Event 79H , Umask 10H
|
||||
Increment each cycle # of uops delivered to IDQ
|
||||
when MS_busy by DSB. Set Cmask = 1 to count
|
||||
cycles. Add Edge=1 to count # of delivery.
|
||||
.It Li IDQ.MS_MITE_UOPS
|
||||
.Pq Event 79H , Umask 20H
|
||||
ncrement each cycle # of uops delivered to IDQ
|
||||
when MS_busy by MITE. Set Cmask = 1 to count
|
||||
cycles.
|
||||
.It Li IDQ.MS_UOPS
|
||||
.Pq Event 79H , Umask 30H
|
||||
Increment each cycle # of uops delivered to IDQ from
|
||||
MS by either DSB or MITE. Set Cmask = 1 to count
|
||||
cycles.
|
||||
.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
|
||||
.Pq Event 79H , Umask 18H
|
||||
Counts cycles DSB is delivered at least one uops. Set
|
||||
Cmask = 1.
|
||||
.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
|
||||
.Pq Event 79H , Umask 18H
|
||||
Counts cycles DSB is delivered four uops. Set Cmask
|
||||
=4.
|
||||
.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
|
||||
.Pq Event 79H , Umask 24H
|
||||
Counts cycles MITE is delivered at least one uops. Set
|
||||
Cmask = 1.
|
||||
.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
|
||||
.Pq Event 79H , Umask 24H
|
||||
Counts cycles MITE is delivered four uops. Set Cmask
|
||||
=4.
|
||||
.It Li IDQ.MITE_ALL_UOPS
|
||||
.Pq Event 79H , Umask 3CH
|
||||
# of uops delivered to IDQ from any path.
|
||||
.It Li ICACHE.MISSES
|
||||
.Pq Event 80H , Umask 02H
|
||||
Number of Instruction Cache, Streaming Buffer and
|
||||
Victim Cache Misses. Includes UC accesses.
|
||||
.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
|
||||
.Pq Event 85H , Umask 01H
|
||||
Misses in ITLB that causes a page walk of any page
|
||||
size.
|
||||
.It Li ITLB_MISSES.WALK_COMPLETED_4K
|
||||
.Pq Event 85H , Umask 02H
|
||||
Completed page walks due to misses in ITLB 4K page
|
||||
entries.
|
||||
.It Li TLB_MISSES.WALK_COMPLETED_2M_4M
|
||||
.Pq Event 85H , Umask 04H
|
||||
Completed page walks due to misses in ITLB 2M/4M
|
||||
page entries.
|
||||
.It Li ITLB_MISSES.WALK_COMPLETED
|
||||
.Pq Event 85H , Umask 0EH
|
||||
Completed page walks in ITLB of any page size.
|
||||
.It Li ITLB_MISSES.WALK_DURATION
|
||||
.Pq Event 85H , Umask 10H
|
||||
Cycle PMH is busy with a walk.
|
||||
.It Li ITLB_MISSES.STLB_HIT_4K
|
||||
.Pq Event 85H , Umask 20H
|
||||
ITLB misses that hit STLB (4K).
|
||||
.It Li ITLB_MISSES.STLB_HIT_2M
|
||||
.Pq Event 85H , Umask 40H
|
||||
ITLB misses that hit STLB (2K).
|
||||
.It Li ITLB_MISSES.STLB_HIT
|
||||
.Pq Event 85H , Umask 60H
|
||||
TLB misses that hit STLB. No page walk.
|
||||
.It Li ILD_STALL.LCP
|
||||
.Pq Event 87H , Umask 01H
|
||||
Stalls caused by changing prefix length of the
|
||||
instruction.
|
||||
.It Li ILD_STALL.IQ_FULL
|
||||
.Pq Event 87H , Umask 04H
|
||||
Stall cycles due to IQ is full.
|
||||
.It Li BR_INST_EXEC.NONTAKEN_COND
|
||||
.Pq Event 88H , Umask 41H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and not taken.
|
||||
.It Li BR_INST_EXEC.TAKEN_COND
|
||||
.Pq Event 88H , Umask 81H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and taken.
|
||||
.It Li BR_INST_EXEC.DIRECT_JMP
|
||||
.Pq Event 88H , Umask 82H
|
||||
Count all unconditional near branch instructions excluding calls and
|
||||
indirect branches.
|
||||
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 88H , Umask 84H
|
||||
Count executed indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
.It Li BR_INST_EXEC.RETURN_NEAR
|
||||
.Pq Event 88H , Umask 88H
|
||||
Count indirect near branches that have a return mnemonic.
|
||||
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 90H
|
||||
Count unconditional near call branch instructions, excluding non call
|
||||
branch, executed.
|
||||
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask A0H
|
||||
Count indirect near calls, including both register and memory indirect,
|
||||
executed.
|
||||
.It Li BR_INST_EXEC.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li BR_MISP_EXEC.NONTAKEN_COND
|
||||
.Pq Event 89H , Umask 41H
|
||||
Count conditional near branch instructions mispredicted as nontaken.
|
||||
.It Li BR_MISP_EXEC.TAKEN_COND
|
||||
.Pq Event 89H , Umask 81H
|
||||
Count conditional near branch instructions mispredicted as taken.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 89H , Umask 84H
|
||||
Count mispredicted indirect near branch instructions that are not calls
|
||||
nor returns.
|
||||
.It Li BR_MISP_EXEC.RETURN_NEAR
|
||||
.Pq Event 89H , Umask 88H
|
||||
Count mispredicted indirect near branches that have a return mnemonic.
|
||||
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 90H
|
||||
Count mispredicted unconditional near call branch instructions, excluding
|
||||
non call branch, executed.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask A0H
|
||||
Count mispredicted indirect near calls, including both register and memory
|
||||
indirect, executed.
|
||||
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
||||
.Pq Event 89H , Umask FFH
|
||||
Counts all mispredicted near executed branches (not necessarily retired).
|
||||
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
||||
.Pq Event 9CH , Umask 01H
|
||||
Count number of non-delivered uops to RAT per
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_0
|
||||
.Pq Event A1H , Umask 01H
|
||||
Cycles which a Uop is dispatched on port 0 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_1
|
||||
.Pq Event A1H , Umask 02H
|
||||
Cycles which a Uop is dispatched on port 1 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_2
|
||||
.Pq Event A1H , Umask 04H
|
||||
Cycles which a Uop is dispatched on port 2 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_3
|
||||
.Pq Event A1H , Umask 08H
|
||||
Cycles which a Uop is dispatched on port 3 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_4
|
||||
.Pq Event A1H , Umask 10H
|
||||
Cycles which a Uop is dispatched on port 4 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_5
|
||||
.Pq Event A1H , Umask 20H
|
||||
Cycles which a Uop is dispatched on port 5 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_6
|
||||
.Pq Event A1H , Umask 40H
|
||||
Cycles which a Uop is dispatched on port 6 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_7
|
||||
.Pq Event A1H , Umask 80H
|
||||
Cycles which a Uop is dispatched on port 7 in this
|
||||
thread.
|
||||
.It Li RESOURCE_STALLS.ANY
|
||||
.Pq Event A2H , Umask 01H
|
||||
Cycles Allocation is stalled due to Resource Related
|
||||
reason.
|
||||
.It Li RESOURCE_STALLS.RS
|
||||
.Pq Event A2H , Umask 04H
|
||||
Cycles stalled due to no eligible RS entry available.
|
||||
.It Li RESOURCE_STALLS.SB
|
||||
.Pq Event A2H , Umask 08H
|
||||
Cycles stalled due to no store buffers available (not
|
||||
including draining form sync).
|
||||
.It Li RESOURCE_STALLS.ROB
|
||||
.Pq Event A2H , Umask 10H
|
||||
Cycles stalled due to re-order buffer full.
|
||||
.It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING
|
||||
.Pq Event A3H , Umask 01H
|
||||
Cycles with pending L2 miss loads. Set Cmask=2 to
|
||||
count cycle.
|
||||
.It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING
|
||||
.Pq Event A3H , Umask 02H
|
||||
Cycles with pending memory loads. Set Cmask=2 to
|
||||
count cycle.
|
||||
.It Li CYCLE_ACTIVITY.STALLS_L2_PENDING
|
||||
.Pq Event A3H , Umask 05H
|
||||
Number of loads missed L2.
|
||||
.It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING
|
||||
.Pq Event A3H , Umask 08H
|
||||
Cycles with pending L1 cache miss loads. Set
|
||||
Cmask=8 to count cycle.
|
||||
.It Li ITLB.ITLB_FLUSH
|
||||
.Pq Event AEH , Umask 01H
|
||||
Counts the number of ITLB flushes, includes
|
||||
4k/2M/4M pages.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND_DATA_RD
|
||||
.Pq Event B0H , Umask 01H
|
||||
Demand data read requests sent to uncore.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND_CODE_RD
|
||||
.Pq Event B0H , Umask 02H
|
||||
Demand code read requests sent to uncore.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND_RFO
|
||||
.Pq Event B0H , Umask 04H
|
||||
Demand RFO read requests sent to uncore, including
|
||||
regular RFOs, locks, ItoM.
|
||||
.It Li OFFCORE_REQUESTS.ALL_DATA_RD
|
||||
.Pq Event B0H , Umask 08H
|
||||
Data read requests sent to uncore (demand and
|
||||
prefetch).
|
||||
.It Li UOPS_EXECUTED.CORE
|
||||
.Pq Event B1H , Umask 02H
|
||||
Counts total number of uops to be executed per-core
|
||||
each cycle.
|
||||
.It Li OFF_CORE_RESPONSE_0
|
||||
.Pq Event B7H , Umask 01H
|
||||
Requires MSR 01A6H
|
||||
.It Li OFF_CORE_RESPONSE_1
|
||||
.Pq Event BBH , Umask 01H
|
||||
Requires MSR 01A7H
|
||||
.It Li PAGE_WALKER_LOADS.DTLB_L1
|
||||
.Pq Event BCH , Umask 11H
|
||||
Number of DTLB page walker loads that hit in the
|
||||
L1+FB.
|
||||
.It Li PAGE_WALKER_LOADS.ITLB_L1
|
||||
.Pq Event BCH , Umask 21H
|
||||
Number of ITLB page walker loads that hit in the
|
||||
L1+FB.
|
||||
.It Li PAGE_WALKER_LOADS.DTLB_L2
|
||||
.Pq Event BCH , Umask 12H
|
||||
Number of DTLB page walker loads that hit in the L2.
|
||||
.It Li PAGE_WALKER_LOADS.ITLB_L2
|
||||
.Pq Event BCH , Umask 22H
|
||||
Number of ITLB page walker loads that hit in the L2.
|
||||
.It Li PAGE_WALKER_LOADS.DTLB_L3
|
||||
.Pq Event BCH , Umask 14H
|
||||
Number of DTLB page walker loads that hit in the L3.
|
||||
.It Li PAGE_WALKER_LOADS.ITLB_L3
|
||||
.Pq Event BCH , Umask 24H
|
||||
Number of ITLB page walker loads that hit in the L3.
|
||||
.It Li PAGE_WALKER_LOADS.DTLB_MEMORY
|
||||
.Pq Event BCH , Umask 18H
|
||||
Number of DTLB page walker loads from memory.
|
||||
.It Li PAGE_WALKER_LOADS.ITLB_MEMORY
|
||||
.Pq Event BCH , Umask 28H
|
||||
Number of ITLB page walker loads from memory.
|
||||
.It Li TLB_FLUSH.DTLB_THREAD
|
||||
.Pq Event BDH , Umask 01H
|
||||
DTLB flush attempts of the thread-specific entries.
|
||||
.It Li TLB_FLUSH.STLB_ANY
|
||||
.Pq Event BDH , Umask 20H
|
||||
Count number of STLB flush attempts.
|
||||
.It Li INST_RETIRED.ANY_P
|
||||
.Pq Event C0H , Umask 00H
|
||||
Number of instructions at retirement.
|
||||
.It Li INST_RETIRED.ALL
|
||||
.Pq Event C0H , Umask 01H
|
||||
Precise instruction retired event with HW to reduce
|
||||
effect of PEBS shadow in IP distribution.
|
||||
.It Li OTHER_ASSISTS.AVX_TO_SSE
|
||||
.Pq Event C1H , Umask 08H
|
||||
Number of transitions from AVX-256 to legacy SSE
|
||||
when penalty applicable.
|
||||
.It Li OTHER_ASSISTS.SSE_TO_AVX
|
||||
.Pq Event C1H , Umask 10H
|
||||
Number of transitions from SSE to AVX-256 when
|
||||
penalty applicable.
|
||||
.It Li OTHER_ASSISTS.ANY_WB_ASSIST
|
||||
.Pq Event C1H , Umask 40H
|
||||
Number of microcode assists invoked by HW upon
|
||||
uop writeback.
|
||||
.It Li UOPS_RETIRED.ALL
|
||||
.Pq Event C2H , Umask 01H
|
||||
Counts the number of micro-ops retired, Use
|
||||
cmask=1 and invert to count active cycles or stalled
|
||||
cycles.
|
||||
.It Li UOPS_RETIRED.RETIRE_SLOTS
|
||||
.Pq Event C2H , Umask 02H
|
||||
Counts the number of retirement slots used each
|
||||
cycle.
|
||||
.It Li MACHINE_CLEARS.MEMORY_ORDERING
|
||||
.Pq Event C3H , Umask 02H
|
||||
Counts the number of machine clears due to memory
|
||||
order conflicts.
|
||||
.It Li MACHINE_CLEARS.SMC
|
||||
.Pq Event C3H , Umask 04H
|
||||
Number of self-modifying-code machine clears
|
||||
detected.
|
||||
.It Li MACHINE_CLEARS.MASKMOV
|
||||
.Pq Event C3H , Umask 20H
|
||||
Counts the number of executed AVX masked load
|
||||
operations that refer to an illegal address range with
|
||||
the mask bits set to 0.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C4H , Umask 00H
|
||||
Branch instructions at retirement.
|
||||
.It Li BR_INST_RETIRED.CONDITIONAL
|
||||
.Pq Event C4H , Umask 01H
|
||||
Counts the number of conditional branch instructions Supports PEBS
|
||||
retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_CALL
|
||||
.Pq Event C4H , Umask 02H
|
||||
Direct and indirect near call instructions retired.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C4H , Umask 04H
|
||||
Counts the number of branch instructions retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_RETURN
|
||||
.Pq Event C4H , Umask 08H
|
||||
Counts the number of near return instructions
|
||||
retired.
|
||||
.It Li BR_INST_RETIRED.NOT_TAKEN
|
||||
.Pq Event C4H , Umask 10H
|
||||
Counts the number of not taken branch instructions
|
||||
retired.
|
||||
It Li BR_INST_RETIRED.NEAR_TAKEN
|
||||
.Pq Event C4H , Umask 20H
|
||||
Number of near taken branches retired.
|
||||
.It Li BR_INST_RETIRED.FAR_BRANCH
|
||||
.Pq Event C4H , Umask 40H
|
||||
Number of far branches retired.
|
||||
.It Li BR_MISP_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C5H , Umask 00H
|
||||
Mispredicted branch instructions at retirement
|
||||
.It Li BR_MISP_RETIRED.CONDITIONAL
|
||||
.Pq Event C5H , Umask 01H
|
||||
Mispredicted conditional branch instructions retired.
|
||||
.It Li BR_MISP_RETIRED.CONDITIONAL
|
||||
.Pq Event C5H , Umask 04H
|
||||
Mispredicted macro branch instructions retired.
|
||||
.It Li FP_ASSIST.X87_OUTPUT
|
||||
.Pq Event CAH , Umask 02H
|
||||
Number of X87 FP assists due to Output values.
|
||||
.It Li FP_ASSIST.X87_INPUT
|
||||
.Pq Event CAH , Umask 04H
|
||||
Number of X87 FP assists due to input values.
|
||||
.It Li FP_ASSIST.SIMD_OUTPUT
|
||||
.Pq Event CAH , Umask 08H
|
||||
Number of SIMD FP assists due to Output values.
|
||||
.It Li FP_ASSIST.SIMD_INPUT
|
||||
.Pq Event CAH , Umask 10H
|
||||
Number of SIMD FP assists due to input values.
|
||||
.It Li FP_ASSIST.ANY
|
||||
.Pq Event CAH , Umask 1EH
|
||||
Cycles with any input/output SSE* or FP assists.
|
||||
.It Li ROB_MISC_EVENTS.LBR_INSERTS
|
||||
.Pq Event CCH , Umask 20H
|
||||
Count cases of saving new LBR records by hardware.
|
||||
.It Li MEM_TRANS_RETIRED.LOAD_LATENCY
|
||||
.Pq Event CDH , Umask 01H
|
||||
Randomly sampled loads whose latency is above a
|
||||
user defined threshold. A small fraction of the overall
|
||||
loads are sampled due to randomization.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
|
||||
.Pq Event D0H , Umask 11H
|
||||
Count retired load uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
|
||||
.Pq Event D0H , Umask 12H
|
||||
Count retired store uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
|
||||
.Pq Event D0H , Umask 41H
|
||||
Count retired load uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_STORES
|
||||
.Pq Event D0H , Umask 42H
|
||||
Count retired store uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_LOADS
|
||||
.Pq Event D0H , Umask 81H
|
||||
Count all retired load uops.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_STORES
|
||||
.Pq Event D0H , Umask 82H
|
||||
Count all retired store uops.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.Pq Event D1H , Umask 01H
|
||||
Retired load uops with L1 cache hits as data sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
|
||||
.Pq Event D1H , Umask 02H
|
||||
Retired load uops with L2 cache hits as data sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
||||
.Pq Event D1H , Umask 04H
|
||||
Retired load uops with LLC cache hits as data
|
||||
sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L2_MISS
|
||||
.Pq Event D1H , Umask 10H
|
||||
Retired load uops missed L2. Unknown data source
|
||||
excluded.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB
|
||||
.Pq Event D1H , Umask 40H
|
||||
Retired load uops which data sources were load uops
|
||||
missed L1 but hit FB due to preceding miss to the
|
||||
same cache line with data not ready.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS
|
||||
.Pq Event D2H , Umask 01H
|
||||
Retired load uops which data sources were LLC hit
|
||||
and cross-core snoop missed in on-pkg core cache.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
|
||||
.Pq Event D2H , Umask 02H
|
||||
Retired load uops which data sources were LLC and
|
||||
cross-core snoop hits in on-pkg core cache.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
|
||||
.Pq Event D2H , Umask 04H
|
||||
Retired load uops which data sources were HitM
|
||||
responses from shared LLC.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
|
||||
.Pq Event D2H , Umask 08H
|
||||
Retired load uops which data sources were hits in
|
||||
LLC without snoops required.
|
||||
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
|
||||
.Pq Event D3H , Umask 01H
|
||||
Retired load uops which data sources missed LLC but
|
||||
serviced from local dram.
|
||||
.It Li BACLEARS.ANY
|
||||
.Pq Event E6H , Umask 1FH
|
||||
Number of front end re-steers due to BPU
|
||||
misprediction.
|
||||
.It Li L2_TRANS.DEMAND_DATA_RD
|
||||
.Pq Event F0H , Umask 01H
|
||||
Demand Data Read requests that access L2 cache.
|
||||
.It Li L2_TRANS.RFO
|
||||
.Pq Event F0H , Umask 02H
|
||||
RFO requests that access L2 cache.
|
||||
.It Li L2_TRANS.CODE_RD
|
||||
.Pq Event F0H , Umask 04H
|
||||
L2 cache accesses when fetching instructions.
|
||||
.It Li L2_TRANS.ALL_PF
|
||||
.Pq Event F0H , Umask 08H
|
||||
Any MLC or LLC HW prefetch accessing L2, including
|
||||
rejects.
|
||||
.It Li L2_TRANS.L1D_WB
|
||||
.Pq Event F0H , Umask 10H
|
||||
L1D writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.L2_FILL
|
||||
.Pq Event F0H , Umask 20H
|
||||
L2 fill requests that access L2 cache.
|
||||
.It Li L2_TRANS.L2_WB
|
||||
.Pq Event F0H , Umask 40H
|
||||
L2 writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.ALL_REQUESTS
|
||||
.Pq Event F0H , Umask 80H
|
||||
Transactions accessing L2 pipe.
|
||||
.It Li L2_LINES_IN.I
|
||||
.Pq Event F1H , Umask 01H
|
||||
L2 cache lines in I state filling L2.
|
||||
.It Li L2_LINES_IN.S
|
||||
.Pq Event F1H , Umask 02H
|
||||
L2 cache lines in S state filling L2.
|
||||
.It Li L2_LINES_IN.E
|
||||
.Pq Event F1H , Umask 04H
|
||||
L2 cache lines in E state filling L2.
|
||||
.It Li L2_LINES_IN.ALL
|
||||
.Pq Event F1H , Umask 07H
|
||||
L2 cache lines filling L2.
|
||||
.It Li L2_LINES_OUT.DEMAND_CLEAN
|
||||
.Pq Event F2H , Umask 05H
|
||||
Clean L2 cache lines evicted by demand.
|
||||
.It Li L2_LINES_OUT.DEMAND_DIRTY
|
||||
.Pq Event F2H , Umask 06H
|
||||
Dirty L2 cache lines evicted by demand.
|
||||
.El
|
||||
.Sh SEE ALSO
|
||||
.Xr pmc 3 ,
|
||||
.Xr pmc.atom 3 ,
|
||||
.Xr pmc.core 3 ,
|
||||
.Xr pmc.iaf 3 ,
|
||||
.Xr pmc.ucf 3 ,
|
||||
.Xr pmc.k7 3 ,
|
||||
.Xr pmc.k8 3 ,
|
||||
.Xr pmc.p4 3 ,
|
||||
.Xr pmc.p5 3 ,
|
||||
.Xr pmc.p6 3 ,
|
||||
.Xr pmc.corei7 3 ,
|
||||
.Xr pmc.corei7uc 3 ,
|
||||
.Xr pmc.haswell 3 ,
|
||||
.Xr pmc.haswelluc 3 ,
|
||||
.Xr pmc.ivybridge 3 ,
|
||||
.Xr pmc.ivybridgexeon 3 ,
|
||||
.Xr pmc.sandybridge 3 ,
|
||||
.Xr pmc.sandybridgeuc 3 ,
|
||||
.Xr pmc.sandybridgexeon 3 ,
|
||||
.Xr pmc.westmere 3 ,
|
||||
.Xr pmc.westmereuc 3 ,
|
||||
.Xr pmc.soft 3 ,
|
||||
.Xr pmc.tsc 3 ,
|
||||
.Xr pmc_cpuinfo 3 ,
|
||||
.Xr pmclog 3 ,
|
||||
.Xr hwpmc 4
|
||||
.Sh HISTORY
|
||||
Support for the Haswell Xeon microarchitecture first appeared in
|
||||
.Fx 10.2 .
|
||||
.Sh AUTHORS
|
||||
The
|
||||
.Lb libpmc
|
||||
library was written by
|
||||
.An "Joseph Koshy"
|
||||
.Aq jkoshy@FreeBSD.org .
|
||||
The support for the Haswell Xeon
|
||||
microarchitecture was written by
|
||||
.An "Randall Stewart"
|
||||
.Aq rrs@FreeBSD.org .
|
||||
@ -449,80 +449,60 @@ Stalls caused by changing prefix length of the instruction.
|
||||
.It Li ILD_STALL.IQ_FULL
|
||||
.Pq Event 87H , Umask 04H
|
||||
Stall cycles due to IQ is full.
|
||||
.It Li BR_INST_EXEC.COND
|
||||
.Pq Event 88H , Umask 01H
|
||||
Qualify conditional near branch instructions executed, but not necessarily
|
||||
retired.
|
||||
Must combine with umask 40H, 80H.
|
||||
.It Li BR_INST_EXEC.NONTAKEN_COND
|
||||
.Pq Event 88H , Umask 41H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and not taken.
|
||||
.It Li BR_INST_EXEC.TAKEN_COND
|
||||
.Pq Event 88H , Umask 81H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and taken.
|
||||
.It Li BR_INST_EXEC.DIRECT_JMP
|
||||
.Pq Event 88H , Umask 02H
|
||||
Qualify all unconditional near branch instructions excluding calls and
|
||||
.Pq Event 88H , Umask 82H
|
||||
Count all unconditional near branch instructions excluding calls and
|
||||
indirect branches.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 88H , Umask 04H
|
||||
Qualify executed indirect near branch instructions that are not calls nor
|
||||
.Pq Event 88H , Umask 84H
|
||||
Count executed indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.RETURN_NEAR
|
||||
.Pq Event 88H , Umask 08H
|
||||
Qualify indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H.
|
||||
.Pq Event 88H , Umask 88H
|
||||
Count indirect near branches that have a return mnemonic.
|
||||
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 10H
|
||||
Qualify unconditional near call branch instructions, excluding non call
|
||||
.Pq Event 88H , Umask 90H
|
||||
Count unconditional near call branch instructions, excluding non call
|
||||
branch, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 20H
|
||||
Qualify indirect near calls, including both register and memory indirect,
|
||||
.Pq Event 88H , Umask A0H
|
||||
Count indirect near calls, including both register and memory indirect,
|
||||
executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.NONTAKEN
|
||||
.Pq Event 88H , Umask 40H
|
||||
Qualify non-taken near branches executed.
|
||||
Applicable to umask 01H only.
|
||||
.It Li BR_INST_EXEC.TAKEN
|
||||
.Pq Event 88H , Umask 80H
|
||||
Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H,
|
||||
10H, 20H.
|
||||
.It Li BR_INST_EXEC.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li BR_MISP_EXEC.COND
|
||||
.Pq Event 89H , Umask 01H
|
||||
Qualify conditional near branch instructions mispredicted.
|
||||
Must combine with umask 40H, 80H.
|
||||
.It Li BR_MISP_EXEC.NONTAKEN_COND
|
||||
.Pq Event 89H , Umask 41H
|
||||
Count conditional near branch instructions mispredicted as nontaken.
|
||||
.It Li BR_MISP_EXEC.TAKEN_COND
|
||||
.Pq Event 89H , Umask 81H
|
||||
Count conditional near branch instructions mispredicted as taken.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 89H , Umask 04H
|
||||
Qualify mispredicted indirect near branch instructions that are not calls
|
||||
.Pq Event 89H , Umask 84H
|
||||
Count mispredicted indirect near branch instructions that are not calls
|
||||
nor returns.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.RETURN_NEAR
|
||||
.Pq Event 89H , Umask 08H
|
||||
Qualify mispredicted indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H.
|
||||
.Pq Event 89H , Umask 88H
|
||||
Count mispredicted indirect near branches that have a return mnemonic.
|
||||
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 10H
|
||||
Qualify mispredicted unconditional near call branch instructions, excluding
|
||||
.Pq Event 89H , Umask 90H
|
||||
Count mispredicted unconditional near call branch instructions, excluding
|
||||
non call branch, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 20H
|
||||
Qualify mispredicted indirect near calls, including both register and memory
|
||||
.Pq Event 89H , Umask A0H
|
||||
Count mispredicted indirect near calls, including both register and memory
|
||||
indirect, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.NONTAKEN
|
||||
.Pq Event 89H , Umask 40H
|
||||
Qualify mispredicted non-taken near branches executed.
|
||||
Applicable to umask 01H only.
|
||||
.It Li BR_MISP_EXEC.TAKEN
|
||||
.Pq Event 89H , Umask 80H
|
||||
Qualify mispredicted taken near branches executed. Must combine with
|
||||
01H,02H, 04H, 08H, 10H, 20H.
|
||||
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
||||
.Pq Event 89H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
Counts all mispredicted near executed branches (not necessarily retired).
|
||||
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
||||
.Pq Event 9CH , Umask 01H
|
||||
Count number of non-delivered uops to RAT per thread.
|
||||
@ -726,31 +706,24 @@ Specify threshold in MSR 0x3F6.
|
||||
.Pq Event CDH , Umask 02H
|
||||
Sample stores and collect precise store operation via PEBS record.
|
||||
PMC3 only.
|
||||
.It Li MEM_UOP_RETIRED.LOADS
|
||||
.Pq Event D0H , Umask 01H
|
||||
Qualify retired memory uops that are loads. Combine with umask 10H, 20H,
|
||||
40H, 80H.
|
||||
Supports PEBS.
|
||||
.It Li MEM_UOP_RETIRED.STORES
|
||||
.Pq Event D0H , Umask 02H
|
||||
Qualify retired memory uops that are stores. Combine with umask 10H, 20H,
|
||||
40H, 80H.
|
||||
.It Li MEM_UOP_RETIRED.STLB_MISS
|
||||
.Pq Event D0H , Umask 10H
|
||||
Qualify retired memory uops with STLB miss. Must combine with umask 01H,
|
||||
02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.LOCK
|
||||
.Pq Event D0H , Umask 20H
|
||||
Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to
|
||||
produce counts.
|
||||
.It Li MEM_UOP_RETIRED.SPLIT
|
||||
.Pq Event D0H , Umask 40H
|
||||
Qualify retired memory uops with line split. Must combine with umask 01H,
|
||||
02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.ALL
|
||||
.Pq Event D0H , Umask 80H
|
||||
Qualify any retired memory uops. Must combine with umask 01H, 02H, to
|
||||
produce counts.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
|
||||
.Pq Event D0H , Umask 11H
|
||||
Count retired load uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
|
||||
.Pq Event D0H , Umask 12H
|
||||
Count retired store uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
|
||||
.Pq Event D0H , Umask 41H
|
||||
Count retired load uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_STORES
|
||||
.Pq Event D0H , Umask 42H
|
||||
Count retired store uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_LOADS
|
||||
.Pq Event D0H , Umask 81H
|
||||
Count all retired load uops.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_STORES
|
||||
.Pq Event D0H , Umask 82H
|
||||
Count all retired store uops.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.Pq Event D1H , Umask 01H
|
||||
Retired load uops with L1 cache hits as data sources.
|
||||
|
||||
@ -449,80 +449,60 @@ Stalls caused by changing prefix length of the instruction.
|
||||
.It Li ILD_STALL.IQ_FULL
|
||||
.Pq Event 87H , Umask 04H
|
||||
Stall cycles due to IQ is full.
|
||||
.It Li BR_INST_EXEC.COND
|
||||
.Pq Event 88H , Umask 01H
|
||||
Qualify conditional near branch instructions executed, but not necessarily
|
||||
retired.
|
||||
Must combine with umask 40H, 80H.
|
||||
.It Li BR_INST_EXEC.NONTAKEN_COND
|
||||
.Pq Event 88H , Umask 41H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and not taken.
|
||||
.It Li BR_INST_EXEC.TAKEN_COND
|
||||
.Pq Event 88H , Umask 81H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and taken.
|
||||
.It Li BR_INST_EXEC.DIRECT_JMP
|
||||
.Pq Event 88H , Umask 02H
|
||||
Qualify all unconditional near branch instructions excluding calls and
|
||||
.Pq Event 88H , Umask 82H
|
||||
Count all unconditional near branch instructions excluding calls and
|
||||
indirect branches.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 88H , Umask 04H
|
||||
Qualify executed indirect near branch instructions that are not calls nor
|
||||
.Pq Event 88H , Umask 84H
|
||||
Count executed indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.RETURN_NEAR
|
||||
.Pq Event 88H , Umask 08H
|
||||
Qualify indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H.
|
||||
.Pq Event 88H , Umask 88H
|
||||
Count indirect near branches that have a return mnemonic.
|
||||
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 10H
|
||||
Qualify unconditional near call branch instructions, excluding non call
|
||||
.Pq Event 88H , Umask 90H
|
||||
Count unconditional near call branch instructions, excluding non call
|
||||
branch, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 20H
|
||||
Qualify indirect near calls, including both register and memory indirect,
|
||||
.Pq Event 88H , Umask A0H
|
||||
Count indirect near calls, including both register and memory indirect,
|
||||
executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_INST_EXEC.NONTAKEN
|
||||
.Pq Event 88H , Umask 40H
|
||||
Qualify non-taken near branches executed.
|
||||
Applicable to umask 01H only.
|
||||
.It Li BR_INST_EXEC.TAKEN
|
||||
.Pq Event 88H , Umask 80H
|
||||
Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H,
|
||||
10H, 20H.
|
||||
.It Li BR_INST_EXEC.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li BR_MISP_EXEC.COND
|
||||
.Pq Event 89H , Umask 01H
|
||||
Qualify conditional near branch instructions mispredicted.
|
||||
Must combine with umask 40H, 80H.
|
||||
.It Li BR_MISP_EXEC.NONTAKEN_COND
|
||||
.Pq Event 89H , Umask 41H
|
||||
Count conditional near branch instructions mispredicted as nontaken.
|
||||
.It Li BR_MISP_EXEC.TAKEN_COND
|
||||
.Pq Event 89H , Umask 81H
|
||||
Count conditional near branch instructions mispredicted as taken.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 89H , Umask 04H
|
||||
Qualify mispredicted indirect near branch instructions that are not calls
|
||||
.Pq Event 89H , Umask 84H
|
||||
Count mispredicted indirect near branch instructions that are not calls
|
||||
nor returns.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.RETURN_NEAR
|
||||
.Pq Event 89H , Umask 08H
|
||||
Qualify mispredicted indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H.
|
||||
.Pq Event 89H , Umask 88H
|
||||
Count mispredicted indirect near branches that have a return mnemonic.
|
||||
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 10H
|
||||
Qualify mispredicted unconditional near call branch instructions, excluding
|
||||
.Pq Event 89H , Umask 90H
|
||||
Count mispredicted unconditional near call branch instructions, excluding
|
||||
non call branch, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 20H
|
||||
Qualify mispredicted indirect near calls, including both register and memory
|
||||
.Pq Event 89H , Umask A0H
|
||||
Count mispredicted indirect near calls, including both register and memory
|
||||
indirect, executed.
|
||||
Must combine with umask 80H.
|
||||
.It Li BR_MISP_EXEC.NONTAKEN
|
||||
.Pq Event 89H , Umask 40H
|
||||
Qualify mispredicted non-taken near branches executed.
|
||||
Applicable to umask 01H only.
|
||||
.It Li BR_MISP_EXEC.TAKEN
|
||||
.Pq Event 89H , Umask 80H
|
||||
Qualify mispredicted taken near branches executed. Must combine with
|
||||
01H,02H, 04H, 08H, 10H, 20H.
|
||||
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
||||
.Pq Event 89H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
Counts all mispredicted near executed branches (not necessarily retired).
|
||||
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
||||
.Pq Event 9CH , Umask 01H
|
||||
Count number of non-delivered uops to RAT per thread.
|
||||
@ -738,31 +718,24 @@ Specify threshold in MSR 0x3F6.
|
||||
.Pq Event CDH , Umask 02H
|
||||
Sample stores and collect precise store operation via PEBS record.
|
||||
PMC3 only.
|
||||
.It Li MEM_UOP_RETIRED.LOADS
|
||||
.Pq Event D0H , Umask 01H
|
||||
Qualify retired memory uops that are loads. Combine with umask 10H, 20H,
|
||||
40H, 80H.
|
||||
Supports PEBS.
|
||||
.It Li MEM_UOP_RETIRED.STORES
|
||||
.Pq Event D0H , Umask 02H
|
||||
Qualify retired memory uops that are stores. Combine with umask 10H, 20H,
|
||||
40H, 80H.
|
||||
.It Li MEM_UOP_RETIRED.STLB_MISS
|
||||
.Pq Event D0H , Umask 10H
|
||||
Qualify retired memory uops with STLB miss. Must combine with umask 01H,
|
||||
02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.LOCK
|
||||
.Pq Event D0H , Umask 20H
|
||||
Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to
|
||||
produce counts.
|
||||
.It Li MEM_UOP_RETIRED.SPLIT
|
||||
.Pq Event D0H , Umask 40H
|
||||
Qualify retired memory uops with line split. Must combine with umask 01H,
|
||||
02H, to produce counts.
|
||||
.It Li MEM_UOP_RETIRED.ALL
|
||||
.Pq Event D0H , Umask 80H
|
||||
Qualify any retired memory uops. Must combine with umask 01H, 02H, to
|
||||
produce counts.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_LOADS
|
||||
.Pq Event D0H , Umask 11H
|
||||
Count retired load uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.STLB_MISS_STORES
|
||||
.Pq Event D0H , Umask 12H
|
||||
Count retired store uops that missed the STLB.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_LOADS
|
||||
.Pq Event D0H , Umask 41H
|
||||
Count retired load uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.SPLIT_STORES
|
||||
.Pq Event D0H , Umask 42H
|
||||
Count retired store uops that were split across a cache line.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_LOADS
|
||||
.Pq Event D0H , Umask 81H
|
||||
Count all retired load uops.
|
||||
.It Li MEM_UOPS_RETIRED.ALL_STORES
|
||||
.Pq Event D0H , Umask 82H
|
||||
Count all retired store uops.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.Pq Event D1H , Umask 01H
|
||||
Retired load uops with L1 cache hits as data sources.
|
||||
|
||||
@ -497,80 +497,60 @@ Stalls caused by changing prefix length of the instruction.
|
||||
.It Li ILD_STALL.IQ_FULL
|
||||
.Pq Event 87H, Umask 04H
|
||||
Stall cycles due to IQ is full.
|
||||
.It Li BR_INST_EXEC.COND
|
||||
.Pq Event 88H, Umask 01H
|
||||
Qualify conditional near branch instructions executed, but not necessarily
|
||||
retired.
|
||||
Must combine with umask 40H, 80H
|
||||
.It Li BR_INST_EXEC.NONTAKEN_COND
|
||||
.Pq Event 88H , Umask 41H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and not taken.
|
||||
.It Li BR_INST_EXEC.TAKEN_COND
|
||||
.Pq Event 88H , Umask 81H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and taken.
|
||||
.It Li BR_INST_EXEC.DIRECT_JMP
|
||||
.Pq Event 88H, Umask 02H
|
||||
Qualify all unconditional near branch instructions excluding calls and indirect
|
||||
branches.
|
||||
Must combine with umask 80H
|
||||
.Pq Event 88H , Umask 82H
|
||||
Count all unconditional near branch instructions excluding calls and
|
||||
indirect branches.
|
||||
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 88H, Umask 04H
|
||||
Qualify executed indirect near branch instructions that are not calls nor
|
||||
.Pq Event 88H , Umask 84H
|
||||
Count executed indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
Must combine with umask 80H
|
||||
.It Li BR_INST_EXEC.RETURN_NEAR
|
||||
.Pq Event 88H, Umask 08H
|
||||
Qualify indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H
|
||||
.Pq Event 88H , Umask 88H
|
||||
Count indirect near branches that have a return mnemonic.
|
||||
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 88H, Umask 10H
|
||||
Qualify unconditional near call branch instructions, excluding non call branch,
|
||||
executed.
|
||||
Must combine with umask 80H
|
||||
.Pq Event 88H , Umask 90H
|
||||
Count unconditional near call branch instructions, excluding non call
|
||||
branch, executed.
|
||||
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 88H, Umask 20H
|
||||
Qualify indirect near calls, including both register and memory indirect,
|
||||
.Pq Event 88H , Umask A0H
|
||||
Count indirect near calls, including both register and memory indirect,
|
||||
executed.
|
||||
Must combine with umask 80H
|
||||
.It Li BR_INST_EXEC.NONTAKEN
|
||||
.Pq Event 88H, Umask 40H
|
||||
Qualify non-taken near branches executed.
|
||||
Applicable to umask 01H only
|
||||
.It Li BR_INST_EXEC.TAKEN
|
||||
.Pq Event 88H, Umask 80H
|
||||
Qualify taken near branches executed.
|
||||
Must combine with 01H,02H, 04H, 08H, 10H, 20H
|
||||
.It Li BR_INST_EXE.ALL_BRANCHES
|
||||
.Pq Event 88H, Umask FFH
|
||||
.It Li BR_INST_EXEC.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li BR_MISP_EXEC.COND
|
||||
.Pq Event 89H, Umask 01H
|
||||
Qualify conditional near branch instructions mispredicted.
|
||||
Must combine with umask 40H, 80H
|
||||
.It Li BR_MISP_EXEC.NONTAKEN_COND
|
||||
.Pq Event 89H , Umask 41H
|
||||
Count conditional near branch instructions mispredicted as nontaken.
|
||||
.It Li BR_MISP_EXEC.TAKEN_COND
|
||||
.Pq Event 89H , Umask 81H
|
||||
Count conditional near branch instructions mispredicted as taken.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 89H, Umask 04H
|
||||
Qualify mispredicted indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
Must combine with umask 80H
|
||||
.Pq Event 89H , Umask 84H
|
||||
Count mispredicted indirect near branch instructions that are not calls
|
||||
nor returns.
|
||||
.It Li BR_MISP_EXEC.RETURN_NEAR
|
||||
.Pq Event 89H, Umask 08H
|
||||
Qualify mispredicted indirect near branches that have a return mnemonic.
|
||||
Must combine with umask 80H
|
||||
.Pq Event 89H , Umask 88H
|
||||
Count mispredicted indirect near branches that have a return mnemonic.
|
||||
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 89H, Umask 10H
|
||||
Qualify mispredicted unconditional near call branch instructions, excluding non
|
||||
call branch, executed.
|
||||
Must combine with umask 80H
|
||||
.Pq Event 89H , Umask 90H
|
||||
Count mispredicted unconditional near call branch instructions, excluding
|
||||
non call branch, executed.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 89H, Umask 20H
|
||||
Qualify mispredicted indirect near calls, including both register and memory
|
||||
.Pq Event 89H , Umask A0H
|
||||
Count mispredicted indirect near calls, including both register and memory
|
||||
indirect, executed.
|
||||
Must combine with umask 80H
|
||||
.It Li BR_MISP_EXEC.NONTAKEN
|
||||
.Pq Event 89H, Umask 40H
|
||||
Qualify mispredicted non-taken near branches executed.
|
||||
Applicable to umask 01H only
|
||||
.It Li BR_MISP_EXEC.TAKEN
|
||||
.Pq Event 89H, Umask 80H
|
||||
Qualify mispredicted taken near branches executed.
|
||||
Must combine with 01H,02H, 04H, 08H, 10H, 20H
|
||||
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
||||
.Pq Event 89H, Umask FFH
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.Pq Event 89H , Umask FFH
|
||||
Counts all mispredicted near executed branches (not necessarily retired).
|
||||
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
||||
.Pq Event 9CH, Umask 01H
|
||||
Count number of non-delivered uops to RAT per thread.
|
||||
|
||||
@ -543,73 +543,60 @@ instruction.
|
||||
.It Li ILD_STALL.IQ_FULL
|
||||
.Pq Event 87H , Umask 04H
|
||||
Stall cycles due to IQ is full.
|
||||
.It Li BR_INST_EXEC.COND
|
||||
.Pq Event 88H , Umask 01H
|
||||
Qualify conditional near branch instructions
|
||||
executed, but not necessarily retired.
|
||||
.It Li BR_INST_EXEC.NONTAKEN_COND
|
||||
.Pq Event 88H , Umask 41H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and not taken.
|
||||
.It Li BR_INST_EXEC.TAKEN_COND
|
||||
.Pq Event 88H , Umask 81H
|
||||
Count conditional near branch instructions that were executed (but not
|
||||
necessarily retired) and taken.
|
||||
.It Li BR_INST_EXEC.DIRECT_JMP
|
||||
.Pq Event 88H , Umask 02H
|
||||
Qualify all unconditional near branch instructions
|
||||
excluding calls and indirect branches.
|
||||
.Pq Event 88H , Umask 82H
|
||||
Count all unconditional near branch instructions excluding calls and
|
||||
indirect branches.
|
||||
.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 88H , Umask 04H
|
||||
Qualify executed indirect near branch instructions
|
||||
that are not calls nor returns.
|
||||
.Pq Event 88H , Umask 84H
|
||||
Count executed indirect near branch instructions that are not calls nor
|
||||
returns.
|
||||
.It Li BR_INST_EXEC.RETURN_NEAR
|
||||
.Pq Event 88H , Umask 08H
|
||||
Qualify indirect near branches that have a return
|
||||
mnemonic.
|
||||
.Pq Event 88H , Umask 88H
|
||||
Count indirect near branches that have a return mnemonic.
|
||||
.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 10H
|
||||
Qualify unconditional near call branch instructions,
|
||||
excluding non call branch, executed.
|
||||
.Pq Event 88H , Umask 90H
|
||||
Count unconditional near call branch instructions, excluding non call
|
||||
branch, executed.
|
||||
.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 88H , Umask 20H
|
||||
Qualify indirect near calls, including both register
|
||||
and memory indirect, executed.
|
||||
.It Li BR_INST_EXEC.NONTAKEN
|
||||
.Pq Event 88H , Umask 40H
|
||||
Qualify non-taken near branches executed.
|
||||
.It Li BR_INST_EXEC.TAKEN
|
||||
.Pq Event 88H , Umask 80H
|
||||
Qualify taken near branches executed. Must
|
||||
combine with 01H,02H, 04H, 08H, 10H, 20H.
|
||||
.It Li BR_INST_EXE.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask A0H
|
||||
Count indirect near calls, including both register and memory indirect,
|
||||
executed.
|
||||
.It Li BR_INST_EXEC.ALL_BRANCHES
|
||||
.Pq Event 88H , Umask FFH
|
||||
Counts all near executed branches (not necessarily
|
||||
retired).
|
||||
.It Li BR_MISP_EXEC.COND
|
||||
.Pq Event 89H , Umask 01H
|
||||
Qualify conditional near branch instructions
|
||||
mispredicted.
|
||||
Counts all near executed branches (not necessarily retired).
|
||||
.It Li BR_MISP_EXEC.NONTAKEN_COND
|
||||
.Pq Event 89H , Umask 41H
|
||||
Count conditional near branch instructions mispredicted as nontaken.
|
||||
.It Li BR_MISP_EXEC.TAKEN_COND
|
||||
.Pq Event 89H , Umask 81H
|
||||
Count conditional near branch instructions mispredicted as taken.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
|
||||
.Pq Event 89H , Umask 04H
|
||||
Qualify mispredicted indirect near branch
|
||||
instructions that are not calls nor returns.
|
||||
.Pq Event 89H , Umask 84H
|
||||
Count mispredicted indirect near branch instructions that are not calls
|
||||
nor returns.
|
||||
.It Li BR_MISP_EXEC.RETURN_NEAR
|
||||
.Pq Event 89H , Umask 08H
|
||||
Qualify mispredicted indirect near branches that
|
||||
have a return mnemonic.
|
||||
.Pq Event 89H , Umask 88H
|
||||
Count mispredicted indirect near branches that have a return mnemonic.
|
||||
.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 10H
|
||||
Qualify mispredicted unconditional near call branch
|
||||
instructions, excluding non call branch, executed.
|
||||
.Pq Event 89H , Umask 90H
|
||||
Count mispredicted unconditional near call branch instructions, excluding
|
||||
non call branch, executed.
|
||||
.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
|
||||
.Pq Event 89H , Umask 20H
|
||||
Qualify mispredicted indirect near calls, including
|
||||
both register and memory indirect, executed.
|
||||
.It Li BR_MISP_EXEC.NONTAKEN
|
||||
.Pq Event 89H , Umask 40H
|
||||
Qualify mispredicted non-taken near branches
|
||||
executed,.
|
||||
.It Li BR_MISP_EXEC.TAKEN
|
||||
.Pq Event 89H , Umask 80H
|
||||
Qualify mispredicted taken near branches executed.
|
||||
Must combine with 01H,02H, 04H, 08H, 10H, 20H
|
||||
.Pq Event 89H , Umask A0H
|
||||
Count mispredicted indirect near calls, including both register and memory
|
||||
indirect, executed.
|
||||
.It Li BR_MISP_EXEC.ALL_BRANCHES
|
||||
.Pq Event 89H , Umask FFH
|
||||
Counts all near executed branches (not necessarily
|
||||
retired).
|
||||
Counts all mispredicted near executed branches (not necessarily retired).
|
||||
.It Li IDQ_UOPS_NOT_DELIVERED.CORE
|
||||
.Pq Event 9CH , Umask 01H
|
||||
Count number of non-delivered uops to RAT per
|
||||
|
||||
@ -80,7 +80,6 @@ SRCS+= aeabi_memcmp.S aeabi_memcpy.S aeabi_memmove.S aeabi_memset.S
|
||||
.if ${MACHINE_CPUARCH} == "powerpc"
|
||||
.PATH: ${.CURDIR}/../libc/quad
|
||||
SRCS+= ashldi3.c ashrdi3.c
|
||||
.PATH: ${.CURDIR}/../libc/powerpc/gen
|
||||
SRCS+= syncicache.c
|
||||
.endif
|
||||
|
||||
@ -89,11 +88,7 @@ SRCS+= syncicache.c
|
||||
SRCS+= uuid_equal.c uuid_is_nil.c
|
||||
|
||||
# _setjmp/_longjmp
|
||||
.if ${MACHINE_ARCH} == "powerpc64"
|
||||
.PATH: ${.CURDIR}/powerpc
|
||||
.else
|
||||
.PATH: ${.CURDIR}/${MACHINE_CPUARCH}
|
||||
.endif
|
||||
SRCS+= _setjmp.S
|
||||
|
||||
# decompression functionality from libbz2
|
||||
|
||||
@ -42,7 +42,7 @@
|
||||
#define JMP_xer 24*REGWIDTH
|
||||
#define JMP_sig 25*REGWIDTH
|
||||
|
||||
ASENTRY_NOPROF(setjmp)
|
||||
ASENTRY_NOPROF(_setjmp)
|
||||
ST_REG 31, JMP_r31(3)
|
||||
/* r1, r2, r14-r30 */
|
||||
ST_REG 1, JMP_r1 (3)
|
||||
@ -79,7 +79,7 @@ ASENTRY_NOPROF(setjmp)
|
||||
|
||||
|
||||
.extern sigsetmask
|
||||
ASENTRY_NOPROF(longjmp)
|
||||
ASENTRY_NOPROF(_longjmp)
|
||||
LD_REG 31, JMP_r31(3)
|
||||
/* r1, r2, r14-r30 */
|
||||
LD_REG 1, JMP_r1 (3)
|
||||
|
||||
103
lib/libstand/powerpc/syncicache.c
Normal file
103
lib/libstand/powerpc/syncicache.c
Normal file
@ -0,0 +1,103 @@
|
||||
/*-
|
||||
* Copyright (C) 1995-1997, 1999 Wolfgang Solfrank.
|
||||
* Copyright (C) 1995-1997, 1999 TooLs GmbH.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by TooLs GmbH.
|
||||
* 4. The name of TooLs GmbH may not be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $NetBSD: syncicache.c,v 1.2 1999/05/05 12:36:40 tsubai Exp $
|
||||
*/
|
||||
|
||||
#ifndef lint
|
||||
static const char rcsid[] =
|
||||
"$FreeBSD$";
|
||||
#endif /* not lint */
|
||||
|
||||
#include <sys/param.h>
|
||||
#if defined(_KERNEL) || defined(_STANDALONE)
|
||||
#include <sys/time.h>
|
||||
#include <sys/proc.h>
|
||||
#include <vm/vm.h>
|
||||
#endif
|
||||
#include <sys/sysctl.h>
|
||||
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/md_var.h>
|
||||
|
||||
#ifdef _STANDALONE
|
||||
int cacheline_size = 32;
|
||||
#endif
|
||||
|
||||
#if !defined(_KERNEL) && !defined(_STANDALONE)
|
||||
#include <stdlib.h>
|
||||
|
||||
int cacheline_size = 0;
|
||||
|
||||
static void getcachelinesize(void);
|
||||
|
||||
static void
|
||||
getcachelinesize()
|
||||
{
|
||||
static int cachemib[] = { CTL_MACHDEP, CPU_CACHELINE };
|
||||
int clen;
|
||||
|
||||
clen = sizeof(cacheline_size);
|
||||
|
||||
if (sysctl(cachemib, sizeof(cachemib) / sizeof(cachemib[0]),
|
||||
&cacheline_size, &clen, NULL, 0) < 0 || !cacheline_size) {
|
||||
abort();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void
|
||||
__syncicache(void *from, int len)
|
||||
{
|
||||
int l, off;
|
||||
char *p;
|
||||
|
||||
#if !defined(_KERNEL) && !defined(_STANDALONE)
|
||||
if (!cacheline_size)
|
||||
getcachelinesize();
|
||||
#endif
|
||||
|
||||
off = (u_int)from & (cacheline_size - 1);
|
||||
l = len += off;
|
||||
p = (char *)from - off;
|
||||
|
||||
do {
|
||||
__asm __volatile ("dcbst 0,%0" :: "r"(p));
|
||||
p += cacheline_size;
|
||||
} while ((l -= cacheline_size) > 0);
|
||||
__asm __volatile ("sync");
|
||||
p = (char *)from - off;
|
||||
do {
|
||||
__asm __volatile ("icbi 0,%0" :: "r"(p));
|
||||
p += cacheline_size;
|
||||
} while ((len -= cacheline_size) > 0);
|
||||
__asm __volatile ("sync; isync");
|
||||
}
|
||||
|
||||
@ -337,7 +337,7 @@ struct pthread_key {
|
||||
|
||||
/*
|
||||
* lwpid_t is 32bit but kernel thr API exports tid as long type
|
||||
* in very earily date.
|
||||
* to preserve the ABI for M:N model in very early date (r131431).
|
||||
*/
|
||||
#define TID(thread) ((uint32_t) ((thread)->tid))
|
||||
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
.\" from: @(#)j0.3 6.7 (Berkeley) 4/19/91
|
||||
.\" $FreeBSD$
|
||||
.\"
|
||||
.Dd February 18, 2008
|
||||
.Dd March 10, 2015
|
||||
.Dt J0 3
|
||||
.Os
|
||||
.Sh NAME
|
||||
@ -77,24 +77,17 @@
|
||||
The functions
|
||||
.Fn j0 ,
|
||||
.Fn j0f ,
|
||||
.Fn j1
|
||||
.Fn j1 ,
|
||||
and
|
||||
.Fn j1f
|
||||
compute the
|
||||
.Em Bessel function of the first kind of the order
|
||||
0 and the
|
||||
.Em order
|
||||
1, respectively,
|
||||
for the
|
||||
real value
|
||||
compute the Bessel function of the first kind of orders
|
||||
0 and 1 for the real value
|
||||
.Fa x ;
|
||||
the functions
|
||||
.Fn jn
|
||||
and
|
||||
.Fn jnf
|
||||
compute the
|
||||
.Em Bessel function of the first kind of the integer
|
||||
.Em order
|
||||
compute the Bessel function of the first kind of the integer order
|
||||
.Fa n
|
||||
for the real value
|
||||
.Fa x .
|
||||
@ -105,13 +98,8 @@ The functions
|
||||
.Fn y1 ,
|
||||
and
|
||||
.Fn y1f
|
||||
compute the linearly independent
|
||||
.Em Bessel function of the second kind of the order
|
||||
0 and the
|
||||
.Em order
|
||||
1, respectively,
|
||||
for the
|
||||
positive
|
||||
compute the linearly independent Bessel function of the second kind
|
||||
of orders 0 and 1 for the positive
|
||||
.Em real
|
||||
value
|
||||
.Fa x ;
|
||||
@ -119,9 +107,7 @@ the functions
|
||||
.Fn yn
|
||||
and
|
||||
.Fn ynf
|
||||
compute the
|
||||
.Em Bessel function of the second kind for the integer
|
||||
.Em order
|
||||
compute the Bessel function of the second kind for the integer order
|
||||
.Fa n
|
||||
for the positive
|
||||
.Em real
|
||||
@ -141,11 +127,20 @@ and
|
||||
.Fn ynf .
|
||||
If
|
||||
.Fa x
|
||||
is negative, these routines will generate an invalid exception and
|
||||
return \*(Na.
|
||||
is negative, including -\*(If, these routines will generate an invalid
|
||||
exception and return \*(Na.
|
||||
If
|
||||
.Fa x
|
||||
is 0 or a sufficiently small positive number, these routines
|
||||
is \*(Pm0, these routines
|
||||
will generate a divide-by-zero exception and return -\*(If.
|
||||
If
|
||||
.Fa x
|
||||
is a sufficiently small positive number, then
|
||||
.Fn y1 ,
|
||||
.Fn y1f ,
|
||||
.Fn yn ,
|
||||
and
|
||||
.Fn ynf
|
||||
will generate an overflow exception and return -\*(If.
|
||||
.Sh SEE ALSO
|
||||
.Xr math 3
|
||||
|
||||
@ -64,6 +64,8 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
static double pzero(double), qzero(double);
|
||||
|
||||
static const volatile double vone = 1, vzero = 0;
|
||||
|
||||
static const double
|
||||
huge = 1e300,
|
||||
one = 1.0,
|
||||
@ -150,10 +152,16 @@ __ieee754_y0(double x)
|
||||
|
||||
EXTRACT_WORDS(hx,lx,x);
|
||||
ix = 0x7fffffff&hx;
|
||||
/* Y0(NaN) is NaN, y0(-inf) is Nan, y0(inf) is 0 */
|
||||
if(ix>=0x7ff00000) return one/(x+x*x);
|
||||
if((ix|lx)==0) return -one/zero;
|
||||
if(hx<0) return zero/zero;
|
||||
/*
|
||||
* y0(NaN) = NaN.
|
||||
* y0(Inf) = 0.
|
||||
* y0(-Inf) = NaN and raise invalid exception.
|
||||
*/
|
||||
if(ix>=0x7ff00000) return vone/(x+x*x);
|
||||
/* y0(+-0) = -inf and raise divide-by-zero exception. */
|
||||
if((ix|lx)==0) return -one/vzero;
|
||||
/* y0(x<0) = NaN and raise invalid exception. */
|
||||
if(hx<0) return vzero/vzero;
|
||||
if(ix >= 0x40000000) { /* |x| >= 2.0 */
|
||||
/* y0(x) = sqrt(2/(pi*x))*(p0(x)*sin(x0)+q0(x)*cos(x0))
|
||||
* where x0 = x-pi/4
|
||||
|
||||
@ -16,11 +16,17 @@
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* See e_j0.c for complete comments.
|
||||
*/
|
||||
|
||||
#include "math.h"
|
||||
#include "math_private.h"
|
||||
|
||||
static float pzerof(float), qzerof(float);
|
||||
|
||||
static const volatile float vone = 1, vzero = 0;
|
||||
|
||||
static const float
|
||||
huge = 1e30,
|
||||
one = 1.0,
|
||||
@ -107,10 +113,9 @@ __ieee754_y0f(float x)
|
||||
|
||||
GET_FLOAT_WORD(hx,x);
|
||||
ix = 0x7fffffff&hx;
|
||||
/* Y0(NaN) is NaN, y0(-inf) is Nan, y0(inf) is 0 */
|
||||
if(ix>=0x7f800000) return one/(x+x*x);
|
||||
if(ix==0) return -one/zero;
|
||||
if(hx<0) return zero/zero;
|
||||
if(ix>=0x7f800000) return vone/(x+x*x);
|
||||
if(ix==0) return -one/vzero;
|
||||
if(hx<0) return vzero/vzero;
|
||||
if(ix >= 0x40000000) { /* |x| >= 2.0 */
|
||||
/* y0(x) = sqrt(2/(pi*x))*(p0(x)*sin(x0)+q0(x)*cos(x0))
|
||||
* where x0 = x-pi/4
|
||||
|
||||
@ -64,6 +64,8 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
static double pone(double), qone(double);
|
||||
|
||||
static const volatile double vone = 1, vzero = 0;
|
||||
|
||||
static const double
|
||||
huge = 1e300,
|
||||
one = 1.0,
|
||||
@ -147,10 +149,16 @@ __ieee754_y1(double x)
|
||||
|
||||
EXTRACT_WORDS(hx,lx,x);
|
||||
ix = 0x7fffffff&hx;
|
||||
/* if Y1(NaN) is NaN, Y1(-inf) is NaN, Y1(inf) is 0 */
|
||||
if(ix>=0x7ff00000) return one/(x+x*x);
|
||||
if((ix|lx)==0) return -one/zero;
|
||||
if(hx<0) return zero/zero;
|
||||
/*
|
||||
* y1(NaN) = NaN.
|
||||
* y1(Inf) = 0.
|
||||
* y1(-Inf) = NaN and raise invalid exception.
|
||||
*/
|
||||
if(ix>=0x7ff00000) return vone/(x+x*x);
|
||||
/* y1(+-0) = -inf and raise divide-by-zero exception. */
|
||||
if((ix|lx)==0) return -one/vzero;
|
||||
/* y1(x<0) = NaN and raise invalid exception. */
|
||||
if(hx<0) return vzero/vzero;
|
||||
if(ix >= 0x40000000) { /* |x| >= 2.0 */
|
||||
s = sin(x);
|
||||
c = cos(x);
|
||||
|
||||
@ -16,11 +16,17 @@
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* See e_j1.c for complete comments.
|
||||
*/
|
||||
|
||||
#include "math.h"
|
||||
#include "math_private.h"
|
||||
|
||||
static float ponef(float), qonef(float);
|
||||
|
||||
static const volatile float vone = 1, vzero = 0;
|
||||
|
||||
static const float
|
||||
huge = 1e30,
|
||||
one = 1.0,
|
||||
@ -104,10 +110,9 @@ __ieee754_y1f(float x)
|
||||
|
||||
GET_FLOAT_WORD(hx,x);
|
||||
ix = 0x7fffffff&hx;
|
||||
/* if Y1(NaN) is NaN, Y1(-inf) is NaN, Y1(inf) is 0 */
|
||||
if(ix>=0x7f800000) return one/(x+x*x);
|
||||
if(ix==0) return -one/zero;
|
||||
if(hx<0) return zero/zero;
|
||||
if(ix>=0x7f800000) return vone/(x+x*x);
|
||||
if(ix==0) return -one/vzero;
|
||||
if(hx<0) return vzero/vzero;
|
||||
if(ix >= 0x40000000) { /* |x| >= 2.0 */
|
||||
s = sinf(x);
|
||||
c = cosf(x);
|
||||
|
||||
@ -43,6 +43,8 @@ __FBSDID("$FreeBSD$");
|
||||
#include "math.h"
|
||||
#include "math_private.h"
|
||||
|
||||
static const volatile double vone = 1, vzero = 0;
|
||||
|
||||
static const double
|
||||
invsqrtpi= 5.64189583547756279280e-01, /* 0x3FE20DD7, 0x50429B6D */
|
||||
two = 2.00000000000000000000e+00, /* 0x40000000, 0x00000000 */
|
||||
@ -220,10 +222,12 @@ __ieee754_yn(int n, double x)
|
||||
|
||||
EXTRACT_WORDS(hx,lx,x);
|
||||
ix = 0x7fffffff&hx;
|
||||
/* if Y(n,NaN) is NaN */
|
||||
/* yn(n,NaN) = NaN */
|
||||
if((ix|((u_int32_t)(lx|-lx))>>31)>0x7ff00000) return x+x;
|
||||
if((ix|lx)==0) return -one/zero;
|
||||
if(hx<0) return zero/zero;
|
||||
/* yn(n,+-0) = -inf and raise divide-by-zero exception. */
|
||||
if((ix|lx)==0) return -one/vzero;
|
||||
/* yn(n,x<0) = NaN and raise invalid exception. */
|
||||
if(hx<0) return vzero/vzero;
|
||||
sign = 1;
|
||||
if(n<0){
|
||||
n = -n;
|
||||
|
||||
@ -16,9 +16,15 @@
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
/*
|
||||
* See e_jn.c for complete comments.
|
||||
*/
|
||||
|
||||
#include "math.h"
|
||||
#include "math_private.h"
|
||||
|
||||
static const volatile float vone = 1, vzero = 0;
|
||||
|
||||
static const float
|
||||
two = 2.0000000000e+00, /* 0x40000000 */
|
||||
one = 1.0000000000e+00; /* 0x3F800000 */
|
||||
@ -172,10 +178,9 @@ __ieee754_ynf(int n, float x)
|
||||
|
||||
GET_FLOAT_WORD(hx,x);
|
||||
ix = 0x7fffffff&hx;
|
||||
/* if Y(n,NaN) is NaN */
|
||||
if(ix>0x7f800000) return x+x;
|
||||
if(ix==0) return -one/zero;
|
||||
if(hx<0) return zero/zero;
|
||||
if(ix==0) return -one/vzero;
|
||||
if(hx<0) return vzero/vzero;
|
||||
sign = 1;
|
||||
if(n<0){
|
||||
n = -n;
|
||||
|
||||
@ -16,9 +16,10 @@ SCRIPTS= disklatency \
|
||||
disklatencycmd \
|
||||
hotopen \
|
||||
nfsclienttime \
|
||||
udptrack \
|
||||
tcpstate \
|
||||
tcptrack \
|
||||
tcpconn
|
||||
tcpconn
|
||||
|
||||
SCRIPTSDIR= ${SHAREDIR}/dtrace
|
||||
|
||||
|
||||
@ -41,6 +41,6 @@ tcp:kernel::state-change
|
||||
{
|
||||
newstate = args[3]->tcps_state;
|
||||
oldstate = args[5]->tcps_state;
|
||||
printf("%d %s\t\t%s\n", args[1]->pid, tcp_state_string[oldstate],
|
||||
printf("%s\t\t%s\n", tcp_state_string[oldstate],
|
||||
tcp_state_string[newstate]);
|
||||
}
|
||||
|
||||
53
share/dtrace/udptrack
Executable file
53
share/dtrace/udptrack
Executable file
@ -0,0 +1,53 @@
|
||||
#!/usr/sbin/dtrace -s
|
||||
/*
|
||||
* Copyright (c) 2015 George V. Neville-Neil
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*
|
||||
* The udptrack D script shows various information about UDP
|
||||
* data that are sent and received on the host.
|
||||
*
|
||||
* Usage: udptrack
|
||||
*/
|
||||
|
||||
#pragma D option quiet
|
||||
udp:kernel::receive
|
||||
{
|
||||
printf("Received %d bytes of data from %s:%d\n",
|
||||
args[4]->udp_length,
|
||||
args[2]->ip_saddr,
|
||||
args[4]->udp_sport);
|
||||
tracemem(args[4]->udp_hdr, 64);
|
||||
}
|
||||
|
||||
udp:kernel::send
|
||||
{
|
||||
printf("Sent %d bytes of data to %s:%d\n",
|
||||
args[4]->udp_length,
|
||||
args[2]->ip_daddr,
|
||||
args[4]->udp_dport);
|
||||
tracemem(args[4]->udp_hdr, 64);
|
||||
}
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
.\" @(#)core.5 8.3 (Berkeley) 12/11/93
|
||||
.\" $FreeBSD$
|
||||
.\"
|
||||
.Dd November 22, 2012
|
||||
.Dd March 8, 2015
|
||||
.Dt CORE 5
|
||||
.Os
|
||||
.Sh NAME
|
||||
@ -101,25 +101,23 @@ variable
|
||||
.Va kern.sugid_coredump
|
||||
to 1.
|
||||
.Pp
|
||||
Corefiles can be compressed by the kernel if the following items
|
||||
are included in the kernel configuration file:
|
||||
Corefiles can be compressed by the kernel if the following item
|
||||
is included in the kernel configuration file:
|
||||
.Bl -tag -width "1234567890" -compact -offset "12345"
|
||||
.It options
|
||||
COMPRESS_USER_CORES
|
||||
.It devices
|
||||
gzio
|
||||
GZIO
|
||||
.El
|
||||
.Pp
|
||||
When COMPRESS_USER_CORES is included the following sysctls can control
|
||||
if core files will be compressed:
|
||||
When the GZIO option is included, the following sysctls control whether core
|
||||
files will be compressed:
|
||||
.Bl -tag -width "kern.compress_user_cores_gzlevel" -compact -offset "12345"
|
||||
.It Em kern.compress_user_cores_gzlevel
|
||||
Gzip compression level.
|
||||
Defaults to -1.
|
||||
Defaults to 6.
|
||||
.It Em kern.compress_user_cores
|
||||
Actually compress user cores.
|
||||
Core files will have the suffix
|
||||
.Em .gz
|
||||
Compressed core files will have a suffix of
|
||||
.Ql .gz
|
||||
appended to them.
|
||||
.El
|
||||
.Sh EXAMPLES
|
||||
|
||||
@ -24,7 +24,7 @@
|
||||
.\"
|
||||
.\" $FreeBSD$
|
||||
.\"
|
||||
.Dd September 18, 2014
|
||||
.Dd March 8, 2015
|
||||
.Dt SDT 9
|
||||
.Os
|
||||
.Sh NAME
|
||||
@ -196,13 +196,13 @@ They are meant to be added to executable code and can be used to instrument the
|
||||
code in which they are called.
|
||||
.Sh EXAMPLES
|
||||
The following probe definition will create a DTrace probe called
|
||||
.Ql icmp::unreach:pkt-receive ,
|
||||
.Ql icmp:::receive-unreachable ,
|
||||
which would hypothetically be triggered when the kernel receives an ICMP packet
|
||||
of type Destination Unreachable:
|
||||
.Bd -literal -offset indent
|
||||
SDT_PROVIDER_DECLARE(icmp);
|
||||
|
||||
SDT_PROBE_DEFINE1(icmp, , unreach, pkt__receive,
|
||||
SDT_PROBE_DEFINE1(icmp, , , receive__unreachable,
|
||||
"struct icmp *");
|
||||
|
||||
.Ed
|
||||
@ -286,10 +286,10 @@ This manual page was written by
|
||||
.Sh BUGS
|
||||
The
|
||||
.Nm
|
||||
macros allow the module name of a probe to be specified as part of a probe
|
||||
definition.
|
||||
However, the DTrace framework uses the module name of probes to determine
|
||||
which probes should be destroyed when a kernel module is unloaded, so the module
|
||||
macros allow the module and function names of a probe to be specified as part of
|
||||
a probe definition.
|
||||
The DTrace framework uses the module name of probes to determine which probes
|
||||
should be destroyed when a kernel module is unloaded, so the module
|
||||
name of a probe should match the name of the module in which its defined.
|
||||
.Nm
|
||||
will set the module name properly if it is left unspecified in the probe
|
||||
|
||||
@ -28,7 +28,7 @@
|
||||
.\"
|
||||
.\" $FreeBSD$
|
||||
.\"
|
||||
.Dd November 19, 2011
|
||||
.Dd March 8, 2015
|
||||
.Dt VOP_VPTOCNP 9
|
||||
.Os
|
||||
.Sh NAME
|
||||
@ -36,9 +36,10 @@
|
||||
.Nd translate a vnode to its component name
|
||||
.Sh SYNOPSIS
|
||||
.In sys/param.h
|
||||
.In sys/ucred.h
|
||||
.In sys/vnode.h
|
||||
.Ft int
|
||||
.Fn VOP_VPTOCNP "struct vnode *vp" "struct vnode **dvp" "char *buf" "int *buflen"
|
||||
.Fn VOP_VPTOCNP "struct vnode *vp" "struct vnode **dvp" "struct ucred *cred" "char *buf" "int *buflen"
|
||||
.Sh DESCRIPTION
|
||||
This translates a vnode into its component name, and writes that name to
|
||||
the head of the buffer specified by
|
||||
@ -49,6 +50,8 @@ The vnode to translate.
|
||||
.It Fa dvp
|
||||
The vnode of the parent directory of
|
||||
.Fa vp .
|
||||
.It Fa cred
|
||||
The caller credentials.
|
||||
.It Fa buf
|
||||
The buffer into which to prepend the component name.
|
||||
.It Fa buflen
|
||||
@ -59,7 +62,8 @@ The default implementation of
|
||||
.Nm
|
||||
scans through
|
||||
.Fa vp Ns 's
|
||||
parent directory looking for a dirent with a matching file number. If
|
||||
parent directory looking for a dirent with a matching file number.
|
||||
If
|
||||
.Fa vp
|
||||
is not a directory, then
|
||||
.Nm
|
||||
|
||||
@ -178,6 +178,7 @@ ian [label="Ian Lepore\nian@FreeBSD.org\n2013/01/07"]
|
||||
iedowse [label="Ian Dowse\niedowse@FreeBSD.org\n2000/12/01"]
|
||||
imp [label="Warner Losh\nimp@FreeBSD.org\n1996/09/20"]
|
||||
ivoras [label="Ivan Voras\nivoras@FreeBSD.org\n2008/06/10"]
|
||||
jah [label="Jason A. Harmening\njah@FreeBSD.org\n2015/03/08"]
|
||||
jamie [label="Jamie Gritton\njamie@FreeBSD.org\n2009/01/28"]
|
||||
jasone [label="Jason Evans\njasone@FreeBSD.org\n1999/03/03"]
|
||||
jceel [label="Jakub Klama\njceel@FreeBSD.org\n2011/09/25"]
|
||||
@ -296,6 +297,7 @@ tuexen [label="Michael Tuexen\ntuexen@FreeBSD.org\n2009/06/06"]
|
||||
tychon [label="Tycho Nightingale\ntychon@FreeBSD.org\n2014/01/21"]
|
||||
ume [label="Hajimu UMEMOTO\nume@FreeBSD.org\n2000/02/26"]
|
||||
uqs [label="Ulrich Spoerlein\nuqs@FreeBSD.org\n2010/01/28"]
|
||||
vangyzen [label="Eric van Gyzen\nvangyzen@FreeBSD.org\n2015/03/08"]
|
||||
vanhu [label="Yvan Vanhullebus\nvanhu@FreeBSD.org\n2008/07/21"]
|
||||
versus [label="Konrad Jankowski\nversus@FreeBSD.org\n2008/10/27"]
|
||||
weongyo [label="Weongyo Jeong\nweongyo@FreeBSD.org\n2007/12/21"]
|
||||
@ -548,6 +550,7 @@ ken -> slm
|
||||
kib -> ae
|
||||
kib -> dchagin
|
||||
kib -> gjb
|
||||
kib -> jah
|
||||
kib -> jlh
|
||||
kib -> jpaetzel
|
||||
kib -> lulf
|
||||
@ -560,6 +563,7 @@ kib -> rmh
|
||||
kib -> stas
|
||||
kib -> tijl
|
||||
kib -> trociny
|
||||
kib -> vangyzen
|
||||
kib -> zont
|
||||
|
||||
kmacy -> lstewart
|
||||
|
||||
@ -247,8 +247,8 @@ ENTRY(armv7_idcache_wbinv_range)
|
||||
add r0, r0, ip
|
||||
subs r1, r1, ip
|
||||
bhi .Larmv7_id_wbinv_next
|
||||
isb /* instruction synchronization barrier */
|
||||
dsb /* data synchronization barrier */
|
||||
isb /* instruction synchronization barrier */
|
||||
RET
|
||||
END(armv7_idcache_wbinv_range)
|
||||
|
||||
@ -258,8 +258,8 @@ ENTRY_NP(armv7_icache_sync_all)
|
||||
#else
|
||||
mcr CP15_ICIALLU
|
||||
#endif
|
||||
isb /* instruction synchronization barrier */
|
||||
dsb /* data synchronization barrier */
|
||||
isb /* instruction synchronization barrier */
|
||||
RET
|
||||
END(armv7_icache_sync_all)
|
||||
|
||||
@ -267,13 +267,13 @@ ENTRY_NP(armv7_icache_sync_range)
|
||||
ldr ip, .Larmv7_icache_line_size
|
||||
ldr ip, [ip]
|
||||
.Larmv7_sync_next:
|
||||
mcr CP15_ICIMVAU(r0)
|
||||
mcr CP15_DCCMVAC(r0)
|
||||
mcr CP15_ICIMVAU(r0)
|
||||
add r0, r0, ip
|
||||
subs r1, r1, ip
|
||||
bhi .Larmv7_sync_next
|
||||
isb /* instruction synchronization barrier */
|
||||
dsb /* data synchronization barrier */
|
||||
isb /* instruction synchronization barrier */
|
||||
RET
|
||||
END(armv7_icache_sync_range)
|
||||
|
||||
|
||||
@ -34,7 +34,14 @@ __FBSDID("$FreeBSD$");
|
||||
#include <machine/cpuinfo.h>
|
||||
#include <machine/cpu-v6.h>
|
||||
|
||||
struct cpuinfo cpuinfo;
|
||||
struct cpuinfo cpuinfo =
|
||||
{
|
||||
/* Use safe defaults for start */
|
||||
.dcache_line_size = 32,
|
||||
.dcache_line_mask = 31,
|
||||
.icache_line_size = 32,
|
||||
.icache_line_mask = 31,
|
||||
};
|
||||
|
||||
/* Read and parse CPU id scheme */
|
||||
void
|
||||
@ -122,4 +129,10 @@ cpuinfo_init(void)
|
||||
cpuinfo.generic_timer_ext = (cpuinfo.id_pfr1 >> 16) & 0xF;
|
||||
cpuinfo.virtualization_ext = (cpuinfo.id_pfr1 >> 12) & 0xF;
|
||||
cpuinfo.security_ext = (cpuinfo.id_pfr1 >> 4) & 0xF;
|
||||
|
||||
/* L1 Cache sizes */
|
||||
cpuinfo.dcache_line_size = 1 << (CPU_CT_DMINLINE(cpuinfo.ctr ) + 2);
|
||||
cpuinfo.dcache_line_mask = cpuinfo.dcache_line_size - 1;
|
||||
cpuinfo.icache_line_size= 1 << (CPU_CT_IMINLINE(cpuinfo.ctr ) + 2);
|
||||
cpuinfo.icache_line_mask = cpuinfo.icache_line_size - 1;
|
||||
}
|
||||
|
||||
@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <machine/cpu.h>
|
||||
#include <machine/proc.h>
|
||||
#include <machine/cpufunc.h>
|
||||
#include <machine/cpuinfo.h>
|
||||
#include <machine/pte.h>
|
||||
#include <machine/intr.h>
|
||||
#include <machine/sysarch.h>
|
||||
@ -146,3 +147,8 @@ ASSYM(MAXCOMLEN, MAXCOMLEN);
|
||||
ASSYM(MAXCPU, MAXCPU);
|
||||
ASSYM(NIRQ, NIRQ);
|
||||
ASSYM(PCPU_SIZE, sizeof(struct pcpu));
|
||||
|
||||
ASSYM(DCACHE_LINE_SIZE, offsetof(struct cpuinfo, dcache_line_size));
|
||||
ASSYM(DCACHE_LINE_MASK, offsetof(struct cpuinfo, dcache_line_mask));
|
||||
ASSYM(ICACHE_LINE_SIZE, offsetof(struct cpuinfo, icache_line_size));
|
||||
ASSYM(ICACHE_LINE_MASK, offsetof(struct cpuinfo, icache_line_mask));
|
||||
|
||||
@ -240,7 +240,6 @@ bcm_fb_init(void *arg)
|
||||
}
|
||||
else {
|
||||
device_printf(sc->dev, "Failed to set framebuffer info\n");
|
||||
return;
|
||||
}
|
||||
|
||||
config_intrhook_disestablish(&sc->init_hook);
|
||||
|
||||
@ -186,17 +186,12 @@ bcm_fb_init(void *arg)
|
||||
|
||||
fbd = device_add_child(sc->dev, "fbd",
|
||||
device_get_unit(sc->dev));
|
||||
if (fbd == NULL) {
|
||||
if (fbd == NULL)
|
||||
device_printf(sc->dev, "Failed to add fbd child\n");
|
||||
return;
|
||||
}
|
||||
if (device_probe_and_attach(fbd) != 0) {
|
||||
else if (device_probe_and_attach(fbd) != 0)
|
||||
device_printf(sc->dev, "Failed to attach fbd device\n");
|
||||
return;
|
||||
}
|
||||
} else {
|
||||
device_printf(sc->dev, "Failed to set framebuffer info\n");
|
||||
return;
|
||||
}
|
||||
|
||||
config_intrhook_disestablish(&sc->init_hook);
|
||||
|
||||
176
sys/arm/broadcom/bcm2835/bcm283x_dwc_fdt.c
Normal file
176
sys/arm/broadcom/bcm2835/bcm283x_dwc_fdt.c
Normal file
@ -0,0 +1,176 @@
|
||||
/*
|
||||
* Copyright 2015 Andrew Turner.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/bus.h>
|
||||
#include <sys/callout.h>
|
||||
#include <sys/condvar.h>
|
||||
#include <sys/module.h>
|
||||
|
||||
#include <dev/ofw/ofw_bus_subr.h>
|
||||
|
||||
#include <dev/usb/usb.h>
|
||||
#include <dev/usb/usbdi.h>
|
||||
|
||||
#include <dev/usb/usb_busdma.h>
|
||||
#include <dev/usb/usb_process.h>
|
||||
|
||||
#include <dev/usb/usb_controller.h>
|
||||
#include <dev/usb/usb_bus.h>
|
||||
|
||||
#include <dev/usb/controller/dwc_otg.h>
|
||||
#include <dev/usb/controller/dwc_otg_fdt.h>
|
||||
|
||||
#include <vm/vm.h>
|
||||
#include <vm/pmap.h>
|
||||
#include <machine/pmap.h>
|
||||
|
||||
#include <arm/broadcom/bcm2835/bcm2835_mbox.h>
|
||||
#include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
|
||||
#include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
|
||||
|
||||
#include "mbox_if.h"
|
||||
|
||||
static device_probe_t bcm283x_dwc_otg_probe;
|
||||
static device_attach_t bcm283x_dwc_otg_attach;
|
||||
|
||||
static int
|
||||
bcm283x_dwc_otg_probe(device_t dev)
|
||||
{
|
||||
|
||||
if (!ofw_bus_status_okay(dev))
|
||||
return (ENXIO);
|
||||
|
||||
if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-usb"))
|
||||
return (ENXIO);
|
||||
|
||||
device_set_desc(dev, "DWC OTG 2.0 integrated USB controller (bcm283x)");
|
||||
|
||||
return (BUS_PROBE_VENDOR);
|
||||
}
|
||||
|
||||
static void
|
||||
bcm283x_dwc_otg_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
|
||||
{
|
||||
bus_addr_t *addr;
|
||||
|
||||
if (err)
|
||||
return;
|
||||
addr = (bus_addr_t *)arg;
|
||||
*addr = PHYS_TO_VCBUS(segs[0].ds_addr);
|
||||
}
|
||||
|
||||
static int
|
||||
bcm283x_dwc_otg_attach(device_t dev)
|
||||
{
|
||||
struct msg_set_power_state *msg;
|
||||
bus_dma_tag_t msg_tag;
|
||||
bus_dmamap_t msg_map;
|
||||
bus_addr_t msg_phys;
|
||||
void *msg_buf;
|
||||
uint32_t reg;
|
||||
device_t mbox;
|
||||
int err;
|
||||
|
||||
/* get mbox device */
|
||||
mbox = devclass_get_device(devclass_find("mbox"), 0);
|
||||
if (mbox == NULL) {
|
||||
device_printf(dev, "can't find mbox\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
err = bus_dma_tag_create(bus_get_dma_tag(dev), 16, 0,
|
||||
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
|
||||
sizeof(struct msg_set_power_state), 1,
|
||||
sizeof(struct msg_set_power_state), 0,
|
||||
NULL, NULL, &msg_tag);
|
||||
if (err != 0) {
|
||||
device_printf(dev, "can't create DMA tag\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
err = bus_dmamem_alloc(msg_tag, (void **)&msg_buf, 0, &msg_map);
|
||||
if (err != 0) {
|
||||
bus_dma_tag_destroy(msg_tag);
|
||||
device_printf(dev, "can't allocate dmamem\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
err = bus_dmamap_load(msg_tag, msg_map, msg_buf,
|
||||
sizeof(struct msg_set_power_state), bcm283x_dwc_otg_cb,
|
||||
&msg_phys, 0);
|
||||
if (err != 0) {
|
||||
bus_dmamem_free(msg_tag, msg_buf, msg_map);
|
||||
bus_dma_tag_destroy(msg_tag);
|
||||
device_printf(dev, "can't load DMA map\n");
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
msg = msg_buf;
|
||||
|
||||
memset(msg, 0, sizeof(*msg));
|
||||
msg->hdr.buf_size = sizeof(*msg);
|
||||
msg->hdr.code = BCM2835_MBOX_CODE_REQ;
|
||||
msg->tag_hdr.tag = BCM2835_MBOX_TAG_SET_POWER_STATE;
|
||||
msg->tag_hdr.val_buf_size = sizeof(msg->body);
|
||||
msg->tag_hdr.val_len = sizeof(msg->body.req);
|
||||
msg->body.req.device_id = BCM2835_MBOX_POWER_ID_USB_HCD;
|
||||
msg->body.req.state = BCM2835_MBOX_POWER_ON | BCM2835_MBOX_POWER_WAIT;
|
||||
msg->end_tag = 0;
|
||||
|
||||
bus_dmamap_sync(msg_tag, msg_map,
|
||||
BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
|
||||
|
||||
MBOX_WRITE(mbox, BCM2835_MBOX_CHAN_PROP, (uint32_t)msg_phys);
|
||||
MBOX_READ(mbox, BCM2835_MBOX_CHAN_PROP, ®);
|
||||
|
||||
bus_dmamap_unload(msg_tag, msg_map);
|
||||
bus_dmamem_free(msg_tag, msg_buf, msg_map);
|
||||
bus_dma_tag_destroy(msg_tag);
|
||||
|
||||
return (dwc_otg_attach(dev));
|
||||
}
|
||||
|
||||
static device_method_t bcm283x_dwc_otg_methods[] = {
|
||||
/* bus interface */
|
||||
DEVMETHOD(device_probe, bcm283x_dwc_otg_probe),
|
||||
DEVMETHOD(device_attach, bcm283x_dwc_otg_attach),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static devclass_t bcm283x_dwc_otg_devclass;
|
||||
|
||||
DEFINE_CLASS_1(bcm283x_dwcotg, bcm283x_dwc_otg_driver, bcm283x_dwc_otg_methods,
|
||||
sizeof(struct dwc_otg_fdt_softc), dwc_otg_driver);
|
||||
DRIVER_MODULE(bcm283x_dwcotg, simplebus, bcm283x_dwc_otg_driver,
|
||||
bcm283x_dwc_otg_devclass, 0, 0);
|
||||
MODULE_DEPEND(bcm283x_dwcotg, usb, 1, 1, 1);
|
||||
@ -15,6 +15,8 @@ arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi
|
||||
arm/broadcom/bcm2835/bcm2835_systimer.c standard
|
||||
arm/broadcom/bcm2835/bcm2835_wdog.c standard
|
||||
|
||||
arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt
|
||||
|
||||
arm/arm/bus_space_base.c standard
|
||||
arm/arm/bus_space_generic.c standard
|
||||
arm/arm/bus_space_asm_generic.S standard
|
||||
|
||||
@ -22,7 +22,6 @@ ident MV-88F78XX0
|
||||
include "../mv/armadaxp/std.mv78x60"
|
||||
|
||||
options SOC_MV_ARMADAXP
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
|
||||
@ -25,13 +25,13 @@ ident BEAGLEBONE
|
||||
|
||||
include "../ti/am335x/std.am335x"
|
||||
|
||||
makeoptions WITHOUT_MODULES="ahc"
|
||||
makeoptions MODULES_EXTRA="dtb/am335x"
|
||||
|
||||
# DTrace support
|
||||
options KDTRACE_HOOKS # Kernel DTrace hooks
|
||||
options DDB_CTF # all architectures - kernel ELF linker loads CTF data
|
||||
makeoptions WITH_CTF=1
|
||||
makeoptions MODULES_OVERRIDE="opensolaris dtrace dtrace/lockstat dtrace/profile dtrace/fbt"
|
||||
makeoptions MODULES_EXTRA+="opensolaris dtrace dtrace/lockstat dtrace/profile dtrace/fbt"
|
||||
|
||||
options HZ=100
|
||||
options SCHED_4BSD # 4BSD scheduler
|
||||
@ -165,5 +165,3 @@ device usfs
|
||||
|
||||
# Flattened Device Tree
|
||||
options FDT # Configure using FDT/DTB data
|
||||
options FDT_DTB_STATIC
|
||||
makeoptions FDT_DTS_FILE=beaglebone.dts
|
||||
|
||||
@ -23,9 +23,6 @@ ident CUBIEBOARD
|
||||
|
||||
include "../allwinner/std.a10"
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
makeoptions WITHOUT_MODULES="ahc"
|
||||
|
||||
options HZ=100
|
||||
options SCHED_4BSD # 4BSD scheduler
|
||||
options PREEMPTION # Enable kernel thread preemption
|
||||
|
||||
@ -23,9 +23,6 @@ ident CUBIEBOARD2
|
||||
|
||||
include "../allwinner/a20/std.a20"
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
makeoptions WITHOUT_MODULES="ahc"
|
||||
|
||||
options HZ=100
|
||||
options SCHED_ULE # ULE scheduler
|
||||
options PREEMPTION # Enable kernel thread preemption
|
||||
|
||||
@ -8,7 +8,6 @@ ident DB-88F78XX
|
||||
include "../mv/discovery/std.db78xxx"
|
||||
|
||||
options SOC_MV_DISCOVERY
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
#makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
@ -8,7 +8,6 @@ ident DB-88F5XXX
|
||||
include "../mv/orion/std.db88f5xxx"
|
||||
|
||||
options SOC_MV_ORION
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
#makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
@ -8,7 +8,6 @@ ident DB-88F6XXX
|
||||
include "../mv/kirkwood/std.db88f6xxx"
|
||||
|
||||
options SOC_MV_KIRKWOOD
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
#makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
#NO_UNIVERSE
|
||||
|
||||
ident DOCKSTAR
|
||||
|
||||
@ -24,8 +25,6 @@ include "../mv/kirkwood/std.db88f6xxx"
|
||||
|
||||
makeoptions FDT_DTS_FILE=dockstar.dts
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
options SOC_MV_KIRKWOOD
|
||||
|
||||
options SCHED_4BSD # 4BSD scheduler
|
||||
|
||||
@ -20,6 +20,7 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
#NO_UNIVERSE
|
||||
|
||||
ident DREAMPLUG-1001
|
||||
|
||||
@ -27,8 +28,6 @@ include "../mv/kirkwood/std.db88f6xxx"
|
||||
|
||||
makeoptions FDT_DTS_FILE=dreamplug-1001.dts
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
options SOC_MV_KIRKWOOD
|
||||
|
||||
options SCHED_4BSD # 4BSD scheduler
|
||||
|
||||
@ -18,9 +18,6 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
makeoptions WITHOUT_MODULES="ahc"
|
||||
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
options HZ=100
|
||||
|
||||
@ -29,9 +29,6 @@ hints "PANDABOARD.hints"
|
||||
|
||||
include "../ti/omap4/pandaboard/std.pandaboard"
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
makeoptions WITHOUT_MODULES="ahc"
|
||||
|
||||
options HZ=100
|
||||
options SCHED_ULE # ULE scheduler
|
||||
options PREEMPTION # Enable kernel thread preemption
|
||||
|
||||
@ -3,12 +3,12 @@
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
#NO_UNIVERSE
|
||||
|
||||
ident SHEEVAPLUG
|
||||
include "../mv/kirkwood/std.db88f6xxx"
|
||||
|
||||
options SOC_MV_KIRKWOOD
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
#makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
@ -8,7 +8,6 @@ ident TS7800
|
||||
include "../mv/orion/std.ts7800"
|
||||
|
||||
options SOC_MV_ORION
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
|
||||
#makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
@ -21,9 +21,6 @@
|
||||
ident VYBRID
|
||||
include "../freescale/vybrid/std.vybrid"
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
makeoptions WITHOUT_MODULES="ahc"
|
||||
|
||||
makeoptions WERROR="-Werror"
|
||||
|
||||
options HZ=100
|
||||
|
||||
@ -23,9 +23,6 @@ ident ZEDBOARD
|
||||
|
||||
include "../xilinx/zedboard/std.zedboard"
|
||||
|
||||
makeoptions MODULES_OVERRIDE=""
|
||||
makeoptions WITHOUT_MODULES="ahc"
|
||||
|
||||
options SCHED_ULE # ULE scheduler
|
||||
options PREEMPTION # Enable kernel thread preemption
|
||||
options INET # InterNETworking
|
||||
|
||||
@ -37,6 +37,9 @@
|
||||
|
||||
#define CPU_ASID_KERNEL 0
|
||||
|
||||
vm_offset_t dcache_wb_pou_checked(vm_offset_t, vm_size_t);
|
||||
vm_offset_t icache_inv_pou_checked(vm_offset_t, vm_size_t);
|
||||
|
||||
/*
|
||||
* Macros to generate CP15 (system control processor) read/write functions.
|
||||
*/
|
||||
@ -302,7 +305,7 @@ icache_sync(vm_offset_t sva, vm_size_t size)
|
||||
vm_offset_t eva = sva + size;
|
||||
|
||||
dsb();
|
||||
for (va = sva; va < eva; va += arm_dcache_align) {
|
||||
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
|
||||
#if __ARM_ARCH >= 7 && defined SMP
|
||||
_CP15_DCCMVAU(va);
|
||||
#else
|
||||
@ -332,6 +335,19 @@ icache_inv_all(void)
|
||||
isb();
|
||||
}
|
||||
|
||||
/* Invalidate branch predictor buffer */
|
||||
static __inline void
|
||||
bpb_inv_all(void)
|
||||
{
|
||||
#if __ARM_ARCH >= 7 && defined SMP
|
||||
_CP15_BPIALLIS();
|
||||
#else
|
||||
_CP15_BPIALL();
|
||||
#endif
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
/* Write back D-cache to PoU */
|
||||
static __inline void
|
||||
dcache_wb_pou(vm_offset_t sva, vm_size_t size)
|
||||
@ -340,7 +356,7 @@ dcache_wb_pou(vm_offset_t sva, vm_size_t size)
|
||||
vm_offset_t eva = sva + size;
|
||||
|
||||
dsb();
|
||||
for (va = sva; va < eva; va += arm_dcache_align) {
|
||||
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
|
||||
#if __ARM_ARCH >= 7 && defined SMP
|
||||
_CP15_DCCMVAU(va);
|
||||
#else
|
||||
@ -358,7 +374,7 @@ dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
|
||||
vm_offset_t eva = sva + size;
|
||||
|
||||
/* invalidate L1 first */
|
||||
for (va = sva; va < eva; va += arm_dcache_align) {
|
||||
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
|
||||
_CP15_DCIMVAC(va);
|
||||
}
|
||||
dsb();
|
||||
@ -368,7 +384,7 @@ dcache_inv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
|
||||
dsb();
|
||||
|
||||
/* then L1 again */
|
||||
for (va = sva; va < eva; va += arm_dcache_align) {
|
||||
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
|
||||
_CP15_DCIMVAC(va);
|
||||
}
|
||||
dsb();
|
||||
@ -383,7 +399,7 @@ dcache_wb_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
|
||||
|
||||
dsb();
|
||||
|
||||
for (va = sva; va < eva; va += arm_dcache_align) {
|
||||
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
|
||||
_CP15_DCCMVAC(va);
|
||||
}
|
||||
dsb();
|
||||
@ -401,7 +417,7 @@ dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
|
||||
dsb();
|
||||
|
||||
/* write back L1 first */
|
||||
for (va = sva; va < eva; va += arm_dcache_align) {
|
||||
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
|
||||
_CP15_DCCMVAC(va);
|
||||
}
|
||||
dsb();
|
||||
@ -410,7 +426,7 @@ dcache_wbinv_poc(vm_offset_t sva, vm_paddr_t pa, vm_size_t size)
|
||||
cpu_l2cache_wbinv_range(pa, size);
|
||||
|
||||
/* then invalidate L1 */
|
||||
for (va = sva; va < eva; va += arm_dcache_align) {
|
||||
for (va = sva; va < eva; va += cpuinfo.dcache_line_size) {
|
||||
_CP15_DCIMVAC(va);
|
||||
}
|
||||
dsb();
|
||||
|
||||
@ -82,6 +82,12 @@ struct cpuinfo {
|
||||
int generic_timer_ext;
|
||||
int virtualization_ext;
|
||||
int security_ext;
|
||||
|
||||
/* L1 cache info */
|
||||
int dcache_line_size;
|
||||
int dcache_line_mask;
|
||||
int icache_line_size;
|
||||
int icache_line_mask;
|
||||
};
|
||||
|
||||
extern struct cpuinfo cpuinfo;
|
||||
|
||||
@ -78,6 +78,14 @@ static struct ti_aintc_softc *ti_aintc_sc = NULL;
|
||||
bus_space_write_4((_sc)->aintc_bst, (_sc)->aintc_bsh, (reg), (val))
|
||||
|
||||
|
||||
static void
|
||||
aintc_post_filter(void *arg)
|
||||
{
|
||||
|
||||
arm_irq_memory_barrier(0);
|
||||
aintc_write_4(ti_aintc_sc, INTC_CONTROL, 1); /* EOI */
|
||||
}
|
||||
|
||||
static int
|
||||
ti_aintc_probe(device_t dev)
|
||||
{
|
||||
@ -124,6 +132,8 @@ ti_aintc_attach(device_t dev)
|
||||
/*Set Priority Threshold */
|
||||
aintc_write_4(sc, INTC_THRESHOLD, 0xFF);
|
||||
|
||||
arm_post_filter = aintc_post_filter;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -149,12 +159,6 @@ arm_get_next_irq(int last_irq)
|
||||
struct ti_aintc_softc *sc = ti_aintc_sc;
|
||||
uint32_t active_irq;
|
||||
|
||||
if (last_irq != -1) {
|
||||
aintc_write_4(sc, INTC_ISR_CLEAR(last_irq >> 5),
|
||||
1UL << (last_irq & 0x1F));
|
||||
aintc_write_4(sc, INTC_CONTROL, 1);
|
||||
}
|
||||
|
||||
/* Get the next active interrupt */
|
||||
active_irq = aintc_read_4(sc, INTC_SIR_IRQ);
|
||||
|
||||
@ -178,6 +182,7 @@ arm_mask_irq(uintptr_t nb)
|
||||
struct ti_aintc_softc *sc = ti_aintc_sc;
|
||||
|
||||
aintc_write_4(sc, INTC_MIR_SET(nb >> 5), (1UL << (nb & 0x1F)));
|
||||
aintc_write_4(sc, INTC_CONTROL, 1); /* EOI */
|
||||
}
|
||||
|
||||
void
|
||||
|
||||
@ -200,7 +200,7 @@ am335x_dmtimer_et_write_4(struct am335x_dmtimer_softc *sc, uint32_t reg,
|
||||
*/
|
||||
#ifdef PPS_SYNC
|
||||
|
||||
#define PPS_CDEV_NAME "pps"
|
||||
#define PPS_CDEV_NAME "dmtpps"
|
||||
|
||||
static void
|
||||
am335x_dmtimer_set_capture_mode(struct am335x_dmtimer_softc *sc, bool force_off)
|
||||
|
||||
@ -1423,5 +1423,6 @@ static driver_t omap4_prcm_driver = {
|
||||
|
||||
static devclass_t omap4_prcm_devclass;
|
||||
|
||||
DRIVER_MODULE(omap4_prcm, simplebus, omap4_prcm_driver, omap4_prcm_devclass, 0, 0);
|
||||
EARLY_DRIVER_MODULE(omap4_prcm, simplebus, omap4_prcm_driver,
|
||||
omap4_prcm_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_EARLY);
|
||||
MODULE_VERSION(omap4_prcm, 1);
|
||||
|
||||
@ -83,7 +83,6 @@ SRCS+= aeabi_memcmp.S aeabi_memcpy.S aeabi_memmove.S aeabi_memset.S
|
||||
.if ${MACHINE_CPUARCH} == "powerpc"
|
||||
.PATH: ${LIBC}/quad
|
||||
SRCS+= ashldi3.c ashrdi3.c
|
||||
.PATH: ${LIBC}/powerpc/gen
|
||||
SRCS+= syncicache.c
|
||||
.endif
|
||||
|
||||
@ -94,8 +93,6 @@ SRCS+= uuid_equal.c uuid_is_nil.c
|
||||
# _setjmp/_longjmp
|
||||
.if ${MACHINE_CPUARCH} == "amd64"
|
||||
.PATH: ${S}/i386
|
||||
.elif ${MACHINE_ARCH} == "powerpc64"
|
||||
.PATH: ${S}/powerpc
|
||||
.else
|
||||
.PATH: ${S}/${MACHINE_CPUARCH}
|
||||
.endif
|
||||
|
||||
@ -45,7 +45,7 @@ u_int32_t acells, scells;
|
||||
|
||||
static char bootargs[128];
|
||||
|
||||
#define HEAP_SIZE 0x80000
|
||||
#define HEAP_SIZE 0x100000
|
||||
|
||||
#define OF_puts(fd, text) OF_write(fd, text, strlen(text))
|
||||
|
||||
|
||||
@ -67,7 +67,7 @@ int
|
||||
__elfN(ofw_exec)(struct preloaded_file *fp)
|
||||
{
|
||||
struct file_metadata *fmp;
|
||||
vm_offset_t mdp;
|
||||
vm_offset_t mdp, dtbp;
|
||||
Elf_Ehdr *e;
|
||||
int error;
|
||||
intptr_t entry;
|
||||
@ -78,15 +78,21 @@ __elfN(ofw_exec)(struct preloaded_file *fp)
|
||||
e = (Elf_Ehdr *)&fmp->md_data;
|
||||
entry = e->e_entry;
|
||||
|
||||
if ((error = md_load(fp->f_args, &mdp)) != 0)
|
||||
if ((error = md_load(fp->f_args, &mdp, &dtbp)) != 0)
|
||||
return (error);
|
||||
|
||||
printf("Kernel entry at 0x%lx ...\n", e->e_entry);
|
||||
|
||||
dev_cleanup();
|
||||
ofw_release_heap();
|
||||
OF_chain((void *)reloc, end - (char *)reloc, (void *)entry,
|
||||
(void *)mdp, sizeof(mdp));
|
||||
if (dtbp != 0) {
|
||||
OF_quiesce();
|
||||
((int (*)(u_long, u_long, u_long, void *, u_long))entry)(dtbp, 0, 0,
|
||||
mdp, sizeof(mdp));
|
||||
} else {
|
||||
OF_chain((void *)reloc, end - (char *)reloc, (void *)entry,
|
||||
(void *)mdp, sizeof(mdp));
|
||||
}
|
||||
|
||||
panic("exec returned");
|
||||
}
|
||||
|
||||
@ -729,6 +729,20 @@ OF_exit()
|
||||
;
|
||||
}
|
||||
|
||||
void
|
||||
OF_quiesce()
|
||||
{
|
||||
static struct {
|
||||
cell_t name;
|
||||
cell_t nargs;
|
||||
cell_t nreturns;
|
||||
} args = {
|
||||
(cell_t)"quiesce",
|
||||
};
|
||||
|
||||
openfirmware(&args);
|
||||
}
|
||||
|
||||
/* Free <size> bytes starting at <virt>, then call <entry> with <arg>. */
|
||||
#if 0
|
||||
void
|
||||
|
||||
@ -82,6 +82,7 @@ void OF_init(int (*openfirm)(void *));
|
||||
|
||||
/* Generic functions */
|
||||
int OF_test(char *);
|
||||
void OF_quiesce(); /* Disable firmware */
|
||||
|
||||
/* Device tree functions */
|
||||
phandle_t OF_peer(phandle_t);
|
||||
|
||||
@ -67,7 +67,7 @@ int
|
||||
ppc64_ofw_elf_exec(struct preloaded_file *fp)
|
||||
{
|
||||
struct file_metadata *fmp;
|
||||
vm_offset_t mdp;
|
||||
vm_offset_t mdp, dtbp;
|
||||
Elf_Ehdr *e;
|
||||
int error;
|
||||
intptr_t entry;
|
||||
@ -80,7 +80,7 @@ ppc64_ofw_elf_exec(struct preloaded_file *fp)
|
||||
/* Handle function descriptor */
|
||||
entry = *(uint64_t *)e->e_entry;
|
||||
|
||||
if ((error = md_load64(fp->f_args, &mdp)) != 0)
|
||||
if ((error = md_load64(fp->f_args, &mdp, &dtbp)) != 0)
|
||||
return (error);
|
||||
|
||||
printf("Kernel entry at 0x%lx ...\n", entry);
|
||||
@ -88,8 +88,14 @@ ppc64_ofw_elf_exec(struct preloaded_file *fp)
|
||||
dev_cleanup();
|
||||
ofw_release_heap();
|
||||
|
||||
OF_chain((void *)reloc, end - (char *)reloc, (void *)entry,
|
||||
(void *)mdp, sizeof(mdp));
|
||||
if (dtbp != 0) {
|
||||
OF_quiesce();
|
||||
((int (*)(u_long, u_long, u_long, void *, u_long))entry)(dtbp, 0, 0,
|
||||
mdp, sizeof(mdp));
|
||||
} else {
|
||||
OF_chain((void *)reloc, end - (char *)reloc, (void *)entry,
|
||||
(void *)mdp, sizeof(mdp));
|
||||
}
|
||||
|
||||
panic("exec returned");
|
||||
}
|
||||
|
||||
@ -21,6 +21,7 @@ LOADER_NFS_SUPPORT?= yes
|
||||
LOADER_TFTP_SUPPORT?= no
|
||||
LOADER_GZIP_SUPPORT?= yes
|
||||
LOADER_BZIP2_SUPPORT?= no
|
||||
LOADER_FDT_SUPPORT?= yes
|
||||
|
||||
.if ${LOADER_DISK_SUPPORT} == "yes"
|
||||
CFLAGS+= -DLOADER_DISK_SUPPORT
|
||||
@ -49,6 +50,14 @@ CFLAGS+= -DLOADER_NFS_SUPPORT
|
||||
.if ${LOADER_TFTP_SUPPORT} == "yes"
|
||||
CFLAGS+= -DLOADER_TFTP_SUPPORT
|
||||
.endif
|
||||
.if ${LOADER_FDT_SUPPORT} == "yes"
|
||||
SRCS+= ofwfdt.c
|
||||
CFLAGS+= -I${.CURDIR}/../../fdt
|
||||
CFLAGS+= -I${.OBJDIR}/../../fdt
|
||||
CFLAGS+= -I${.CURDIR}/../../../contrib/libfdt
|
||||
CFLAGS+= -DLOADER_FDT_SUPPORT
|
||||
LIBFDT= ${.OBJDIR}/../../fdt/libfdt.a
|
||||
.endif
|
||||
|
||||
.if ${MK_FORTH} != "no"
|
||||
# Enable BootForth
|
||||
@ -89,13 +98,13 @@ CFLAGS+= -I${.CURDIR}/../../ofw/libofw
|
||||
LIBSTAND= ${.OBJDIR}/../../libstand32/libstand.a
|
||||
CFLAGS+= -I${.CURDIR}/../../../../lib/libstand/
|
||||
|
||||
DPADD= ${LIBFICL} ${LIBOFW} ${LIBSTAND}
|
||||
LDADD= ${LIBFICL} ${LIBOFW} ${LIBSTAND}
|
||||
DPADD= ${LIBFICL} ${LIBOFW} ${LIBFDT} ${LIBSTAND}
|
||||
LDADD= ${LIBFICL} ${LIBOFW} ${LIBFDT} ${LIBSTAND}
|
||||
|
||||
vers.c: ${.CURDIR}/../../common/newvers.sh ${.CURDIR}/version
|
||||
sh ${.CURDIR}/../../common/newvers.sh ${.CURDIR}/version ${NEWVERSWHAT}
|
||||
|
||||
loader.help: help.common help.ofw
|
||||
loader.help: help.common help.ofw ${.CURDIR}/../../fdt/help.fdt
|
||||
cat ${.ALLSRC} | \
|
||||
awk -f ${.CURDIR}/../../common/merge_help.awk > ${.TARGET}
|
||||
|
||||
|
||||
@ -34,11 +34,11 @@ __FBSDID("$FreeBSD$");
|
||||
#include <sys/reboot.h>
|
||||
#include <sys/linker.h>
|
||||
#include <sys/boot.h>
|
||||
#include <fdt_platform.h>
|
||||
|
||||
#include <machine/metadata.h>
|
||||
|
||||
#include "bootstrap.h"
|
||||
#include "libofw.h"
|
||||
|
||||
int
|
||||
md_getboothowto(char *kargs)
|
||||
@ -243,7 +243,7 @@ md_copymodules(vm_offset_t addr, int kern64)
|
||||
* - Module metadata are formatted and placed in kernel space.
|
||||
*/
|
||||
int
|
||||
md_load_dual(char *args, vm_offset_t *modulep, int kern64)
|
||||
md_load_dual(char *args, vm_offset_t *modulep, vm_offset_t *dtb, int kern64)
|
||||
{
|
||||
struct preloaded_file *kfp;
|
||||
struct preloaded_file *xp;
|
||||
@ -251,6 +251,7 @@ md_load_dual(char *args, vm_offset_t *modulep, int kern64)
|
||||
vm_offset_t kernend;
|
||||
vm_offset_t addr;
|
||||
vm_offset_t envp;
|
||||
vm_offset_t fdtp;
|
||||
vm_offset_t size;
|
||||
uint64_t scratch64;
|
||||
char *rootdevname;
|
||||
@ -286,6 +287,14 @@ md_load_dual(char *args, vm_offset_t *modulep, int kern64)
|
||||
/* pad to a page boundary */
|
||||
addr = roundup(addr, PAGE_SIZE);
|
||||
|
||||
/* Copy out FDT */
|
||||
*dtb = fdtp = 0;
|
||||
if (getenv("usefdt") != NULL) {
|
||||
size = fdt_copy(addr);
|
||||
*dtb = fdtp = addr;
|
||||
addr = roundup(addr + size, PAGE_SIZE);
|
||||
}
|
||||
|
||||
kernend = 0;
|
||||
kfp = file_findfile(NULL, kern64 ? "elf64 kernel" : "elf32 kernel");
|
||||
if (kfp == NULL)
|
||||
@ -296,10 +305,16 @@ md_load_dual(char *args, vm_offset_t *modulep, int kern64)
|
||||
if (kern64) {
|
||||
scratch64 = envp;
|
||||
file_addmetadata(kfp, MODINFOMD_ENVP, sizeof scratch64, &scratch64);
|
||||
if (fdtp != 0) {
|
||||
scratch64 = fdtp;
|
||||
file_addmetadata(kfp, MODINFOMD_DTBP, sizeof scratch64, &scratch64);
|
||||
}
|
||||
scratch64 = kernend;
|
||||
file_addmetadata(kfp, MODINFOMD_KERNEND, sizeof scratch64, &scratch64);
|
||||
} else {
|
||||
file_addmetadata(kfp, MODINFOMD_ENVP, sizeof envp, &envp);
|
||||
if (fdtp != 0)
|
||||
file_addmetadata(kfp, MODINFOMD_DTBP, sizeof fdtp, &fdtp);
|
||||
file_addmetadata(kfp, MODINFOMD_KERNEND, sizeof kernend, &kernend);
|
||||
}
|
||||
|
||||
@ -321,14 +336,14 @@ md_load_dual(char *args, vm_offset_t *modulep, int kern64)
|
||||
}
|
||||
|
||||
int
|
||||
md_load(char *args, vm_offset_t *modulep)
|
||||
md_load(char *args, vm_offset_t *modulep, vm_offset_t *dtb)
|
||||
{
|
||||
return (md_load_dual(args, modulep, 0));
|
||||
return (md_load_dual(args, modulep, dtb, 0));
|
||||
}
|
||||
|
||||
int
|
||||
md_load64(char *args, vm_offset_t *modulep)
|
||||
md_load64(char *args, vm_offset_t *modulep, vm_offset_t *dtb)
|
||||
{
|
||||
return (md_load_dual(args, modulep, 1));
|
||||
return (md_load_dual(args, modulep, dtb, 1));
|
||||
}
|
||||
|
||||
|
||||
202
sys/boot/powerpc/ofw/ofwfdt.c
Normal file
202
sys/boot/powerpc/ofw/ofwfdt.c
Normal file
@ -0,0 +1,202 @@
|
||||
/*-
|
||||
* Copyright (C) 2014-2015 Nathan Whitehorn
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
||||
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
||||
* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
||||
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
||||
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <stand.h>
|
||||
#include <sys/param.h>
|
||||
#include <fdt_platform.h>
|
||||
#include <openfirm.h>
|
||||
#include <libfdt.h>
|
||||
#include "bootstrap.h"
|
||||
|
||||
static int
|
||||
OF_hasprop(phandle_t node, const char *prop)
|
||||
{
|
||||
return (OF_getproplen(node, prop) > 0);
|
||||
}
|
||||
|
||||
static void
|
||||
add_node_to_fdt(void *buffer, phandle_t node, int fdt_offset)
|
||||
{
|
||||
int i, child_offset, error;
|
||||
char name[2048], *lastprop, *subname;
|
||||
void *propbuf;
|
||||
size_t proplen;
|
||||
|
||||
lastprop = NULL;
|
||||
while (OF_nextprop(node, lastprop, name) > 0) {
|
||||
proplen = OF_getproplen(node, name);
|
||||
propbuf = malloc(proplen);
|
||||
OF_getprop(node, name, propbuf, proplen);
|
||||
error = fdt_setprop(buffer, fdt_offset, name, propbuf, proplen);
|
||||
free(propbuf);
|
||||
lastprop = name;
|
||||
if (error)
|
||||
printf("Error %d adding property %s to "
|
||||
"node %d\n", error, name, fdt_offset);
|
||||
}
|
||||
|
||||
if (!OF_hasprop(node, "phandle") && !OF_hasprop(node, "linux,phandle")
|
||||
&& !OF_hasprop(node, "ibm,phandle"))
|
||||
fdt_setprop(buffer, fdt_offset, "phandle", &node, sizeof(node));
|
||||
|
||||
for (node = OF_child(node); node > 0; node = OF_peer(node)) {
|
||||
OF_package_to_path(node, name, sizeof(name));
|
||||
subname = strrchr(name, '/');
|
||||
subname++;
|
||||
child_offset = fdt_add_subnode(buffer, fdt_offset, subname);
|
||||
if (child_offset < 0) {
|
||||
printf("Error %d adding node %s (%s), skipping\n",
|
||||
child_offset, name, subname);
|
||||
continue;
|
||||
}
|
||||
|
||||
add_node_to_fdt(buffer, node, child_offset);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
ofwfdt_fixups(void *fdtp)
|
||||
{
|
||||
int offset, len, i;
|
||||
phandle_t node;
|
||||
ihandle_t rtas;
|
||||
const void *prop;
|
||||
|
||||
/*
|
||||
* Instantiate and add reservations for RTAS state if present
|
||||
*/
|
||||
|
||||
offset = fdt_path_offset(fdtp, "/rtas");
|
||||
if (offset > 0) {
|
||||
uint32_t base;
|
||||
void *rtasmem;
|
||||
char path[255];
|
||||
|
||||
node = OF_finddevice("/rtas");
|
||||
OF_package_to_path(node, path, sizeof(path));
|
||||
OF_getprop(node, "rtas-size", &len, sizeof(len));
|
||||
|
||||
/* Allocate memory */
|
||||
rtasmem = OF_claim(0, len, 4096);
|
||||
|
||||
/* Instantiate RTAS */
|
||||
rtas = OF_open(path);
|
||||
base = 0;
|
||||
OF_call_method("instantiate-rtas", rtas, 1, 1, (cell_t)rtas,
|
||||
&base);
|
||||
|
||||
/* Store info to FDT using Linux convention */
|
||||
base = cpu_to_fdt32(base);
|
||||
fdt_setprop(fdtp, offset, "linux,rtas-entry", &base,
|
||||
sizeof(base));
|
||||
base = cpu_to_fdt32((uint32_t)rtasmem);
|
||||
offset = fdt_path_offset(fdtp, "/rtas");
|
||||
fdt_setprop(fdtp, offset, "linux,rtas-base", &base,
|
||||
sizeof(base));
|
||||
|
||||
/* Mark RTAS private data area reserved */
|
||||
fdt_add_mem_rsv(fdtp, base, len);
|
||||
} else {
|
||||
/*
|
||||
* Remove /memory/available properties, which reflect long-gone OF
|
||||
* state. Note that this doesn't work if we need RTAS still, since
|
||||
* that's part of the firmware.
|
||||
*/
|
||||
|
||||
offset = fdt_path_offset(fdtp, "/memory@0");
|
||||
if (offset > 0)
|
||||
fdt_delprop(fdtp, offset, "available");
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
/*
|
||||
* Convert stored ihandles under /chosen to xref phandles
|
||||
*/
|
||||
offset = fdt_path_offset(fdtp, "/chosen");
|
||||
if (offset > 0) {
|
||||
const char *chosenprops[] = {"stdout", "stdin", "mmu", "cpu",
|
||||
NULL};
|
||||
const uint32_t *ihand;
|
||||
for (i = 0; chosenprops[i] != NULL; i++) {
|
||||
ihand = fdt_getprop(fdtp, offset, chosenprops[i], &len);
|
||||
if (ihand != NULL && len == sizeof(*ihand)) {
|
||||
node = OF_instance_to_package(
|
||||
fdt32_to_cpu(*ihand));
|
||||
if (OF_hasprop(node, "phandle"))
|
||||
OF_getprop(node, "phandle", &node,
|
||||
sizeof(node));
|
||||
else if (OF_hasprop(node, "linux,phandle"))
|
||||
OF_getprop(node, "linux,phandle", &node,
|
||||
sizeof(node));
|
||||
else if (OF_hasprop(node, "ibm,phandle"))
|
||||
OF_getprop(node, "ibm,phandle", &node,
|
||||
sizeof(node));
|
||||
node = cpu_to_fdt32(node);
|
||||
fdt_setprop(fdtp, offset, chosenprops[i], &node, sizeof(node));
|
||||
}
|
||||
|
||||
/* Refind node in case it moved */
|
||||
offset = fdt_path_offset(fdtp, "/chosen");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
fdt_platform_load_dtb(void)
|
||||
{
|
||||
void *buffer;
|
||||
size_t buflen = 409600;
|
||||
|
||||
buffer = malloc(buflen);
|
||||
fdt_create_empty_tree(buffer, buflen);
|
||||
add_node_to_fdt(buffer, OF_peer(0), fdt_path_offset(buffer, "/"));
|
||||
ofwfdt_fixups(buffer);
|
||||
fdt_pack(buffer);
|
||||
|
||||
fdt_load_dtb_addr(buffer);
|
||||
free(buffer);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
fdt_platform_fixups(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static int
|
||||
command_fdt(int argc, char *argv[])
|
||||
{
|
||||
|
||||
return (command_fdt_internal(argc, argv));
|
||||
}
|
||||
|
||||
COMMAND_SET(fdt, "fdt", "flattened device tree handling", command_fdt);
|
||||
|
||||
@ -276,7 +276,7 @@ md_copymodules(vm_offset_t addr)
|
||||
* - Module metadata are formatted and placed in kernel space.
|
||||
*/
|
||||
int
|
||||
md_load(char *args, vm_offset_t *modulep)
|
||||
md_load(char *args, vm_offset_t *modulep, vm_offset_t *dtbp)
|
||||
{
|
||||
struct preloaded_file *kfp;
|
||||
struct preloaded_file *xp;
|
||||
@ -289,6 +289,7 @@ md_load(char *args, vm_offset_t *modulep)
|
||||
int howto;
|
||||
|
||||
howto = md_getboothowto(args);
|
||||
*dtbp = 0;
|
||||
|
||||
/*
|
||||
* Allow the environment variable 'rootdev' to override the supplied device
|
||||
|
||||
@ -2889,11 +2889,6 @@ options SHMMNI=33
|
||||
# a single process at one time.
|
||||
options SHMSEG=9
|
||||
|
||||
# Compress user core dumps.
|
||||
options COMPRESS_USER_CORES
|
||||
# required to compress file output from kernel for COMPRESS_USER_CORES.
|
||||
device gzio
|
||||
|
||||
# Set the amount of time (in seconds) the system will wait before
|
||||
# rebooting automatically when a kernel panic occurs. If set to (-1),
|
||||
# the system will wait indefinitely until a key is pressed on the
|
||||
@ -2983,3 +2978,7 @@ options RANDOM_DEBUG # Debugging messages
|
||||
|
||||
# Module to enable execution of application via emulators like QEMU
|
||||
options IMAGACT_BINMISC
|
||||
|
||||
# zlib I/O stream support
|
||||
# This enables support for compressed core dumps.
|
||||
options GZIO
|
||||
|
||||
@ -3140,6 +3140,7 @@ kern/uipc_debug.c optional ddb
|
||||
kern/uipc_domain.c standard
|
||||
kern/uipc_mbuf.c standard
|
||||
kern/uipc_mbuf2.c standard
|
||||
kern/uipc_mbufhash.c standard
|
||||
kern/uipc_mqueue.c optional p1003_1b_mqueue
|
||||
kern/uipc_sem.c optional p1003_1b_semaphores
|
||||
kern/uipc_shm.c standard
|
||||
@ -3857,9 +3858,6 @@ ofed/drivers/net/mlx4/sys_tune.c optional mlx4ib | mlxen \
|
||||
ofed/drivers/net/mlx4/en_cq.c optional mlxen \
|
||||
no-depend obj-prefix "mlx4_" \
|
||||
compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
|
||||
ofed/drivers/net/mlx4/utils.c optional mlxen \
|
||||
no-depend obj-prefix "mlx4_" \
|
||||
compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
|
||||
ofed/drivers/net/mlx4/en_main.c optional mlxen \
|
||||
no-depend obj-prefix "mlx4_" \
|
||||
compile-with "${OFED_C_NOIMP} -I$S/ofed/drivers/net/mlx4/"
|
||||
|
||||
@ -87,13 +87,13 @@ COMPAT_FREEBSD9 opt_compat.h
|
||||
COMPAT_FREEBSD10 opt_compat.h
|
||||
COMPAT_LINUXAPI opt_compat.h
|
||||
COMPILING_LINT opt_global.h
|
||||
COMPRESS_USER_CORES opt_core.h
|
||||
CY_PCI_FASTINTR
|
||||
DEADLKRES opt_watchdog.h
|
||||
DIRECTIO
|
||||
FILEMON opt_dontuse.h
|
||||
FFCLOCK
|
||||
FULL_PREEMPTION opt_sched.h
|
||||
GZIO opt_gzio.h
|
||||
IMAGACT_BINMISC opt_dontuse.h
|
||||
IPI_PREEMPTION opt_sched.h
|
||||
GEOM_AES opt_geom.h
|
||||
|
||||
@ -1637,6 +1637,7 @@ bge_setmulti(struct bge_softc *sc)
|
||||
if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
|
||||
for (i = 0; i < 4; i++)
|
||||
CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
|
||||
free(mta, M_DEVBUF);
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
@ -52,7 +52,6 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
#include <net/ethernet.h>
|
||||
#include <net/if.h>
|
||||
#include <net/if_var.h>
|
||||
#include <net/if_arp.h>
|
||||
#include <net/if_dl.h>
|
||||
#include <net/if_media.h>
|
||||
@ -98,7 +97,7 @@ __FBSDID("$FreeBSD$");
|
||||
CSUM_TCP_IPV6 | CSUM_UDP_IPV6)
|
||||
|
||||
struct cgem_softc {
|
||||
struct ifnet *ifp;
|
||||
if_t ifp;
|
||||
struct mtx sc_mtx;
|
||||
device_t dev;
|
||||
device_t miibus;
|
||||
@ -298,9 +297,10 @@ cgem_mac_hash(u_char eaddr[])
|
||||
static void
|
||||
cgem_rx_filter(struct cgem_softc *sc)
|
||||
{
|
||||
struct ifnet *ifp = sc->ifp;
|
||||
struct ifmultiaddr *ifma;
|
||||
int index;
|
||||
if_t ifp = sc->ifp;
|
||||
u_char *mta;
|
||||
|
||||
int index, i, mcnt;
|
||||
uint32_t hash_hi, hash_lo;
|
||||
uint32_t net_cfg;
|
||||
|
||||
@ -313,28 +313,34 @@ cgem_rx_filter(struct cgem_softc *sc)
|
||||
CGEM_NET_CFG_NO_BCAST |
|
||||
CGEM_NET_CFG_COPY_ALL);
|
||||
|
||||
if ((ifp->if_flags & IFF_PROMISC) != 0)
|
||||
if ((if_getflags(ifp) & IFF_PROMISC) != 0)
|
||||
net_cfg |= CGEM_NET_CFG_COPY_ALL;
|
||||
else {
|
||||
if ((ifp->if_flags & IFF_BROADCAST) == 0)
|
||||
if ((if_getflags(ifp) & IFF_BROADCAST) == 0)
|
||||
net_cfg |= CGEM_NET_CFG_NO_BCAST;
|
||||
if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
|
||||
if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
|
||||
hash_hi = 0xffffffff;
|
||||
hash_lo = 0xffffffff;
|
||||
} else {
|
||||
if_maddr_rlock(ifp);
|
||||
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
||||
if (ifma->ifma_addr->sa_family != AF_LINK)
|
||||
continue;
|
||||
mcnt = if_multiaddr_count(ifp, -1);
|
||||
mta = malloc(ETHER_ADDR_LEN * mcnt, M_DEVBUF,
|
||||
M_NOWAIT);
|
||||
if (mta == NULL) {
|
||||
device_printf(sc->dev,
|
||||
"failed to allocate temp mcast list\n");
|
||||
return;
|
||||
}
|
||||
if_multiaddr_array(ifp, mta, &mcnt, mcnt);
|
||||
for (i = 0; i < mcnt; i++) {
|
||||
index = cgem_mac_hash(
|
||||
LLADDR((struct sockaddr_dl *)
|
||||
ifma->ifma_addr));
|
||||
(mta + (i * ETHER_ADDR_LEN))));
|
||||
if (index > 31)
|
||||
hash_hi |= (1<<(index-32));
|
||||
hash_hi |= (1 << (index - 32));
|
||||
else
|
||||
hash_lo |= (1<<index);
|
||||
hash_lo |= (1 << index);
|
||||
}
|
||||
if_maddr_runlock(ifp);
|
||||
free(mta, M_DEVBUF);
|
||||
}
|
||||
|
||||
if (hash_hi != 0 || hash_lo != 0)
|
||||
@ -418,10 +424,7 @@ cgem_setup_descs(struct cgem_softc *sc)
|
||||
sc->rxring[i].addr = CGEM_RXDESC_OWN;
|
||||
sc->rxring[i].ctl = 0;
|
||||
sc->rxring_m[i] = NULL;
|
||||
err = bus_dmamap_create(sc->mbuf_dma_tag, 0,
|
||||
&sc->rxring_m_dmamap[i]);
|
||||
if (err)
|
||||
return (err);
|
||||
sc->rxring_m_dmamap[i] = NULL;
|
||||
}
|
||||
sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP;
|
||||
|
||||
@ -451,10 +454,7 @@ cgem_setup_descs(struct cgem_softc *sc)
|
||||
sc->txring[i].addr = 0;
|
||||
sc->txring[i].ctl = CGEM_TXDESC_USED;
|
||||
sc->txring_m[i] = NULL;
|
||||
err = bus_dmamap_create(sc->mbuf_dma_tag, 0,
|
||||
&sc->txring_m_dmamap[i]);
|
||||
if (err)
|
||||
return (err);
|
||||
sc->txring_m_dmamap[i] = NULL;
|
||||
}
|
||||
sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP;
|
||||
|
||||
@ -486,10 +486,19 @@ cgem_fill_rqueue(struct cgem_softc *sc)
|
||||
m->m_pkthdr.rcvif = sc->ifp;
|
||||
|
||||
/* Load map and plug in physical address. */
|
||||
if (bus_dmamap_create(sc->mbuf_dma_tag, 0,
|
||||
&sc->rxring_m_dmamap[sc->rxring_hd_ptr])) {
|
||||
sc->rxdmamapfails++;
|
||||
m_free(m);
|
||||
break;
|
||||
}
|
||||
if (bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
|
||||
sc->rxring_m_dmamap[sc->rxring_hd_ptr], m,
|
||||
segs, &nsegs, BUS_DMA_NOWAIT)) {
|
||||
sc->rxdmamapfails++;
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
sc->rxring_m_dmamap[sc->rxring_hd_ptr]);
|
||||
sc->rxring_m_dmamap[sc->rxring_hd_ptr] = NULL;
|
||||
m_free(m);
|
||||
break;
|
||||
}
|
||||
@ -517,7 +526,7 @@ cgem_fill_rqueue(struct cgem_softc *sc)
|
||||
static void
|
||||
cgem_recv(struct cgem_softc *sc)
|
||||
{
|
||||
struct ifnet *ifp = sc->ifp;
|
||||
if_t ifp = sc->ifp;
|
||||
struct mbuf *m, *m_hd, **m_tl;
|
||||
uint32_t ctl;
|
||||
|
||||
@ -540,9 +549,12 @@ cgem_recv(struct cgem_softc *sc)
|
||||
sc->rxring_m_dmamap[sc->rxring_tl_ptr],
|
||||
BUS_DMASYNC_POSTREAD);
|
||||
|
||||
/* Unload dmamap. */
|
||||
/* Unload and destroy dmamap. */
|
||||
bus_dmamap_unload(sc->mbuf_dma_tag,
|
||||
sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
|
||||
sc->rxring_m_dmamap[sc->rxring_tl_ptr] = NULL;
|
||||
|
||||
/* Increment tail pointer. */
|
||||
if (++sc->rxring_tl_ptr == CGEM_NUM_RX_DESCS)
|
||||
@ -571,7 +583,7 @@ cgem_recv(struct cgem_softc *sc)
|
||||
/* Are we using hardware checksumming? Check the
|
||||
* status in the receive descriptor.
|
||||
*/
|
||||
if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) {
|
||||
if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
|
||||
/* TCP or UDP checks out, IP checks out too. */
|
||||
if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
|
||||
CGEM_RXDESC_CKSUM_STAT_TCP_GOOD ||
|
||||
@ -605,7 +617,7 @@ cgem_recv(struct cgem_softc *sc)
|
||||
m_hd = m_hd->m_next;
|
||||
m->m_next = NULL;
|
||||
if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
|
||||
(*ifp->if_input)(ifp, m);
|
||||
if_input(ifp, m);
|
||||
}
|
||||
CGEM_LOCK(sc);
|
||||
}
|
||||
@ -624,14 +636,17 @@ cgem_clean_tx(struct cgem_softc *sc)
|
||||
((ctl = sc->txring[sc->txring_tl_ptr].ctl) &
|
||||
CGEM_TXDESC_USED) != 0) {
|
||||
|
||||
/* Sync cache. nop? */
|
||||
/* Sync cache. */
|
||||
bus_dmamap_sync(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[sc->txring_tl_ptr],
|
||||
BUS_DMASYNC_POSTWRITE);
|
||||
|
||||
/* Unload DMA map. */
|
||||
/* Unload and destroy DMA map. */
|
||||
bus_dmamap_unload(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[sc->txring_tl_ptr]);
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[sc->txring_tl_ptr]);
|
||||
sc->txring_m_dmamap[sc->txring_tl_ptr] = NULL;
|
||||
|
||||
/* Free up the mbuf. */
|
||||
m = sc->txring_m[sc->txring_tl_ptr];
|
||||
@ -674,15 +689,15 @@ cgem_clean_tx(struct cgem_softc *sc)
|
||||
sc->txring_tl_ptr++;
|
||||
sc->txring_queued--;
|
||||
|
||||
sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
||||
if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE);
|
||||
}
|
||||
}
|
||||
|
||||
/* Start transmits. */
|
||||
static void
|
||||
cgem_start_locked(struct ifnet *ifp)
|
||||
cgem_start_locked(if_t ifp)
|
||||
{
|
||||
struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc;
|
||||
struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
|
||||
struct mbuf *m;
|
||||
bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
|
||||
uint32_t ctl;
|
||||
@ -690,7 +705,7 @@ cgem_start_locked(struct ifnet *ifp)
|
||||
|
||||
CGEM_ASSERT_LOCKED(sc);
|
||||
|
||||
if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0)
|
||||
if ((if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0)
|
||||
return;
|
||||
|
||||
for (;;) {
|
||||
@ -704,18 +719,24 @@ cgem_start_locked(struct ifnet *ifp)
|
||||
/* Still no room? */
|
||||
if (sc->txring_queued >=
|
||||
CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) {
|
||||
ifp->if_drv_flags |= IFF_DRV_OACTIVE;
|
||||
if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
|
||||
sc->txfull++;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Grab next transmit packet. */
|
||||
IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
|
||||
m = if_dequeue(ifp);
|
||||
if (m == NULL)
|
||||
break;
|
||||
|
||||
/* Load DMA map. */
|
||||
/* Create and load DMA map. */
|
||||
if (bus_dmamap_create(sc->mbuf_dma_tag, 0,
|
||||
&sc->txring_m_dmamap[sc->txring_hd_ptr])) {
|
||||
m_freem(m);
|
||||
sc->txdmamapfails++;
|
||||
continue;
|
||||
}
|
||||
err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[sc->txring_hd_ptr],
|
||||
m, segs, &nsegs, BUS_DMA_NOWAIT);
|
||||
@ -726,6 +747,9 @@ cgem_start_locked(struct ifnet *ifp)
|
||||
if (m2 == NULL) {
|
||||
sc->txdefragfails++;
|
||||
m_freem(m);
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[sc->txring_hd_ptr]);
|
||||
sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL;
|
||||
continue;
|
||||
}
|
||||
m = m2;
|
||||
@ -737,6 +761,9 @@ cgem_start_locked(struct ifnet *ifp)
|
||||
if (err) {
|
||||
/* Give up. */
|
||||
m_freem(m);
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[sc->txring_hd_ptr]);
|
||||
sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL;
|
||||
sc->txdmamapfails++;
|
||||
continue;
|
||||
}
|
||||
@ -788,9 +815,9 @@ cgem_start_locked(struct ifnet *ifp)
|
||||
}
|
||||
|
||||
static void
|
||||
cgem_start(struct ifnet *ifp)
|
||||
cgem_start(if_t ifp)
|
||||
{
|
||||
struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc;
|
||||
struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
|
||||
|
||||
CGEM_LOCK(sc);
|
||||
cgem_start_locked(ifp);
|
||||
@ -902,11 +929,12 @@ static void
|
||||
cgem_intr(void *arg)
|
||||
{
|
||||
struct cgem_softc *sc = (struct cgem_softc *)arg;
|
||||
if_t ifp = sc->ifp;
|
||||
uint32_t istatus;
|
||||
|
||||
CGEM_LOCK(sc);
|
||||
|
||||
if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
|
||||
if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
|
||||
CGEM_UNLOCK(sc);
|
||||
return;
|
||||
}
|
||||
@ -945,8 +973,8 @@ cgem_intr(void *arg)
|
||||
}
|
||||
|
||||
/* Restart transmitter if needed. */
|
||||
if (!IFQ_DRV_IS_EMPTY(&sc->ifp->if_snd))
|
||||
cgem_start_locked(sc->ifp);
|
||||
if (!if_sendq_empty(ifp))
|
||||
cgem_start_locked(ifp);
|
||||
|
||||
CGEM_UNLOCK(sc);
|
||||
}
|
||||
@ -982,9 +1010,10 @@ cgem_reset(struct cgem_softc *sc)
|
||||
static void
|
||||
cgem_config(struct cgem_softc *sc)
|
||||
{
|
||||
if_t ifp = sc->ifp;
|
||||
uint32_t net_cfg;
|
||||
uint32_t dma_cfg;
|
||||
u_char *eaddr = IF_LLADDR(sc->ifp);
|
||||
u_char *eaddr = if_getlladdr(ifp);
|
||||
|
||||
CGEM_ASSERT_LOCKED(sc);
|
||||
|
||||
@ -999,7 +1028,7 @@ cgem_config(struct cgem_softc *sc)
|
||||
CGEM_NET_CFG_SPEED100;
|
||||
|
||||
/* Enable receive checksum offloading? */
|
||||
if ((sc->ifp->if_capenable & IFCAP_RXCSUM) != 0)
|
||||
if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
|
||||
net_cfg |= CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
|
||||
|
||||
WR4(sc, CGEM_NET_CFG, net_cfg);
|
||||
@ -1012,7 +1041,7 @@ cgem_config(struct cgem_softc *sc)
|
||||
CGEM_DMA_CFG_DISC_WHEN_NO_AHB;
|
||||
|
||||
/* Enable transmit checksum offloading? */
|
||||
if ((sc->ifp->if_capenable & IFCAP_TXCSUM) != 0)
|
||||
if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
|
||||
dma_cfg |= CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN;
|
||||
|
||||
WR4(sc, CGEM_DMA_CFG, dma_cfg);
|
||||
@ -1045,14 +1074,13 @@ cgem_init_locked(struct cgem_softc *sc)
|
||||
|
||||
CGEM_ASSERT_LOCKED(sc);
|
||||
|
||||
if ((sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
|
||||
if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0)
|
||||
return;
|
||||
|
||||
cgem_config(sc);
|
||||
cgem_fill_rqueue(sc);
|
||||
|
||||
sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
|
||||
sc->ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
|
||||
if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
|
||||
|
||||
mii = device_get_softc(sc->miibus);
|
||||
mii_mediachg(mii);
|
||||
@ -1088,8 +1116,12 @@ cgem_stop(struct cgem_softc *sc)
|
||||
sc->txring[i].ctl = CGEM_TXDESC_USED;
|
||||
sc->txring[i].addr = 0;
|
||||
if (sc->txring_m[i]) {
|
||||
/* Unload and destroy dmamap. */
|
||||
bus_dmamap_unload(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[i]);
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
sc->txring_m_dmamap[i]);
|
||||
sc->txring_m_dmamap[i] = NULL;
|
||||
m_freem(sc->txring_m[i]);
|
||||
sc->txring_m[i] = NULL;
|
||||
}
|
||||
@ -1105,9 +1137,12 @@ cgem_stop(struct cgem_softc *sc)
|
||||
sc->rxring[i].addr = CGEM_RXDESC_OWN;
|
||||
sc->rxring[i].ctl = 0;
|
||||
if (sc->rxring_m[i]) {
|
||||
/* Unload dmamap. */
|
||||
/* Unload and destroy dmamap. */
|
||||
bus_dmamap_unload(sc->mbuf_dma_tag,
|
||||
sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
|
||||
sc->rxring_m_dmamap[i]);
|
||||
bus_dmamap_destroy(sc->mbuf_dma_tag,
|
||||
sc->rxring_m_dmamap[i]);
|
||||
sc->rxring_m_dmamap[i] = NULL;
|
||||
|
||||
m_freem(sc->rxring_m[i]);
|
||||
sc->rxring_m[i] = NULL;
|
||||
@ -1125,9 +1160,9 @@ cgem_stop(struct cgem_softc *sc)
|
||||
|
||||
|
||||
static int
|
||||
cgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
||||
cgem_ioctl(if_t ifp, u_long cmd, caddr_t data)
|
||||
{
|
||||
struct cgem_softc *sc = ifp->if_softc;
|
||||
struct cgem_softc *sc = if_getsoftc(ifp);
|
||||
struct ifreq *ifr = (struct ifreq *)data;
|
||||
struct mii_data *mii;
|
||||
int error = 0, mask;
|
||||
@ -1135,27 +1170,27 @@ cgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
||||
switch (cmd) {
|
||||
case SIOCSIFFLAGS:
|
||||
CGEM_LOCK(sc);
|
||||
if ((ifp->if_flags & IFF_UP) != 0) {
|
||||
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
|
||||
if (((ifp->if_flags ^ sc->if_old_flags) &
|
||||
if ((if_getflags(ifp) & IFF_UP) != 0) {
|
||||
if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
|
||||
if (((if_getflags(ifp) ^ sc->if_old_flags) &
|
||||
(IFF_PROMISC | IFF_ALLMULTI)) != 0) {
|
||||
cgem_rx_filter(sc);
|
||||
}
|
||||
} else {
|
||||
cgem_init_locked(sc);
|
||||
}
|
||||
} else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
|
||||
ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
|
||||
} else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
|
||||
if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
|
||||
cgem_stop(sc);
|
||||
}
|
||||
sc->if_old_flags = ifp->if_flags;
|
||||
sc->if_old_flags = if_getflags(ifp);
|
||||
CGEM_UNLOCK(sc);
|
||||
break;
|
||||
|
||||
case SIOCADDMULTI:
|
||||
case SIOCDELMULTI:
|
||||
/* Set up multi-cast filters. */
|
||||
if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
|
||||
if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
|
||||
CGEM_LOCK(sc);
|
||||
cgem_rx_filter(sc);
|
||||
CGEM_UNLOCK(sc);
|
||||
@ -1170,23 +1205,23 @@ cgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
||||
|
||||
case SIOCSIFCAP:
|
||||
CGEM_LOCK(sc);
|
||||
mask = ifp->if_capenable ^ ifr->ifr_reqcap;
|
||||
mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
|
||||
|
||||
if ((mask & IFCAP_TXCSUM) != 0) {
|
||||
if ((ifr->ifr_reqcap & IFCAP_TXCSUM) != 0) {
|
||||
/* Turn on TX checksumming. */
|
||||
ifp->if_capenable |= (IFCAP_TXCSUM |
|
||||
IFCAP_TXCSUM_IPV6);
|
||||
ifp->if_hwassist |= CGEM_CKSUM_ASSIST;
|
||||
if_setcapenablebit(ifp, IFCAP_TXCSUM |
|
||||
IFCAP_TXCSUM_IPV6, 0);
|
||||
if_sethwassistbits(ifp, CGEM_CKSUM_ASSIST, 0);
|
||||
|
||||
WR4(sc, CGEM_DMA_CFG,
|
||||
RD4(sc, CGEM_DMA_CFG) |
|
||||
CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN);
|
||||
} else {
|
||||
/* Turn off TX checksumming. */
|
||||
ifp->if_capenable &= ~(IFCAP_TXCSUM |
|
||||
IFCAP_TXCSUM_IPV6);
|
||||
ifp->if_hwassist &= ~CGEM_CKSUM_ASSIST;
|
||||
if_setcapenablebit(ifp, 0, IFCAP_TXCSUM |
|
||||
IFCAP_TXCSUM_IPV6);
|
||||
if_sethwassistbits(ifp, 0, CGEM_CKSUM_ASSIST);
|
||||
|
||||
WR4(sc, CGEM_DMA_CFG,
|
||||
RD4(sc, CGEM_DMA_CFG) &
|
||||
@ -1196,25 +1231,25 @@ cgem_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
|
||||
if ((mask & IFCAP_RXCSUM) != 0) {
|
||||
if ((ifr->ifr_reqcap & IFCAP_RXCSUM) != 0) {
|
||||
/* Turn on RX checksumming. */
|
||||
ifp->if_capenable |= (IFCAP_RXCSUM |
|
||||
IFCAP_RXCSUM_IPV6);
|
||||
if_setcapenablebit(ifp, IFCAP_RXCSUM |
|
||||
IFCAP_RXCSUM_IPV6, 0);
|
||||
WR4(sc, CGEM_NET_CFG,
|
||||
RD4(sc, CGEM_NET_CFG) |
|
||||
CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
|
||||
} else {
|
||||
/* Turn off RX checksumming. */
|
||||
ifp->if_capenable &= ~(IFCAP_RXCSUM |
|
||||
IFCAP_RXCSUM_IPV6);
|
||||
if_setcapenablebit(ifp, 0, IFCAP_RXCSUM |
|
||||
IFCAP_RXCSUM_IPV6);
|
||||
WR4(sc, CGEM_NET_CFG,
|
||||
RD4(sc, CGEM_NET_CFG) &
|
||||
~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
|
||||
}
|
||||
}
|
||||
if ((ifp->if_capenable & (IFCAP_RXCSUM | IFCAP_TXCSUM)) ==
|
||||
if ((if_getcapenable(ifp) & (IFCAP_RXCSUM | IFCAP_TXCSUM)) ==
|
||||
(IFCAP_RXCSUM | IFCAP_TXCSUM))
|
||||
ifp->if_capenable |= IFCAP_VLAN_HWCSUM;
|
||||
if_setcapenablebit(ifp, IFCAP_VLAN_HWCSUM, 0);
|
||||
else
|
||||
ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM;
|
||||
if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM);
|
||||
|
||||
CGEM_UNLOCK(sc);
|
||||
break;
|
||||
@ -1238,16 +1273,16 @@ cgem_child_detached(device_t dev, device_t child)
|
||||
}
|
||||
|
||||
static int
|
||||
cgem_ifmedia_upd(struct ifnet *ifp)
|
||||
cgem_ifmedia_upd(if_t ifp)
|
||||
{
|
||||
struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc;
|
||||
struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
|
||||
struct mii_data *mii;
|
||||
struct mii_softc *miisc;
|
||||
int error = 0;
|
||||
|
||||
mii = device_get_softc(sc->miibus);
|
||||
CGEM_LOCK(sc);
|
||||
if ((ifp->if_flags & IFF_UP) != 0) {
|
||||
if ((if_getflags(ifp) & IFF_UP) != 0) {
|
||||
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
|
||||
PHY_RESET(miisc);
|
||||
error = mii_mediachg(mii);
|
||||
@ -1258,9 +1293,9 @@ cgem_ifmedia_upd(struct ifnet *ifp)
|
||||
}
|
||||
|
||||
static void
|
||||
cgem_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
|
||||
cgem_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
|
||||
{
|
||||
struct cgem_softc *sc = (struct cgem_softc *) ifp->if_softc;
|
||||
struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
|
||||
struct mii_data *mii;
|
||||
|
||||
mii = device_get_softc(sc->miibus);
|
||||
@ -1606,7 +1641,7 @@ static int
|
||||
cgem_attach(device_t dev)
|
||||
{
|
||||
struct cgem_softc *sc = device_get_softc(dev);
|
||||
struct ifnet *ifp = NULL;
|
||||
if_t ifp = NULL;
|
||||
phandle_t node;
|
||||
pcell_t cell;
|
||||
int rid, err;
|
||||
@ -1647,23 +1682,23 @@ cgem_attach(device_t dev)
|
||||
cgem_detach(dev);
|
||||
return (ENOMEM);
|
||||
}
|
||||
ifp->if_softc = sc;
|
||||
if_setsoftc(ifp, sc);
|
||||
if_initname(ifp, IF_CGEM_NAME, device_get_unit(dev));
|
||||
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
||||
ifp->if_start = cgem_start;
|
||||
ifp->if_ioctl = cgem_ioctl;
|
||||
ifp->if_init = cgem_init;
|
||||
ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
|
||||
IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM;
|
||||
/* Disable hardware checksumming by default. */
|
||||
ifp->if_hwassist = 0;
|
||||
ifp->if_capenable = ifp->if_capabilities &
|
||||
~(IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWCSUM);
|
||||
ifp->if_snd.ifq_drv_maxlen = CGEM_NUM_TX_DESCS;
|
||||
IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
|
||||
IFQ_SET_READY(&ifp->if_snd);
|
||||
if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
|
||||
if_setinitfn(ifp, cgem_init);
|
||||
if_setioctlfn(ifp, cgem_ioctl);
|
||||
if_setstartfn(ifp, cgem_start);
|
||||
if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
|
||||
IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM, 0);
|
||||
if_setsendqlen(ifp, CGEM_NUM_TX_DESCS);
|
||||
if_setsendqready(ifp);
|
||||
|
||||
sc->if_old_flags = ifp->if_flags;
|
||||
/* Disable hardware checksumming by default. */
|
||||
if_sethwassist(ifp, 0);
|
||||
if_setcapenable(ifp, if_getcapabilities(ifp) &
|
||||
~(IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWCSUM));
|
||||
|
||||
sc->if_old_flags = if_getflags(ifp);
|
||||
sc->rxbufs = DEFAULT_NUM_RX_BUFS;
|
||||
sc->rxhangwar = 1;
|
||||
|
||||
@ -1726,7 +1761,7 @@ cgem_detach(device_t dev)
|
||||
cgem_stop(sc);
|
||||
CGEM_UNLOCK(sc);
|
||||
callout_drain(&sc->tick_ch);
|
||||
sc->ifp->if_flags &= ~IFF_UP;
|
||||
if_setflagbits(sc->ifp, 0, IFF_UP);
|
||||
ether_ifdetach(sc->ifp);
|
||||
}
|
||||
|
||||
@ -1752,7 +1787,8 @@ cgem_detach(device_t dev)
|
||||
/* Release DMA resources. */
|
||||
if (sc->rxring != NULL) {
|
||||
if (sc->rxring_physaddr != 0) {
|
||||
bus_dmamap_unload(sc->desc_dma_tag, sc->rxring_dma_map);
|
||||
bus_dmamap_unload(sc->desc_dma_tag,
|
||||
sc->rxring_dma_map);
|
||||
sc->rxring_physaddr = 0;
|
||||
}
|
||||
bus_dmamem_free(sc->desc_dma_tag, sc->rxring,
|
||||
@ -1767,7 +1803,8 @@ cgem_detach(device_t dev)
|
||||
}
|
||||
if (sc->txring != NULL) {
|
||||
if (sc->txring_physaddr != 0) {
|
||||
bus_dmamap_unload(sc->desc_dma_tag, sc->txring_dma_map);
|
||||
bus_dmamap_unload(sc->desc_dma_tag,
|
||||
sc->txring_dma_map);
|
||||
sc->txring_physaddr = 0;
|
||||
}
|
||||
bus_dmamem_free(sc->desc_dma_tag, sc->txring,
|
||||
|
||||
@ -65,6 +65,13 @@ __FBSDID("$FreeBSD$");
|
||||
#include "common/t4_tcb.h"
|
||||
#include "tom/t4_tom.h"
|
||||
|
||||
VNET_DECLARE(int, tcp_do_autorcvbuf);
|
||||
#define V_tcp_do_autorcvbuf VNET(tcp_do_autorcvbuf)
|
||||
VNET_DECLARE(int, tcp_autorcvbuf_inc);
|
||||
#define V_tcp_autorcvbuf_inc VNET(tcp_autorcvbuf_inc)
|
||||
VNET_DECLARE(int, tcp_autorcvbuf_max);
|
||||
#define V_tcp_autorcvbuf_max VNET(tcp_autorcvbuf_max)
|
||||
|
||||
#define PPOD_SZ(n) ((n) * sizeof(struct pagepod))
|
||||
#define PPOD_SIZE (PPOD_SZ(1))
|
||||
|
||||
@ -411,6 +418,21 @@ handle_ddp_data(struct toepcb *toep, __be32 ddp_report, __be32 rcv_nxt, int len)
|
||||
else
|
||||
discourage_ddp(toep);
|
||||
|
||||
/* receive buffer autosize */
|
||||
if (sb->sb_flags & SB_AUTOSIZE &&
|
||||
V_tcp_do_autorcvbuf &&
|
||||
sb->sb_hiwat < V_tcp_autorcvbuf_max &&
|
||||
len > (sbspace(sb) / 8 * 7)) {
|
||||
unsigned int hiwat = sb->sb_hiwat;
|
||||
unsigned int newsize = min(hiwat + V_tcp_autorcvbuf_inc,
|
||||
V_tcp_autorcvbuf_max);
|
||||
|
||||
if (!sbreserve_locked(sb, newsize, so, NULL))
|
||||
sb->sb_flags &= ~SB_AUTOSIZE;
|
||||
else
|
||||
toep->rx_credits += newsize - hiwat;
|
||||
}
|
||||
|
||||
KASSERT(toep->sb_cc >= sbused(sb),
|
||||
("%s: sb %p has more data (%d) than last time (%d).",
|
||||
__func__, sb, sbused(sb), toep->sb_cc));
|
||||
|
||||
@ -149,8 +149,10 @@ arswitch_probe(device_t dev)
|
||||
DPRINTF(dev, "chipname=%s, id=%08x\n", chipname, id);
|
||||
if (chipname != NULL) {
|
||||
snprintf(desc, sizeof(desc),
|
||||
"Atheros %s Ethernet Switch",
|
||||
chipname);
|
||||
"Atheros %s Ethernet Switch (ver %d rev %d)",
|
||||
chipname,
|
||||
sc->chip_ver,
|
||||
sc->chip_rev);
|
||||
device_set_desc_copy(dev, desc);
|
||||
return (BUS_PROBE_DEFAULT);
|
||||
}
|
||||
@ -177,9 +179,11 @@ arswitch_attach_phys(struct arswitch_softc *sc)
|
||||
err = mii_attach(sc->sc_dev, &sc->miibus[phy], sc->ifp[phy],
|
||||
arswitch_ifmedia_upd, arswitch_ifmedia_sts, \
|
||||
BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, 0);
|
||||
#if 0
|
||||
DPRINTF(sc->sc_dev, "%s attached to pseudo interface %s\n",
|
||||
device_get_nameunit(sc->miibus[phy]),
|
||||
sc->ifp[phy]->if_xname);
|
||||
#endif
|
||||
if (err != 0) {
|
||||
device_printf(sc->sc_dev,
|
||||
"attaching PHY %d failed\n",
|
||||
@ -299,12 +303,26 @@ arswitch_attach(device_t dev)
|
||||
sc->hal.arswitch_port_vlan_setup = ar8xxx_port_vlan_setup;
|
||||
sc->hal.arswitch_port_vlan_get = ar8xxx_port_vlan_get;
|
||||
sc->hal.arswitch_vlan_init_hw = ar8xxx_reset_vlans;
|
||||
|
||||
sc->hal.arswitch_vlan_getvgroup = ar8xxx_getvgroup;
|
||||
sc->hal.arswitch_vlan_setvgroup = ar8xxx_setvgroup;
|
||||
|
||||
sc->hal.arswitch_vlan_get_pvid = ar8xxx_get_pvid;
|
||||
sc->hal.arswitch_vlan_set_pvid = ar8xxx_set_pvid;
|
||||
|
||||
sc->hal.arswitch_get_dot1q_vlan = ar8xxx_get_dot1q_vlan;
|
||||
sc->hal.arswitch_set_dot1q_vlan = ar8xxx_set_dot1q_vlan;
|
||||
sc->hal.arswitch_flush_dot1q_vlan = ar8xxx_flush_dot1q_vlan;
|
||||
sc->hal.arswitch_purge_dot1q_vlan = ar8xxx_purge_dot1q_vlan;
|
||||
sc->hal.arswitch_get_port_vlan = ar8xxx_get_port_vlan;
|
||||
sc->hal.arswitch_set_port_vlan = ar8xxx_set_port_vlan;
|
||||
|
||||
sc->hal.arswitch_atu_flush = ar8xxx_atu_flush;
|
||||
|
||||
sc->hal.arswitch_phy_read = arswitch_readphy_internal;
|
||||
sc->hal.arswitch_phy_write = arswitch_writephy_internal;
|
||||
|
||||
|
||||
/*
|
||||
* Attach switch related functions
|
||||
*/
|
||||
@ -320,8 +338,10 @@ arswitch_attach(device_t dev)
|
||||
ar8316_attach(sc);
|
||||
else if (AR8X16_IS_SWITCH(sc, AR8327))
|
||||
ar8327_attach(sc);
|
||||
else
|
||||
else {
|
||||
DPRINTF(dev, "%s: unknown switch (%d)?\n", __func__, sc->sc_switchtype);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
/* Common defaults. */
|
||||
sc->info.es_nports = 5; /* XXX technically 6, but 6th not used */
|
||||
@ -348,14 +368,18 @@ arswitch_attach(device_t dev)
|
||||
sc->numphys = AR8X16_NUM_PHYS;
|
||||
|
||||
/* Reset the switch. */
|
||||
if (arswitch_reset(dev))
|
||||
if (arswitch_reset(dev)) {
|
||||
DPRINTF(dev, "%s: arswitch_reset: failed\n", __func__);
|
||||
return (ENXIO);
|
||||
}
|
||||
|
||||
err = sc->hal.arswitch_hw_setup(sc);
|
||||
DPRINTF(dev, "%s: hw_setup: err=%d\n", __func__, err);
|
||||
if (err != 0)
|
||||
return (err);
|
||||
|
||||
err = sc->hal.arswitch_hw_global_setup(sc);
|
||||
DPRINTF(dev, "%s: hw_global_setup: err=%d\n", __func__, err);
|
||||
if (err != 0)
|
||||
return (err);
|
||||
|
||||
@ -368,17 +392,20 @@ arswitch_attach(device_t dev)
|
||||
* Attach the PHYs and complete the bus enumeration.
|
||||
*/
|
||||
err = arswitch_attach_phys(sc);
|
||||
DPRINTF(dev, "%s: attach_phys: err=%d\n", __func__, err);
|
||||
if (err != 0)
|
||||
return (err);
|
||||
|
||||
/* Default to ingress filters off. */
|
||||
err = arswitch_set_vlan_mode(sc, 0);
|
||||
DPRINTF(dev, "%s: set_vlan_mode: err=%d\n", __func__, err);
|
||||
if (err != 0)
|
||||
return (err);
|
||||
|
||||
bus_generic_probe(dev);
|
||||
bus_enumerate_hinted_children(dev);
|
||||
err = bus_generic_attach(dev);
|
||||
DPRINTF(dev, "%s: bus_generic_attach: err=%d\n", __func__, err);
|
||||
if (err != 0)
|
||||
return (err);
|
||||
|
||||
@ -611,6 +638,15 @@ ar8xxx_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p)
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_is_cpuport(struct arswitch_softc *sc, int port)
|
||||
{
|
||||
|
||||
return ((port == AR8X16_PORT_CPU) ||
|
||||
((AR8X16_IS_SWITCH(sc, AR8327) &&
|
||||
port == AR8327_PORT_GMAC6)));
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_getport(device_t dev, etherswitch_port_t *p)
|
||||
{
|
||||
@ -620,7 +656,8 @@ arswitch_getport(device_t dev, etherswitch_port_t *p)
|
||||
int err;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (p->es_port < 0 || p->es_port > sc->numphys)
|
||||
/* XXX +1 is for AR8327; should make this configurable! */
|
||||
if (p->es_port < 0 || p->es_port > sc->info.es_nports)
|
||||
return (ENXIO);
|
||||
|
||||
err = sc->hal.arswitch_port_vlan_get(sc, p);
|
||||
@ -628,7 +665,7 @@ arswitch_getport(device_t dev, etherswitch_port_t *p)
|
||||
return (err);
|
||||
|
||||
mii = arswitch_miiforport(sc, p->es_port);
|
||||
if (p->es_port == AR8X16_PORT_CPU) {
|
||||
if (arswitch_is_cpuport(sc, p->es_port)) {
|
||||
/* fill in fixed values for CPU port */
|
||||
/* XXX is this valid in all cases? */
|
||||
p->es_flags |= ETHERSWITCH_PORT_CPU;
|
||||
@ -697,7 +734,7 @@ arswitch_setport(device_t dev, etherswitch_port_t *p)
|
||||
struct ifnet *ifp;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
if (p->es_port < 0 || p->es_port > sc->numphys)
|
||||
if (p->es_port < 0 || p->es_port > sc->info.es_nports)
|
||||
return (ENXIO);
|
||||
|
||||
/* Port flags. */
|
||||
@ -708,7 +745,7 @@ arswitch_setport(device_t dev, etherswitch_port_t *p)
|
||||
}
|
||||
|
||||
/* Do not allow media changes on CPU port. */
|
||||
if (p->es_port == AR8X16_PORT_CPU)
|
||||
if (arswitch_is_cpuport(sc, p->es_port))
|
||||
return (0);
|
||||
|
||||
mii = arswitch_miiforport(sc, p->es_port);
|
||||
@ -803,6 +840,22 @@ arswitch_setvgroup(device_t dev, etherswitch_vlangroup_t *e)
|
||||
return (sc->hal.arswitch_vlan_setvgroup(sc, e));
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_readphy(device_t dev, int phy, int reg)
|
||||
{
|
||||
struct arswitch_softc *sc = device_get_softc(dev);
|
||||
|
||||
return (sc->hal.arswitch_phy_read(dev, phy, reg));
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_writephy(device_t dev, int phy, int reg, int val)
|
||||
{
|
||||
struct arswitch_softc *sc = device_get_softc(dev);
|
||||
|
||||
return (sc->hal.arswitch_phy_write(dev, phy, reg, val));
|
||||
}
|
||||
|
||||
static device_method_t arswitch_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, arswitch_probe),
|
||||
|
||||
@ -57,6 +57,9 @@
|
||||
#include <dev/etherswitch/arswitch/arswitchreg.h>
|
||||
#include <dev/etherswitch/arswitch/arswitchvar.h>
|
||||
#include <dev/etherswitch/arswitch/arswitch_reg.h>
|
||||
#include <dev/etherswitch/arswitch/arswitch_phy.h>
|
||||
#include <dev/etherswitch/arswitch/arswitch_vlans.h>
|
||||
|
||||
#include <dev/etherswitch/arswitch/arswitch_8327.h>
|
||||
|
||||
#include "mdio_if.h"
|
||||
@ -290,7 +293,7 @@ ar8327_fetch_pdata_port(struct arswitch_softc *sc,
|
||||
sbuf, &val) == 0)
|
||||
pcfg->rxpause = val;
|
||||
|
||||
#if 0
|
||||
#if 1
|
||||
device_printf(sc->sc_dev,
|
||||
"%s: port %d: speed=%d, duplex=%d, txpause=%d, rxpause=%d\n",
|
||||
__func__,
|
||||
@ -562,6 +565,7 @@ ar8327_init_pdata(struct arswitch_softc *sc)
|
||||
/* SGMII config */
|
||||
bzero(&scfg, sizeof(scfg));
|
||||
if (ar8327_fetch_pdata_sgmii(sc, &scfg)) {
|
||||
device_printf(sc->sc_dev, "%s: SGMII cfg?\n", __func__);
|
||||
t = scfg.sgmii_ctrl;
|
||||
if (sc->chip_rev == 1)
|
||||
t |= AR8327_SGMII_CTRL_EN_PLL |
|
||||
@ -651,18 +655,23 @@ ar8327_hw_global_setup(struct arswitch_softc *sc)
|
||||
arswitch_writereg(sc->sc_dev, AR8327_REG_EEE_CTRL, t);
|
||||
|
||||
/* Set the right number of ports */
|
||||
sc->info.es_nports = 6;
|
||||
/* GMAC0 (CPU), GMAC1..5 (PHYs), GMAC6 (CPU) */
|
||||
sc->info.es_nports = 7;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Port setup.
|
||||
* Port setup. Called at attach time.
|
||||
*/
|
||||
static void
|
||||
ar8327_port_init(struct arswitch_softc *sc, int port)
|
||||
{
|
||||
uint32_t t;
|
||||
int ports;
|
||||
|
||||
/* For now, port can see all other ports */
|
||||
ports = 0x7f;
|
||||
|
||||
if (port == AR8X16_PORT_CPU)
|
||||
t = sc->ar8327.port0_status;
|
||||
@ -696,7 +705,7 @@ ar8327_port_init(struct arswitch_softc *sc, int port)
|
||||
t |= AR8X16_PORT_CTRL_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
|
||||
|
||||
/* So this allows traffic to any port except ourselves */
|
||||
t |= (0x7f & ~(1 << port));
|
||||
t |= (ports & ~(1 << port));
|
||||
arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port), t);
|
||||
}
|
||||
|
||||
@ -704,17 +713,43 @@ static int
|
||||
ar8327_port_vlan_setup(struct arswitch_softc *sc, etherswitch_port_t *p)
|
||||
{
|
||||
|
||||
/* XXX stub for now */
|
||||
device_printf(sc->sc_dev, "%s: called\n", __func__);
|
||||
/* Check: ADDTAG/STRIPTAG - exclusive */
|
||||
|
||||
ARSWITCH_LOCK(sc);
|
||||
|
||||
/* Set the PVID. */
|
||||
if (p->es_pvid != 0)
|
||||
sc->hal.arswitch_vlan_set_pvid(sc, p->es_port, p->es_pvid);
|
||||
|
||||
/*
|
||||
* DOUBLE_TAG
|
||||
* VLAN_MODE_ADD
|
||||
* VLAN_MODE_STRIP
|
||||
*/
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Get the port VLAN configuration.
|
||||
*/
|
||||
static int
|
||||
ar8327_port_vlan_get(struct arswitch_softc *sc, etherswitch_port_t *p)
|
||||
{
|
||||
|
||||
/* XXX stub for now */
|
||||
device_printf(sc->sc_dev, "%s: called\n", __func__);
|
||||
ARSWITCH_LOCK(sc);
|
||||
|
||||
/* Retrieve the PVID */
|
||||
sc->hal.arswitch_vlan_get_pvid(sc, p->es_port, &p->es_pvid);
|
||||
|
||||
/* Retrieve the current port configuration */
|
||||
/*
|
||||
* DOUBLE_TAG
|
||||
* VLAN_MODE_ADD
|
||||
* VLAN_MODE_STRIP
|
||||
*/
|
||||
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -723,6 +758,13 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
|
||||
{
|
||||
int i;
|
||||
uint32_t mode, t;
|
||||
int ports;
|
||||
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_NOTOWNED);
|
||||
ARSWITCH_LOCK(sc);
|
||||
|
||||
/* Clear the existing VLAN configuration */
|
||||
memset(sc->vid, 0, sizeof(sc->vid));
|
||||
|
||||
/*
|
||||
* Disable mirroring.
|
||||
@ -732,11 +774,25 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
|
||||
(0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
|
||||
|
||||
/*
|
||||
* For now, let's default to one portgroup, just so traffic
|
||||
* flows. All ports can see other ports.
|
||||
* XXX TODO: disable any Q-in-Q port configuration,
|
||||
* tagging, egress filters, etc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* For now, let's default to one portgroup, just so traffic
|
||||
* flows. All ports can see other ports. There are two CPU GMACs
|
||||
* (GMAC0, GMAC6), GMAC1..GMAC5 are external PHYs.
|
||||
*
|
||||
* (ETHERSWITCH_VLAN_PORT)
|
||||
*/
|
||||
ports = 0x7f;
|
||||
|
||||
for (i = 0; i < AR8327_NUM_PORTS; i++) {
|
||||
/* set pvid = 1; there's only one vlangroup */
|
||||
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT)
|
||||
sc->vid[i] = i | ETHERSWITCH_VID_VALID;
|
||||
|
||||
/* set pvid = 1; there's only one vlangroup to start with */
|
||||
t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
|
||||
t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
|
||||
arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(i), t);
|
||||
@ -749,7 +805,7 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
|
||||
arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN1(i), t);
|
||||
|
||||
/* Ports can see other ports */
|
||||
t = (0x7f & ~(1 << i)); /* all ports besides us */
|
||||
t = (ports & ~(1 << i)); /* all ports besides us */
|
||||
t |= AR8327_PORT_LOOKUP_LEARN;
|
||||
|
||||
/* in_port_only, forward */
|
||||
@ -769,36 +825,95 @@ ar8327_reset_vlans(struct arswitch_softc *sc)
|
||||
AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
|
||||
0);
|
||||
}
|
||||
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
}
|
||||
|
||||
static int
|
||||
ar8327_vlan_get_port(struct arswitch_softc *sc, uint32_t *ports, int vid)
|
||||
{
|
||||
int port;
|
||||
uint32_t reg;
|
||||
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
/* For port based vlans the vlanid is the same as the port index. */
|
||||
port = vid & ETHERSWITCH_VID_MASK;
|
||||
reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port));
|
||||
*ports = reg & 0x7f;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ar8327_vlan_set_port(struct arswitch_softc *sc, uint32_t ports, int vid)
|
||||
{
|
||||
int err, port;
|
||||
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
/* For port based vlans the vlanid is the same as the port index. */
|
||||
port = vid & ETHERSWITCH_VID_MASK;
|
||||
|
||||
err = arswitch_modifyreg(sc->sc_dev, AR8327_REG_PORT_LOOKUP(port),
|
||||
0x7f, /* vlan membership mask */
|
||||
(ports & 0x7f));
|
||||
|
||||
if (err)
|
||||
return (err);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ar8327_vlan_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
|
||||
{
|
||||
device_printf(sc->sc_dev, "%s: called\n", __func__);
|
||||
return (0);
|
||||
|
||||
/* XXX for now, no dot1q vlans */
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
|
||||
return (EINVAL);
|
||||
return (ar8xxx_getvgroup(sc, vg));
|
||||
}
|
||||
|
||||
static int
|
||||
ar8327_vlan_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
|
||||
{
|
||||
|
||||
device_printf(sc->sc_dev, "%s: called\n", __func__);
|
||||
return (0);
|
||||
/* XXX for now, no dot1q vlans */
|
||||
if (sc->vlan_mode == ETHERSWITCH_VLAN_DOT1Q)
|
||||
return (EINVAL);
|
||||
return (ar8xxx_setvgroup(sc, vg));
|
||||
}
|
||||
|
||||
static int
|
||||
ar8327_get_pvid(struct arswitch_softc *sc, int port, int *pvid)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
device_printf(sc->sc_dev, "%s: called\n", __func__);
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
|
||||
|
||||
/*
|
||||
* XXX for now, assuming it's CVID; likely very wrong!
|
||||
*/
|
||||
port = port & ETHERSWITCH_VID_MASK;
|
||||
reg = arswitch_readreg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port));
|
||||
reg = reg >> AR8327_PORT_VLAN0_DEF_CVID_S;
|
||||
reg = reg & 0xfff;
|
||||
|
||||
*pvid = reg;
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
ar8327_set_pvid(struct arswitch_softc *sc, int port, int pvid)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
/* Limit pvid to valid values */
|
||||
pvid &= 0x7f;
|
||||
|
||||
t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
|
||||
t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
|
||||
arswitch_writereg(sc->sc_dev, AR8327_REG_PORT_VLAN0(port), t);
|
||||
|
||||
device_printf(sc->sc_dev, "%s: called\n", __func__);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -832,17 +947,32 @@ ar8327_attach(struct arswitch_softc *sc)
|
||||
sc->hal.arswitch_hw_global_setup = ar8327_hw_global_setup;
|
||||
|
||||
sc->hal.arswitch_port_init = ar8327_port_init;
|
||||
|
||||
sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup;
|
||||
sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup;
|
||||
sc->hal.arswitch_port_vlan_setup = ar8327_port_vlan_setup;
|
||||
sc->hal.arswitch_port_vlan_get = ar8327_port_vlan_get;
|
||||
|
||||
sc->hal.arswitch_vlan_init_hw = ar8327_reset_vlans;
|
||||
sc->hal.arswitch_vlan_getvgroup = ar8327_vlan_getvgroup;
|
||||
sc->hal.arswitch_vlan_setvgroup = ar8327_vlan_setvgroup;
|
||||
sc->hal.arswitch_vlan_get_pvid = ar8327_get_pvid;
|
||||
sc->hal.arswitch_vlan_set_pvid = ar8327_set_pvid;
|
||||
|
||||
sc->hal.arswitch_get_port_vlan = ar8327_vlan_get_port;
|
||||
sc->hal.arswitch_set_port_vlan = ar8327_vlan_set_port;
|
||||
|
||||
sc->hal.arswitch_atu_flush = ar8327_atu_flush;
|
||||
|
||||
/*
|
||||
* Reading the PHY via the MDIO interface currently doesn't
|
||||
* work correctly.
|
||||
*
|
||||
* So for now, just go direct to the PHY registers themselves.
|
||||
* This has always worked on external devices, but not internal
|
||||
* devices (AR934x, AR724x, AR933x.)
|
||||
*/
|
||||
sc->hal.arswitch_phy_read = arswitch_readphy_external;
|
||||
sc->hal.arswitch_phy_write = arswitch_writephy_external;
|
||||
|
||||
/* Set the switch vlan capabilities. */
|
||||
sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q |
|
||||
ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG;
|
||||
|
||||
@ -67,11 +67,46 @@ static SYSCTL_NODE(_debug, OID_AUTO, arswitch, CTLFLAG_RD, 0, "arswitch");
|
||||
#endif
|
||||
|
||||
/*
|
||||
* access PHYs integrated into the switch chip through the switch's MDIO
|
||||
* Access PHYs integrated into the switch by going direct
|
||||
* to the PHY space itself, rather than through the switch
|
||||
* MDIO register.
|
||||
*/
|
||||
int
|
||||
arswitch_readphy_external(device_t dev, int phy, int reg)
|
||||
{
|
||||
int ret;
|
||||
struct arswitch_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
ARSWITCH_LOCK(sc);
|
||||
ret = (MDIO_READREG(device_get_parent(dev), phy, reg));
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_writephy_external(device_t dev, int phy, int reg, int data)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
ARSWITCH_LOCK(sc);
|
||||
(void) MDIO_WRITEREG(device_get_parent(dev), phy,
|
||||
reg, data);
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* Access PHYs integrated into the switch chip through the switch's MDIO
|
||||
* control register.
|
||||
*/
|
||||
int
|
||||
arswitch_readphy(device_t dev, int phy, int reg)
|
||||
arswitch_readphy_internal(device_t dev, int phy, int reg)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
uint32_t data = 0, ctrl;
|
||||
@ -105,8 +140,10 @@ arswitch_readphy(device_t dev, int phy, int reg)
|
||||
if ((ctrl & AR8X16_MDIO_CTRL_BUSY) == 0)
|
||||
break;
|
||||
}
|
||||
if (timeout < 0)
|
||||
if (timeout < 0) {
|
||||
DPRINTF(dev, "arswitch_readphy(): phy=%d.%02x; timeout=%d\n", phy, reg, timeout);
|
||||
goto fail;
|
||||
}
|
||||
data = arswitch_readreg_lsb(dev, a) &
|
||||
AR8X16_MDIO_CTRL_DATA_MASK;
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
@ -118,7 +155,7 @@ arswitch_readphy(device_t dev, int phy, int reg)
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_writephy(device_t dev, int phy, int reg, int data)
|
||||
arswitch_writephy_internal(device_t dev, int phy, int reg, int data)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
uint32_t ctrl;
|
||||
|
||||
@ -28,7 +28,10 @@
|
||||
#ifndef __ARSWITCH_PHY_H__
|
||||
#define __ARSWITCH_PHY_H__
|
||||
|
||||
extern int arswitch_readphy(device_t dev, int phy, int reg);
|
||||
extern int arswitch_writephy(device_t dev, int phy, int reg, int data);
|
||||
extern int arswitch_readphy_external(device_t dev, int phy, int reg);
|
||||
extern int arswitch_writephy_external(device_t dev, int phy, int reg, int data);
|
||||
|
||||
extern int arswitch_readphy_internal(device_t dev, int phy, int reg);
|
||||
extern int arswitch_writephy_internal(device_t dev, int phy, int reg, int data);
|
||||
|
||||
#endif /* __ARSWITCH_PHY_H__ */
|
||||
|
||||
@ -68,12 +68,13 @@ arswitch_split_setpage(device_t dev, uint32_t addr, uint16_t *phy,
|
||||
struct arswitch_softc *sc = device_get_softc(dev);
|
||||
uint16_t page;
|
||||
|
||||
page = ((addr) >> 9) & 0xffff;
|
||||
*phy = (((addr) >> 6) & 0x07) | 0x10;
|
||||
*reg = ((addr) >> 1) & 0x1f;
|
||||
page = (addr >> 9) & 0x1ff;
|
||||
*phy = (addr >> 6) & 0x7;
|
||||
*reg = (addr >> 1) & 0x1f;
|
||||
|
||||
if (sc->page != page) {
|
||||
MDIO_WRITEREG(device_get_parent(dev), 0x18, 0, page);
|
||||
DELAY(2000);
|
||||
sc->page = page;
|
||||
}
|
||||
}
|
||||
@ -87,9 +88,21 @@ static inline int
|
||||
arswitch_readreg16(device_t dev, int addr)
|
||||
{
|
||||
uint16_t phy, reg;
|
||||
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return (MDIO_READREG(device_get_parent(dev), phy, reg));
|
||||
return (MDIO_READREG(device_get_parent(dev), 0x10 | phy, reg));
|
||||
}
|
||||
|
||||
/*
|
||||
* Write half a register. See above!
|
||||
*/
|
||||
static inline int
|
||||
arswitch_writereg16(device_t dev, int addr, int data)
|
||||
{
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return (MDIO_WRITEREG(device_get_parent(dev), 0x10 | phy, reg, data));
|
||||
}
|
||||
|
||||
/*
|
||||
@ -121,18 +134,70 @@ arswitch_writemmd(device_t dev, int phy, uint16_t dbg_addr,
|
||||
MII_ATH_MMD_DATA, dbg_data);
|
||||
}
|
||||
|
||||
/*
|
||||
* Write half a register
|
||||
*/
|
||||
static inline int
|
||||
arswitch_writereg16(device_t dev, int addr, int data)
|
||||
static uint32_t
|
||||
arswitch_reg_read32(device_t dev, int phy, int reg)
|
||||
{
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return (MDIO_WRITEREG(device_get_parent(dev), phy, reg, data));
|
||||
uint16_t lo, hi;
|
||||
lo = MDIO_READREG(device_get_parent(dev), phy, reg);
|
||||
hi = MDIO_READREG(device_get_parent(dev), phy, reg + 1);
|
||||
|
||||
return (hi << 16) | lo;
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_reg_write32(device_t dev, int phy, int reg, uint32_t value)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
int r;
|
||||
uint16_t lo, hi;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
lo = value & 0xffff;
|
||||
hi = (uint16_t) (value >> 16);
|
||||
|
||||
if (sc->mii_lo_first) {
|
||||
r = MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg, lo);
|
||||
r |= MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg + 1, hi);
|
||||
} else {
|
||||
r = MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg + 1, hi);
|
||||
r |= MDIO_WRITEREG(device_get_parent(dev),
|
||||
phy, reg, lo);
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_readreg(device_t dev, int addr)
|
||||
{
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return arswitch_reg_read32(dev, 0x10 | phy, reg);
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_writereg(device_t dev, int addr, int value)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
uint16_t phy, reg;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
|
||||
}
|
||||
|
||||
/*
|
||||
* Read/write 16 bit values in the switch register space.
|
||||
*
|
||||
* Some of the registers are control registers (eg the MDIO
|
||||
* data versus control space) and so need to be treated
|
||||
* differently.
|
||||
*/
|
||||
int
|
||||
arswitch_readreg_lsb(device_t dev, int addr)
|
||||
{
|
||||
@ -161,53 +226,31 @@ arswitch_writereg_msb(device_t dev, int addr, int data)
|
||||
return (arswitch_writereg16(dev, addr + 2, (data >> 16) & 0xffff));
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_readreg(device_t dev, int addr)
|
||||
{
|
||||
|
||||
return (arswitch_readreg_lsb(dev, addr) |
|
||||
arswitch_readreg_msb(dev, addr));
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_writereg(device_t dev, int addr, int value)
|
||||
{
|
||||
struct arswitch_softc *sc;
|
||||
int r;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
/* XXX Check the first write too? */
|
||||
if (sc->mii_lo_first) {
|
||||
r = arswitch_writereg_lsb(dev, addr, value);
|
||||
r |= arswitch_writereg_msb(dev, addr, value);
|
||||
} else {
|
||||
r = arswitch_writereg_msb(dev, addr, value);
|
||||
r |= arswitch_writereg_lsb(dev, addr, value);
|
||||
}
|
||||
|
||||
return r;
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_modifyreg(device_t dev, int addr, int mask, int set)
|
||||
{
|
||||
int value;
|
||||
|
||||
value = arswitch_readreg(dev, addr);
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
|
||||
value = arswitch_reg_read32(dev, 0x10 | phy, reg);
|
||||
value &= ~mask;
|
||||
value |= set;
|
||||
return (arswitch_writereg(dev, addr, value));
|
||||
return (arswitch_reg_write32(dev, 0x10 | phy, reg, value));
|
||||
}
|
||||
|
||||
int
|
||||
arswitch_waitreg(device_t dev, int addr, int mask, int val, int timeout)
|
||||
{
|
||||
int err, v;
|
||||
uint16_t phy, reg;
|
||||
|
||||
arswitch_split_setpage(dev, addr, &phy, ®);
|
||||
|
||||
err = -1;
|
||||
while (1) {
|
||||
v = arswitch_readreg(dev, addr);
|
||||
v = arswitch_reg_read32(dev, 0x10 | phy, reg);
|
||||
v &= mask;
|
||||
if (v == val) {
|
||||
err = 0;
|
||||
|
||||
@ -53,11 +53,10 @@
|
||||
/*
|
||||
* XXX TODO: teach about the AR933x SoC switch
|
||||
* XXX TODO: teach about the AR934x SoC switch
|
||||
* XXX TODO: teach about the AR8327 external switch
|
||||
*/
|
||||
|
||||
static int
|
||||
arswitch_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid,
|
||||
ar8xxx_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid,
|
||||
uint32_t data)
|
||||
{
|
||||
int err;
|
||||
@ -87,30 +86,30 @@ arswitch_vlan_op(struct arswitch_softc *sc, uint32_t op, uint32_t vid,
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_flush_dot1q_vlan(struct arswitch_softc *sc)
|
||||
int
|
||||
ar8xxx_flush_dot1q_vlan(struct arswitch_softc *sc)
|
||||
{
|
||||
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
|
||||
return (arswitch_vlan_op(sc, AR8X16_VLAN_OP_FLUSH, 0, 0));
|
||||
return (ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_FLUSH, 0, 0));
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_purge_dot1q_vlan(struct arswitch_softc *sc, int vid)
|
||||
int
|
||||
ar8xxx_purge_dot1q_vlan(struct arswitch_softc *sc, int vid)
|
||||
{
|
||||
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
|
||||
return (arswitch_vlan_op(sc, AR8X16_VLAN_OP_PURGE, vid, 0));
|
||||
return (ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_PURGE, vid, 0));
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)
|
||||
int
|
||||
ar8xxx_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)
|
||||
{
|
||||
uint32_t reg;
|
||||
int err;
|
||||
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
|
||||
err = arswitch_vlan_op(sc, AR8X16_VLAN_OP_GET, vid, 0);
|
||||
err = ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_GET, vid, 0);
|
||||
if (err)
|
||||
return (err);
|
||||
|
||||
@ -124,20 +123,20 @@ arswitch_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports, int vid)
|
||||
int
|
||||
ar8xxx_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports, int vid)
|
||||
{
|
||||
int err;
|
||||
|
||||
ARSWITCH_LOCK_ASSERT(sc, MA_OWNED);
|
||||
err = arswitch_vlan_op(sc, AR8X16_VLAN_OP_LOAD, vid, ports);
|
||||
err = ar8xxx_vlan_op(sc, AR8X16_VLAN_OP_LOAD, vid, ports);
|
||||
if (err)
|
||||
return (err);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_get_port_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)
|
||||
int
|
||||
ar8xxx_get_port_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)
|
||||
{
|
||||
int port;
|
||||
uint32_t reg;
|
||||
@ -151,8 +150,8 @@ arswitch_get_port_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid)
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
arswitch_set_port_vlan(struct arswitch_softc *sc, uint32_t ports, int vid)
|
||||
int
|
||||
ar8xxx_set_port_vlan(struct arswitch_softc *sc, uint32_t ports, int vid)
|
||||
{
|
||||
int err, port;
|
||||
|
||||
@ -193,7 +192,7 @@ ar8xxx_reset_vlans(struct arswitch_softc *sc)
|
||||
}
|
||||
}
|
||||
|
||||
if (arswitch_flush_dot1q_vlan(sc)) {
|
||||
if (sc->hal.arswitch_flush_dot1q_vlan(sc)) {
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
return;
|
||||
}
|
||||
@ -224,7 +223,7 @@ ar8xxx_reset_vlans(struct arswitch_softc *sc)
|
||||
ports = 0;
|
||||
for (i = 0; i <= sc->numphys; i++)
|
||||
ports |= (1 << i);
|
||||
arswitch_set_dot1q_vlan(sc, ports, sc->vid[0]);
|
||||
sc->hal.arswitch_set_dot1q_vlan(sc, ports, sc->vid[0]);
|
||||
sc->vid[0] |= ETHERSWITCH_VID_VALID;
|
||||
} else if (sc->vlan_mode == ETHERSWITCH_VLAN_PORT) {
|
||||
/* Initialize the port based vlans. */
|
||||
@ -286,11 +285,11 @@ ar8xxx_getvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
|
||||
/* Member Ports. */
|
||||
switch (sc->vlan_mode) {
|
||||
case ETHERSWITCH_VLAN_DOT1Q:
|
||||
err = arswitch_get_dot1q_vlan(sc, &vg->es_member_ports,
|
||||
err = sc->hal.arswitch_get_dot1q_vlan(sc, &vg->es_member_ports,
|
||||
vg->es_vid);
|
||||
break;
|
||||
case ETHERSWITCH_VLAN_PORT:
|
||||
err = arswitch_get_port_vlan(sc, &vg->es_member_ports,
|
||||
err = sc->hal.arswitch_get_port_vlan(sc, &vg->es_member_ports,
|
||||
vg->es_vid);
|
||||
break;
|
||||
default:
|
||||
@ -323,7 +322,7 @@ ar8xxx_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
|
||||
(vid & ETHERSWITCH_VID_VALID) != 0 &&
|
||||
(vid & ETHERSWITCH_VID_MASK) !=
|
||||
(vg->es_vid & ETHERSWITCH_VID_MASK)) {
|
||||
err = arswitch_purge_dot1q_vlan(sc, vid);
|
||||
err = sc->hal.arswitch_purge_dot1q_vlan(sc, vid);
|
||||
if (err) {
|
||||
ARSWITCH_UNLOCK(sc);
|
||||
return (err);
|
||||
@ -345,10 +344,10 @@ ar8xxx_setvgroup(struct arswitch_softc *sc, etherswitch_vlangroup_t *vg)
|
||||
/* Member Ports. */
|
||||
switch (sc->vlan_mode) {
|
||||
case ETHERSWITCH_VLAN_DOT1Q:
|
||||
err = arswitch_set_dot1q_vlan(sc, vg->es_member_ports, vid);
|
||||
err = sc->hal.arswitch_set_dot1q_vlan(sc, vg->es_member_ports, vid);
|
||||
break;
|
||||
case ETHERSWITCH_VLAN_PORT:
|
||||
err = arswitch_set_port_vlan(sc, vg->es_member_ports, vid);
|
||||
err = sc->hal.arswitch_set_port_vlan(sc, vg->es_member_ports, vid);
|
||||
break;
|
||||
default:
|
||||
err = -1;
|
||||
|
||||
@ -35,4 +35,11 @@ int ar8xxx_setvgroup(struct arswitch_softc *, etherswitch_vlangroup_t *);
|
||||
int ar8xxx_get_pvid(struct arswitch_softc *, int, int *);
|
||||
int ar8xxx_set_pvid(struct arswitch_softc *, int, int);
|
||||
|
||||
int ar8xxx_flush_dot1q_vlan(struct arswitch_softc *sc);
|
||||
int ar8xxx_purge_dot1q_vlan(struct arswitch_softc *sc, int vid);
|
||||
int ar8xxx_get_dot1q_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid);
|
||||
int ar8xxx_set_dot1q_vlan(struct arswitch_softc *sc, uint32_t ports, int vid);
|
||||
int ar8xxx_get_port_vlan(struct arswitch_softc *sc, uint32_t *ports, int vid);
|
||||
int ar8xxx_set_port_vlan(struct arswitch_softc *sc, uint32_t ports, int vid);
|
||||
|
||||
#endif /* __ARSWITCH_VLANS_H__ */
|
||||
|
||||
@ -370,6 +370,9 @@
|
||||
#define AR8327_NUM_PHYS 5
|
||||
#define AR8327_PORTS_ALL 0x7f
|
||||
|
||||
#define AR8327_PORT_GMAC0 0
|
||||
#define AR8327_PORT_GMAC6 6
|
||||
|
||||
#define AR8327_REG_MASK 0x000
|
||||
|
||||
#define AR8327_REG_PAD0_MODE 0x004
|
||||
|
||||
@ -60,7 +60,7 @@ struct arswitch_softc {
|
||||
int is_internal_switch;
|
||||
int chip_ver;
|
||||
int chip_rev;
|
||||
int mii_lo_first;
|
||||
int mii_lo_first; /* Send low data DWORD before high */
|
||||
ar8x16_switch_type sc_switchtype;
|
||||
/* should be the max of both pre-AR8327 and AR8327 ports */
|
||||
char *ifname[ARSWITCH_NUM_PHYS];
|
||||
@ -98,6 +98,22 @@ struct arswitch_softc {
|
||||
int *);
|
||||
int (* arswitch_vlan_set_pvid) (struct arswitch_softc *, int,
|
||||
int);
|
||||
|
||||
int (* arswitch_flush_dot1q_vlan) (struct arswitch_softc *sc);
|
||||
int (* arswitch_purge_dot1q_vlan) (struct arswitch_softc *sc,
|
||||
int vid);
|
||||
int (* arswitch_get_dot1q_vlan) (struct arswitch_softc *,
|
||||
uint32_t *ports, int vid);
|
||||
int (* arswitch_set_dot1q_vlan) (struct arswitch_softc *sc,
|
||||
uint32_t ports, int vid);
|
||||
int (* arswitch_get_port_vlan) (struct arswitch_softc *sc,
|
||||
uint32_t *ports, int vid);
|
||||
int (* arswitch_set_port_vlan) (struct arswitch_softc *sc,
|
||||
uint32_t ports, int vid);
|
||||
|
||||
/* PHY functions */
|
||||
int (* arswitch_phy_read) (device_t, int, int);
|
||||
int (* arswitch_phy_write) (device_t, int, int, int);
|
||||
} hal;
|
||||
|
||||
struct {
|
||||
|
||||
@ -185,9 +185,9 @@ gpiobus_init_softc(device_t dev)
|
||||
/* Pins = GPIO_PIN_MAX() + 1 */
|
||||
sc->sc_npins++;
|
||||
|
||||
sc->sc_pins_mapped = malloc(sizeof(int) * sc->sc_npins, M_DEVBUF,
|
||||
sc->sc_pins = malloc(sizeof(*sc->sc_pins) * sc->sc_npins, M_DEVBUF,
|
||||
M_NOWAIT | M_ZERO);
|
||||
if (sc->sc_pins_mapped == NULL)
|
||||
if (sc->sc_pins == NULL)
|
||||
return (ENOMEM);
|
||||
|
||||
/* Initialize the bus lock. */
|
||||
@ -242,11 +242,11 @@ gpiobus_map_pin(device_t bus, uint32_t pin)
|
||||
return (-1);
|
||||
}
|
||||
/* Mark pin as mapped and give warning if it's already mapped. */
|
||||
if (sc->sc_pins_mapped[pin]) {
|
||||
if (sc->sc_pins[pin].mapped) {
|
||||
device_printf(bus, "warning: pin %d is already mapped\n", pin);
|
||||
return (-1);
|
||||
}
|
||||
sc->sc_pins_mapped[pin] = 1;
|
||||
sc->sc_pins[pin].mapped = 1;
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -281,6 +281,9 @@ gpiobus_parse_pins(struct gpiobus_softc *sc, device_t child, int mask)
|
||||
return (EINVAL);
|
||||
}
|
||||
devi->pins[npins++] = i;
|
||||
/* Use the child name as pin name. */
|
||||
GPIOBUS_PIN_SETNAME(sc->sc_busdev, i,
|
||||
device_get_nameunit(child));
|
||||
}
|
||||
|
||||
return (0);
|
||||
@ -340,10 +343,14 @@ gpiobus_detach(device_t dev)
|
||||
gpiobus_free_ivars(devi);
|
||||
}
|
||||
free(devlist, M_TEMP);
|
||||
|
||||
if (sc->sc_pins_mapped) {
|
||||
free(sc->sc_pins_mapped, M_DEVBUF);
|
||||
sc->sc_pins_mapped = NULL;
|
||||
if (sc->sc_pins) {
|
||||
for (i = 0; i < sc->sc_npins; i++) {
|
||||
if (sc->sc_pins[i].name != NULL)
|
||||
free(sc->sc_pins[i].name, M_DEVBUF);
|
||||
sc->sc_pins[i].name = NULL;
|
||||
}
|
||||
free(sc->sc_pins, M_DEVBUF);
|
||||
sc->sc_pins = NULL;
|
||||
}
|
||||
|
||||
return (0);
|
||||
@ -664,6 +671,43 @@ gpiobus_pin_toggle(device_t dev, device_t child, uint32_t pin)
|
||||
return GPIO_PIN_TOGGLE(sc->sc_dev, devi->pins[pin]);
|
||||
}
|
||||
|
||||
static int
|
||||
gpiobus_pin_getname(device_t dev, uint32_t pin, char *name)
|
||||
{
|
||||
struct gpiobus_softc *sc;
|
||||
|
||||
sc = GPIOBUS_SOFTC(dev);
|
||||
if (pin > sc->sc_npins)
|
||||
return (EINVAL);
|
||||
/* Did we have a name for this pin ? */
|
||||
if (sc->sc_pins[pin].name != NULL) {
|
||||
memcpy(name, sc->sc_pins[pin].name, GPIOMAXNAME);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/* Return the default pin name. */
|
||||
return (GPIO_PIN_GETNAME(device_get_parent(dev), pin, name));
|
||||
}
|
||||
|
||||
static int
|
||||
gpiobus_pin_setname(device_t dev, uint32_t pin, const char *name)
|
||||
{
|
||||
struct gpiobus_softc *sc;
|
||||
|
||||
sc = GPIOBUS_SOFTC(dev);
|
||||
if (pin > sc->sc_npins)
|
||||
return (EINVAL);
|
||||
if (name == NULL)
|
||||
return (EINVAL);
|
||||
/* Save the pin name. */
|
||||
if (sc->sc_pins[pin].name == NULL)
|
||||
sc->sc_pins[pin].name = malloc(GPIOMAXNAME, M_DEVBUF,
|
||||
M_WAITOK | M_ZERO);
|
||||
strlcpy(sc->sc_pins[pin].name, name, GPIOMAXNAME);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t gpiobus_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, gpiobus_probe),
|
||||
@ -699,6 +743,8 @@ static device_method_t gpiobus_methods[] = {
|
||||
DEVMETHOD(gpiobus_pin_get, gpiobus_pin_get),
|
||||
DEVMETHOD(gpiobus_pin_set, gpiobus_pin_set),
|
||||
DEVMETHOD(gpiobus_pin_toggle, gpiobus_pin_toggle),
|
||||
DEVMETHOD(gpiobus_pin_getname, gpiobus_pin_getname),
|
||||
DEVMETHOD(gpiobus_pin_setname, gpiobus_pin_setname),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
@ -106,3 +106,21 @@ METHOD int pin_setflags {
|
||||
uint32_t pin_num;
|
||||
uint32_t flags;
|
||||
};
|
||||
|
||||
#
|
||||
# Get the pin name
|
||||
#
|
||||
METHOD int pin_getname {
|
||||
device_t dev;
|
||||
uint32_t pin_num;
|
||||
char *name;
|
||||
};
|
||||
|
||||
#
|
||||
# Set the pin name
|
||||
#
|
||||
METHOD int pin_setname {
|
||||
device_t dev;
|
||||
uint32_t pin_num;
|
||||
const char *name;
|
||||
};
|
||||
|
||||
@ -60,6 +60,12 @@
|
||||
#define GPIOBUS_WAIT 1
|
||||
#define GPIOBUS_DONTWAIT 2
|
||||
|
||||
struct gpiobus_pin_data
|
||||
{
|
||||
int mapped; /* pin is mapped/reserved. */
|
||||
char *name; /* pin name. */
|
||||
};
|
||||
|
||||
struct gpiobus_softc
|
||||
{
|
||||
struct mtx sc_mtx; /* bus mutex */
|
||||
@ -68,7 +74,7 @@ struct gpiobus_softc
|
||||
device_t sc_owner; /* bus owner */
|
||||
device_t sc_dev; /* driver device */
|
||||
int sc_npins; /* total pins on bus */
|
||||
int *sc_pins_mapped; /* mark mapped pins */
|
||||
struct gpiobus_pin_data *sc_pins; /* pin data */
|
||||
};
|
||||
|
||||
struct gpiobus_pin
|
||||
|
||||
@ -40,6 +40,7 @@ __FBSDID("$FreeBSD$");
|
||||
#include <dev/gpio/gpiobusvar.h>
|
||||
|
||||
#include "gpio_if.h"
|
||||
#include "gpiobus_if.h"
|
||||
|
||||
#undef GPIOC_DEBUG
|
||||
#ifdef GPIOC_DEBUG
|
||||
@ -112,12 +113,16 @@ static int
|
||||
gpioc_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int fflag,
|
||||
struct thread *td)
|
||||
{
|
||||
device_t bus;
|
||||
int max_pin, res;
|
||||
struct gpioc_softc *sc = cdev->si_drv1;
|
||||
struct gpio_pin pin;
|
||||
struct gpio_req req;
|
||||
uint32_t caps;
|
||||
|
||||
bus = GPIO_GET_BUS(sc->sc_pdev);
|
||||
if (bus == NULL)
|
||||
return (EINVAL);
|
||||
switch (cmd) {
|
||||
case GPIOMAXPIN:
|
||||
max_pin = -1;
|
||||
@ -133,7 +138,7 @@ gpioc_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int fflag,
|
||||
if (res)
|
||||
break;
|
||||
GPIO_PIN_GETCAPS(sc->sc_pdev, pin.gp_pin, &pin.gp_caps);
|
||||
GPIO_PIN_GETNAME(sc->sc_pdev, pin.gp_pin, pin.gp_name);
|
||||
GPIOBUS_PIN_GETNAME(bus, pin.gp_pin, pin.gp_name);
|
||||
bcopy(&pin, arg, sizeof(pin));
|
||||
break;
|
||||
case GPIOSETCONFIG:
|
||||
@ -167,6 +172,12 @@ gpioc_ioctl(struct cdev *cdev, u_long cmd, caddr_t arg, int fflag,
|
||||
req.gp_pin);
|
||||
res = GPIO_PIN_TOGGLE(sc->sc_pdev, req.gp_pin);
|
||||
break;
|
||||
case GPIOSETNAME:
|
||||
bcopy(arg, &pin, sizeof(pin));
|
||||
dprintf("set name on pin %d\n", pin.gp_pin);
|
||||
res = GPIOBUS_PIN_SETNAME(bus, pin.gp_pin,
|
||||
pin.gp_name);
|
||||
break;
|
||||
default:
|
||||
return (ENOTTY);
|
||||
break;
|
||||
|
||||
@ -39,6 +39,8 @@ __FBSDID("$FreeBSD$");
|
||||
#include <dev/gpio/gpiobusvar.h>
|
||||
#include <dev/ofw/ofw_bus.h>
|
||||
|
||||
#include "gpiobus_if.h"
|
||||
|
||||
static struct ofw_gpiobus_devinfo *ofw_gpiobus_setup_devinfo(device_t,
|
||||
device_t, phandle_t);
|
||||
static void ofw_gpiobus_destroy_devinfo(device_t, struct ofw_gpiobus_devinfo *);
|
||||
@ -49,6 +51,8 @@ device_t
|
||||
ofw_gpiobus_add_fdt_child(device_t bus, const char *drvname, phandle_t child)
|
||||
{
|
||||
device_t childdev;
|
||||
int i;
|
||||
struct gpiobus_ivar *devi;
|
||||
struct ofw_gpiobus_devinfo *dinfo;
|
||||
|
||||
/*
|
||||
@ -67,6 +71,11 @@ ofw_gpiobus_add_fdt_child(device_t bus, const char *drvname, phandle_t child)
|
||||
device_delete_child(bus, childdev);
|
||||
return (NULL);
|
||||
}
|
||||
/* Use the child name as pin name. */
|
||||
devi = &dinfo->opd_dinfo;
|
||||
for (i = 0; i < devi->npins; i++)
|
||||
GPIOBUS_PIN_SETNAME(bus, devi->pins[i],
|
||||
device_get_nameunit(childdev));
|
||||
|
||||
return (childdev);
|
||||
}
|
||||
@ -159,7 +168,7 @@ ofw_gpiobus_destroy_devinfo(device_t bus, struct ofw_gpiobus_devinfo *dinfo)
|
||||
for (i = 0; i < devi->npins; i++) {
|
||||
if (devi->pins[i] > sc->sc_npins)
|
||||
continue;
|
||||
sc->sc_pins_mapped[devi->pins[i]] = 0;
|
||||
sc->sc_pins[devi->pins[i]].mapped = 0;
|
||||
}
|
||||
gpiobus_free_ivars(devi);
|
||||
resource_list_free(&dinfo->opd_dinfo.rl);
|
||||
|
||||
@ -1126,6 +1126,10 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
IAPDESCR(79H_3CH, 0x79, 0x3C, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
|
||||
IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2),
|
||||
|
||||
@ -1188,46 +1192,57 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
|
||||
IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
|
||||
IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2),
|
||||
IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
@ -1261,7 +1276,8 @@ static struct iap_event_descr iap_events[] = {
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_IB | IAP_F_IBX),
|
||||
IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_IB |
|
||||
IAP_F_SBX | IAP_F_IBX),
|
||||
IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/
|
||||
IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/
|
||||
@ -1586,29 +1602,21 @@ static struct iap_event_descr iap_events[] = {
|
||||
|
||||
/* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */
|
||||
IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC),
|
||||
IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB |
|
||||
IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
|
||||
IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
|
||||
IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM),
|
||||
IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
|
||||
IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
|
||||
IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX),
|
||||
IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
|
||||
IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */
|
||||
IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
|
||||
IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */
|
||||
IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW |
|
||||
IAP_F_HWX),
|
||||
IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
|
||||
IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */
|
||||
IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX |
|
||||
IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */
|
||||
IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
|
||||
IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
|
||||
IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
|
||||
IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB |
|
||||
IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
|
||||
IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB |
|
||||
IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX),
|
||||
IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM |
|
||||
@ -1965,15 +1973,15 @@ iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri)
|
||||
break;
|
||||
/* Events valid only on counter 1. */
|
||||
case PMC_EV_IAP_EVENT_C0H_01H:
|
||||
mask = 0x1;
|
||||
mask = 0x2;
|
||||
break;
|
||||
/* Events valid only on counter 2. */
|
||||
case PMC_EV_IAP_EVENT_48H_01H:
|
||||
case PMC_EV_IAP_EVENT_A2H_02H:
|
||||
case PMC_EV_IAP_EVENT_A3H_08H:
|
||||
mask = 0x4;
|
||||
break;
|
||||
/* Events valid only on counter 3. */
|
||||
case PMC_EV_IAP_EVENT_A3H_08H:
|
||||
case PMC_EV_IAP_EVENT_BBH_01H:
|
||||
case PMC_EV_IAP_EVENT_CDH_01H:
|
||||
case PMC_EV_IAP_EVENT_CDH_02H:
|
||||
|
||||
@ -856,7 +856,14 @@ __PMC_EV(IAP, EVENT_88H_10H) \
|
||||
__PMC_EV(IAP, EVENT_88H_20H) \
|
||||
__PMC_EV(IAP, EVENT_88H_30H) \
|
||||
__PMC_EV(IAP, EVENT_88H_40H) \
|
||||
__PMC_EV(IAP, EVENT_88H_41H) \
|
||||
__PMC_EV(IAP, EVENT_88H_80H) \
|
||||
__PMC_EV(IAP, EVENT_88H_81H) \
|
||||
__PMC_EV(IAP, EVENT_88H_82H) \
|
||||
__PMC_EV(IAP, EVENT_88H_84H) \
|
||||
__PMC_EV(IAP, EVENT_88H_88H) \
|
||||
__PMC_EV(IAP, EVENT_88H_90H) \
|
||||
__PMC_EV(IAP, EVENT_88H_A0H) \
|
||||
__PMC_EV(IAP, EVENT_88H_7FH) \
|
||||
__PMC_EV(IAP, EVENT_88H_FFH) \
|
||||
__PMC_EV(IAP, EVENT_89H_00H) \
|
||||
@ -869,7 +876,14 @@ __PMC_EV(IAP, EVENT_89H_10H) \
|
||||
__PMC_EV(IAP, EVENT_89H_20H) \
|
||||
__PMC_EV(IAP, EVENT_89H_30H) \
|
||||
__PMC_EV(IAP, EVENT_89H_40H) \
|
||||
__PMC_EV(IAP, EVENT_89H_41H) \
|
||||
__PMC_EV(IAP, EVENT_89H_80H) \
|
||||
__PMC_EV(IAP, EVENT_89H_81H) \
|
||||
__PMC_EV(IAP, EVENT_89H_82H) \
|
||||
__PMC_EV(IAP, EVENT_89H_84H) \
|
||||
__PMC_EV(IAP, EVENT_89H_88H) \
|
||||
__PMC_EV(IAP, EVENT_89H_90H) \
|
||||
__PMC_EV(IAP, EVENT_89H_A0H) \
|
||||
__PMC_EV(IAP, EVENT_89H_7FH) \
|
||||
__PMC_EV(IAP, EVENT_89H_FFH) \
|
||||
__PMC_EV(IAP, EVENT_8AH_00H) \
|
||||
@ -2578,6 +2592,7 @@ __PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H)
|
||||
* Aliases for Haswell core PMC events
|
||||
*/
|
||||
#define __PMC_EV_ALIAS_HASWELL_XEON() \
|
||||
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
|
||||
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
|
||||
@ -2585,7 +2600,7 @@ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K", \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \
|
||||
IAP_EVENT_08H_04H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \
|
||||
@ -2641,8 +2656,8 @@ __PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \
|
||||
IAP_EVENT_58H_08H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_02H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_01H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
|
||||
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
|
||||
IAP_EVENT_60H_01H) \
|
||||
@ -2677,24 +2692,22 @@ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_88H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
|
||||
IAP_EVENT_88H_84H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_89H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
|
||||
IAP_EVENT_89H_84H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
|
||||
@ -2762,14 +2775,12 @@ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
|
||||
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
|
||||
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
|
||||
@ -2807,6 +2818,7 @@ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H)
|
||||
|
||||
|
||||
#define __PMC_EV_ALIAS_HASWELL() \
|
||||
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
|
||||
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
|
||||
@ -2814,7 +2826,7 @@ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K", \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \
|
||||
IAP_EVENT_08H_04H) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \
|
||||
__PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \
|
||||
@ -2870,8 +2882,8 @@ __PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \
|
||||
IAP_EVENT_58H_08H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \
|
||||
__PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_02H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_01H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \
|
||||
__PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \
|
||||
__PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \
|
||||
__PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \
|
||||
IAP_EVENT_60H_01H) \
|
||||
@ -2906,24 +2918,22 @@ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_88H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
|
||||
IAP_EVENT_88H_84H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_89H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
|
||||
IAP_EVENT_89H_84H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
|
||||
@ -2991,14 +3001,12 @@ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \
|
||||
__PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
|
||||
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
|
||||
@ -3036,6 +3044,7 @@ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H)
|
||||
|
||||
|
||||
#define __PMC_EV_ALIAS_IVYBRIDGE() \
|
||||
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
|
||||
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
|
||||
@ -3132,24 +3141,22 @@ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_88H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
|
||||
IAP_EVENT_88H_84H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_89H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
|
||||
IAP_EVENT_89H_84H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
|
||||
@ -3218,15 +3225,12 @@ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
|
||||
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
|
||||
@ -3268,6 +3272,7 @@ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H)
|
||||
* Aliases for Ivy Bridge Xeon PMC events (325462-045US January 2013)
|
||||
*/
|
||||
#define __PMC_EV_ALIAS_IVYBRIDGE_XEON() \
|
||||
__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \
|
||||
__PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \
|
||||
__PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \
|
||||
@ -3363,24 +3368,22 @@ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_88H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
|
||||
IAP_EVENT_88H_84H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_89H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
|
||||
IAP_EVENT_89H_84H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
|
||||
@ -3449,15 +3452,12 @@ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \
|
||||
__PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \
|
||||
__PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
|
||||
__PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \
|
||||
__PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \
|
||||
__PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \
|
||||
@ -3599,24 +3599,22 @@ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_88H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
|
||||
IAP_EVENT_88H_84H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_89H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
|
||||
IAP_EVENT_89H_84H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
|
||||
@ -3829,25 +3827,23 @@ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \
|
||||
__PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \
|
||||
__PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_88H_04H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \
|
||||
IAP_EVENT_88H_84H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \
|
||||
IAP_EVENT_89H_04H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
IAP_EVENT_89H_84H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \
|
||||
__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \
|
||||
__PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \
|
||||
__PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user