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Enable UART support for Xilinx Ultrascale+ SoCs
Xilinx Ultrascale+ are based on Cortex-A53 and use existing UART driver (uart_dev_cdnc). Enable it in arm64 GENERIC config. Submitted by: Michal Stanek <mst@semihalf.com> Obtained from: Semihalf
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parent
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commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=336259
@ -711,6 +711,8 @@ static struct uart_class uart_cdnc_class = {
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static struct ofw_compat_data compat_data[] = {
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{"cadence,uart", (uintptr_t)&uart_cdnc_class},
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{"cdns,uart-r1p12", (uintptr_t)&uart_cdnc_class},
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{"xlnx,xuartps", (uintptr_t)&uart_cdnc_class},
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{NULL, (uintptr_t)NULL},
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};
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UART_FDT_CLASS_AND_DEVICE(compat_data);
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@ -106,6 +106,7 @@ options SOC_CAVM_THUNDERX
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options SOC_HISI_HI6220
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options SOC_BRCM_BCM2837
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options SOC_ROCKCHIP_RK3328
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options SOC_XILINX_ZYNQ
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# Annapurna Alpine drivers
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device al_ccu # Alpine Cache Coherency Unit
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@ -87,6 +87,7 @@ arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt
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arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt
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arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837
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arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
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arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq
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arm64/acpica/acpi_machdep.c optional acpi
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arm64/acpica/OsdEnvironment.c optional acpi
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arm64/acpica/acpi_wakeup.c optional acpi
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@ -20,3 +20,4 @@ SOC_BRCM_BCM2837 opt_soc.h
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SOC_CAVM_THUNDERX opt_soc.h
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SOC_HISI_HI6220 opt_soc.h
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SOC_ROCKCHIP_RK3328 opt_soc.h
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SOC_XILINX_ZYNQ opt_soc.h
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