mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-16 10:20:30 +00:00
Add another CPUID for AMD CPUs and fix style(9) while I am here.
This commit is contained in:
Jung-uk Kim
parent
4b493b1a6d
commit
ab5916a526
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=167493
@ -312,7 +312,7 @@ printcpuinfo(void)
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"\006<b5>"
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"\007<b6>"
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"\010<b7>"
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"\011<b8>"
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"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
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"\012<b9>"
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"\013<b10>"
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"\014<b11>"
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@ -112,35 +112,36 @@
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#define CPUID_IA64 0x40000000
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#define CPUID_PBE 0x80000000
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#define CPUID2_SSE3 0x00000001
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#define CPUID2_MON 0x00000008
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#define CPUID2_DS_CPL 0x00000010
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#define CPUID2_VMX 0x00000020
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#define CPUID2_EST 0x00000080
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#define CPUID2_TM2 0x00000100
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#define CPUID2_SSSE3 0x00000200
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#define CPUID2_CNXTID 0x00000400
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#define CPUID2_CX16 0x00002000
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#define CPUID2_XTPR 0x00004000
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#define CPUID2_SSE3 0x00000001
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#define CPUID2_MON 0x00000008
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#define CPUID2_DS_CPL 0x00000010
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#define CPUID2_VMX 0x00000020
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#define CPUID2_EST 0x00000080
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#define CPUID2_TM2 0x00000100
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#define CPUID2_SSSE3 0x00000200
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#define CPUID2_CNXTID 0x00000400
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#define CPUID2_CX16 0x00002000
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#define CPUID2_XTPR 0x00004000
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/*
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* Important bits in the AMD extended cpuid flags
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*/
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#define AMDID_SYSCALL 0x00000800
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#define AMDID_MP 0x00080000
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#define AMDID_NX 0x00100000
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#define AMDID_EXT_MMX 0x00400000
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#define AMDID_FFXSR 0x01000000
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#define AMDID_RDTSCP 0x08000000
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#define AMDID_LM 0x20000000
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#define AMDID_EXT_3DNOW 0x40000000
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#define AMDID_3DNOW 0x80000000
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#define AMDID_SYSCALL 0x00000800
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#define AMDID_MP 0x00080000
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#define AMDID_NX 0x00100000
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#define AMDID_EXT_MMX 0x00400000
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#define AMDID_FFXSR 0x01000000
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#define AMDID_RDTSCP 0x08000000
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#define AMDID_LM 0x20000000
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#define AMDID_EXT_3DNOW 0x40000000
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#define AMDID_3DNOW 0x80000000
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#define AMDID2_LAHF 0x00000001
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#define AMDID2_CMP 0x00000002
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#define AMDID2_SVM 0x00000004
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#define AMDID2_EXT_APIC 0x00000008
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#define AMDID2_CR8 0x00000010
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#define AMDID2_LAHF 0x00000001
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#define AMDID2_CMP 0x00000002
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#define AMDID2_SVM 0x00000004
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#define AMDID2_EXT_APIC 0x00000008
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#define AMDID2_CR8 0x00000010
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#define AMDID2_PREFETCH 0x00000100
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/*
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* CPUID instruction 1 ebx info
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@ -153,29 +154,29 @@
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/*
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* AMD extended function 8000_0008h ecx info
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*/
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#define AMDID_CMP_CORES 0x000000ff
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#define AMDID_CMP_CORES 0x000000ff
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/*
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* Model-specific registers for the i386 family
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*/
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#define MSR_P5_MC_ADDR 0x000
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#define MSR_P5_MC_TYPE 0x001
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#define MSR_TSC 0x010
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#define MSR_P5_MC_ADDR 0x000
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#define MSR_P5_MC_TYPE 0x001
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#define MSR_TSC 0x010
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#define MSR_P5_CESR 0x011
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#define MSR_P5_CTR0 0x012
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#define MSR_P5_CTR1 0x013
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#define MSR_IA32_PLATFORM_ID 0x017
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#define MSR_APICBASE 0x01b
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#define MSR_EBL_CR_POWERON 0x02a
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#define MSR_APICBASE 0x01b
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#define MSR_EBL_CR_POWERON 0x02a
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#define MSR_TEST_CTL 0x033
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#define MSR_BIOS_UPDT_TRIG 0x079
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#define MSR_BIOS_UPDT_TRIG 0x079
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#define MSR_BBL_CR_D0 0x088
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#define MSR_BBL_CR_D1 0x089
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#define MSR_BBL_CR_D2 0x08a
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#define MSR_BIOS_SIGN 0x08b
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#define MSR_PERFCTR0 0x0c1
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#define MSR_PERFCTR1 0x0c2
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#define MSR_MTRRcap 0x0fe
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#define MSR_BIOS_SIGN 0x08b
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#define MSR_PERFCTR0 0x0c1
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#define MSR_PERFCTR1 0x0c2
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#define MSR_MTRRcap 0x0fe
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#define MSR_BBL_CR_ADDR 0x116
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#define MSR_BBL_CR_DECC 0x118
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#define MSR_BBL_CR_CTL 0x119
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@ -185,47 +186,47 @@
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#define MSR_SYSENTER_CS_MSR 0x174
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#define MSR_SYSENTER_ESP_MSR 0x175
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#define MSR_SYSENTER_EIP_MSR 0x176
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#define MSR_MCG_CAP 0x179
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#define MSR_MCG_STATUS 0x17a
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#define MSR_MCG_CTL 0x17b
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#define MSR_EVNTSEL0 0x186
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#define MSR_EVNTSEL1 0x187
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#define MSR_THERM_CONTROL 0x19a
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#define MSR_THERM_INTERRUPT 0x19b
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#define MSR_THERM_STATUS 0x19c
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#define MSR_MCG_CAP 0x179
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#define MSR_MCG_STATUS 0x17a
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#define MSR_MCG_CTL 0x17b
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#define MSR_EVNTSEL0 0x186
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#define MSR_EVNTSEL1 0x187
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#define MSR_THERM_CONTROL 0x19a
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#define MSR_THERM_INTERRUPT 0x19b
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#define MSR_THERM_STATUS 0x19c
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#define MSR_IA32_MISC_ENABLE 0x1a0
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#define MSR_DEBUGCTLMSR 0x1d9
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#define MSR_LASTBRANCHFROMIP 0x1db
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#define MSR_LASTBRANCHTOIP 0x1dc
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#define MSR_LASTINTFROMIP 0x1dd
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#define MSR_LASTINTTOIP 0x1de
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#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
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#define MSR_MTRRVarBase 0x200
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#define MSR_MTRR64kBase 0x250
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#define MSR_MTRR16kBase 0x258
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#define MSR_MTRR4kBase 0x268
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#define MSR_PAT 0x277
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#define MSR_MTRRdefType 0x2ff
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#define MSR_MC0_CTL 0x400
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#define MSR_MC0_STATUS 0x401
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#define MSR_MC0_ADDR 0x402
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#define MSR_MC0_MISC 0x403
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#define MSR_MC1_CTL 0x404
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#define MSR_MC1_STATUS 0x405
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#define MSR_MC1_ADDR 0x406
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#define MSR_MC1_MISC 0x407
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#define MSR_MC2_CTL 0x408
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#define MSR_MC2_STATUS 0x409
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#define MSR_MC2_ADDR 0x40a
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#define MSR_MC2_MISC 0x40b
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#define MSR_MC3_CTL 0x40c
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#define MSR_MC3_STATUS 0x40d
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#define MSR_MC3_ADDR 0x40e
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#define MSR_MC3_MISC 0x40f
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#define MSR_MC4_CTL 0x410
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#define MSR_MC4_STATUS 0x411
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#define MSR_MC4_ADDR 0x412
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#define MSR_MC4_MISC 0x413
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#define MSR_DEBUGCTLMSR 0x1d9
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#define MSR_LASTBRANCHFROMIP 0x1db
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#define MSR_LASTBRANCHTOIP 0x1dc
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#define MSR_LASTINTFROMIP 0x1dd
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#define MSR_LASTINTTOIP 0x1de
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#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
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#define MSR_MTRRVarBase 0x200
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#define MSR_MTRR64kBase 0x250
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#define MSR_MTRR16kBase 0x258
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#define MSR_MTRR4kBase 0x268
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#define MSR_PAT 0x277
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#define MSR_MTRRdefType 0x2ff
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#define MSR_MC0_CTL 0x400
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#define MSR_MC0_STATUS 0x401
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#define MSR_MC0_ADDR 0x402
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#define MSR_MC0_MISC 0x403
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#define MSR_MC1_CTL 0x404
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#define MSR_MC1_STATUS 0x405
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#define MSR_MC1_ADDR 0x406
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#define MSR_MC1_MISC 0x407
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#define MSR_MC2_CTL 0x408
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#define MSR_MC2_STATUS 0x409
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#define MSR_MC2_ADDR 0x40a
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#define MSR_MC2_MISC 0x40b
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#define MSR_MC3_CTL 0x40c
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#define MSR_MC3_STATUS 0x40d
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#define MSR_MC3_ADDR 0x40e
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#define MSR_MC3_MISC 0x40f
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#define MSR_MC4_CTL 0x410
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#define MSR_MC4_STATUS 0x411
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#define MSR_MC4_ADDR 0x412
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#define MSR_MC4_MISC 0x413
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/*
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* Constants related to MSR's.
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@ -250,9 +251,9 @@
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/*
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* Constants related to MTRRs
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*/
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#define MTRR_N64K 8 /* numbers of fixed-size entries */
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#define MTRR_N16K 16
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#define MTRR_N4K 64
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#define MTRR_N64K 8 /* numbers of fixed-size entries */
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#define MTRR_N16K 16
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#define MTRR_N4K 64
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/* Performance Control Register (5x86 only). */
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#define PCR0 0x20
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@ -349,11 +350,11 @@
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#define RCR6 0xe2
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#define RCR7 0xe3
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#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
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#define RCR_RCE 0x01 /* Enables caching for ARR7. */
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#define RCR_WWO 0x02 /* Weak write ordering. */
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#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
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#define RCR_RCE 0x01 /* Enables caching for ARR7. */
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#define RCR_WWO 0x02 /* Weak write ordering. */
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#define RCR_WL 0x04 /* Weak locking. */
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#define RCR_WG 0x08 /* Write gathering. */
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#define RCR_WG 0x08 /* Write gathering. */
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#define RCR_WT 0x10 /* Write-through. */
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#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
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@ -832,7 +832,7 @@ printcpuinfo(void)
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"\006<b5>"
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"\007<b6>"
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"\010<b7>"
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"\011<b8>"
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"\011Prefetch" /* 3DNow! Prefetch/PrefetchW */
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"\012<b9>"
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"\013<b10>"
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"\014<b11>"
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@ -104,35 +104,36 @@
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#define CPUID_IA64 0x40000000
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#define CPUID_PBE 0x80000000
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#define CPUID2_SSE3 0x00000001
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#define CPUID2_MON 0x00000008
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#define CPUID2_DS_CPL 0x00000010
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#define CPUID2_VMX 0x00000020
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#define CPUID2_EST 0x00000080
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#define CPUID2_TM2 0x00000100
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#define CPUID2_SSSE3 0x00000200
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#define CPUID2_CNXTID 0x00000400
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#define CPUID2_CX16 0x00002000
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#define CPUID2_XTPR 0x00004000
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#define CPUID2_SSE3 0x00000001
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#define CPUID2_MON 0x00000008
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#define CPUID2_DS_CPL 0x00000010
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#define CPUID2_VMX 0x00000020
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#define CPUID2_EST 0x00000080
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#define CPUID2_TM2 0x00000100
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#define CPUID2_SSSE3 0x00000200
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#define CPUID2_CNXTID 0x00000400
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#define CPUID2_CX16 0x00002000
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#define CPUID2_XTPR 0x00004000
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/*
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* Important bits in the AMD extended cpuid flags
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*/
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#define AMDID_SYSCALL 0x00000800
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#define AMDID_MP 0x00080000
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#define AMDID_NX 0x00100000
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#define AMDID_EXT_MMX 0x00400000
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#define AMDID_FFXSR 0x01000000
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#define AMDID_RDTSCP 0x08000000
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#define AMDID_LM 0x20000000
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#define AMDID_EXT_3DNOW 0x40000000
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#define AMDID_3DNOW 0x80000000
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#define AMDID_SYSCALL 0x00000800
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#define AMDID_MP 0x00080000
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#define AMDID_NX 0x00100000
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#define AMDID_EXT_MMX 0x00400000
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#define AMDID_FFXSR 0x01000000
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#define AMDID_RDTSCP 0x08000000
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#define AMDID_LM 0x20000000
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#define AMDID_EXT_3DNOW 0x40000000
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#define AMDID_3DNOW 0x80000000
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#define AMDID2_LAHF 0x00000001
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#define AMDID2_CMP 0x00000002
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#define AMDID2_SVM 0x00000004
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#define AMDID2_EXT_APIC 0x00000008
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#define AMDID2_CR8 0x00000010
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#define AMDID2_LAHF 0x00000001
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#define AMDID2_CMP 0x00000002
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#define AMDID2_SVM 0x00000004
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#define AMDID2_EXT_APIC 0x00000008
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#define AMDID2_CR8 0x00000010
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#define AMDID2_PREFETCH 0x00000100
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/*
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* CPUID instruction 1 ebx info
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@ -145,29 +146,29 @@
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/*
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* AMD extended function 8000_0008h ecx info
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*/
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#define AMDID_CMP_CORES 0x000000ff
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#define AMDID_CMP_CORES 0x000000ff
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/*
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* Model-specific registers for the i386 family
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*/
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#define MSR_P5_MC_ADDR 0x000
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#define MSR_P5_MC_TYPE 0x001
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#define MSR_TSC 0x010
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#define MSR_P5_MC_ADDR 0x000
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#define MSR_P5_MC_TYPE 0x001
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#define MSR_TSC 0x010
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#define MSR_P5_CESR 0x011
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#define MSR_P5_CTR0 0x012
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#define MSR_P5_CTR1 0x013
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#define MSR_IA32_PLATFORM_ID 0x017
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#define MSR_APICBASE 0x01b
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#define MSR_EBL_CR_POWERON 0x02a
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#define MSR_APICBASE 0x01b
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#define MSR_EBL_CR_POWERON 0x02a
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#define MSR_TEST_CTL 0x033
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#define MSR_BIOS_UPDT_TRIG 0x079
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#define MSR_BIOS_UPDT_TRIG 0x079
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#define MSR_BBL_CR_D0 0x088
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#define MSR_BBL_CR_D1 0x089
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#define MSR_BBL_CR_D2 0x08a
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#define MSR_BIOS_SIGN 0x08b
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#define MSR_PERFCTR0 0x0c1
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#define MSR_PERFCTR1 0x0c2
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#define MSR_MTRRcap 0x0fe
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#define MSR_BIOS_SIGN 0x08b
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#define MSR_PERFCTR0 0x0c1
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#define MSR_PERFCTR1 0x0c2
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#define MSR_MTRRcap 0x0fe
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#define MSR_BBL_CR_ADDR 0x116
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#define MSR_BBL_CR_DECC 0x118
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#define MSR_BBL_CR_CTL 0x119
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@ -177,47 +178,47 @@
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#define MSR_SYSENTER_CS_MSR 0x174
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#define MSR_SYSENTER_ESP_MSR 0x175
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#define MSR_SYSENTER_EIP_MSR 0x176
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#define MSR_MCG_CAP 0x179
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#define MSR_MCG_STATUS 0x17a
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#define MSR_MCG_CTL 0x17b
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#define MSR_EVNTSEL0 0x186
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#define MSR_EVNTSEL1 0x187
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#define MSR_THERM_CONTROL 0x19a
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#define MSR_THERM_INTERRUPT 0x19b
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#define MSR_THERM_STATUS 0x19c
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#define MSR_MCG_CAP 0x179
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#define MSR_MCG_STATUS 0x17a
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#define MSR_MCG_CTL 0x17b
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#define MSR_EVNTSEL0 0x186
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#define MSR_EVNTSEL1 0x187
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#define MSR_THERM_CONTROL 0x19a
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#define MSR_THERM_INTERRUPT 0x19b
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#define MSR_THERM_STATUS 0x19c
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#define MSR_IA32_MISC_ENABLE 0x1a0
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#define MSR_DEBUGCTLMSR 0x1d9
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#define MSR_LASTBRANCHFROMIP 0x1db
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#define MSR_LASTBRANCHTOIP 0x1dc
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#define MSR_LASTINTFROMIP 0x1dd
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#define MSR_LASTINTTOIP 0x1de
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#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
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#define MSR_MTRRVarBase 0x200
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#define MSR_MTRR64kBase 0x250
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#define MSR_MTRR16kBase 0x258
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#define MSR_MTRR4kBase 0x268
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#define MSR_PAT 0x277
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#define MSR_MTRRdefType 0x2ff
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#define MSR_MC0_CTL 0x400
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#define MSR_MC0_STATUS 0x401
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#define MSR_MC0_ADDR 0x402
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#define MSR_MC0_MISC 0x403
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#define MSR_MC1_CTL 0x404
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#define MSR_MC1_STATUS 0x405
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#define MSR_MC1_ADDR 0x406
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#define MSR_MC1_MISC 0x407
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#define MSR_MC2_CTL 0x408
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#define MSR_MC2_STATUS 0x409
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#define MSR_MC2_ADDR 0x40a
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#define MSR_MC2_MISC 0x40b
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#define MSR_MC3_CTL 0x40c
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#define MSR_MC3_STATUS 0x40d
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#define MSR_MC3_ADDR 0x40e
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#define MSR_MC3_MISC 0x40f
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#define MSR_MC4_CTL 0x410
|
||||
#define MSR_MC4_STATUS 0x411
|
||||
#define MSR_MC4_ADDR 0x412
|
||||
#define MSR_MC4_MISC 0x413
|
||||
#define MSR_DEBUGCTLMSR 0x1d9
|
||||
#define MSR_LASTBRANCHFROMIP 0x1db
|
||||
#define MSR_LASTBRANCHTOIP 0x1dc
|
||||
#define MSR_LASTINTFROMIP 0x1dd
|
||||
#define MSR_LASTINTTOIP 0x1de
|
||||
#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
|
||||
#define MSR_MTRRVarBase 0x200
|
||||
#define MSR_MTRR64kBase 0x250
|
||||
#define MSR_MTRR16kBase 0x258
|
||||
#define MSR_MTRR4kBase 0x268
|
||||
#define MSR_PAT 0x277
|
||||
#define MSR_MTRRdefType 0x2ff
|
||||
#define MSR_MC0_CTL 0x400
|
||||
#define MSR_MC0_STATUS 0x401
|
||||
#define MSR_MC0_ADDR 0x402
|
||||
#define MSR_MC0_MISC 0x403
|
||||
#define MSR_MC1_CTL 0x404
|
||||
#define MSR_MC1_STATUS 0x405
|
||||
#define MSR_MC1_ADDR 0x406
|
||||
#define MSR_MC1_MISC 0x407
|
||||
#define MSR_MC2_CTL 0x408
|
||||
#define MSR_MC2_STATUS 0x409
|
||||
#define MSR_MC2_ADDR 0x40a
|
||||
#define MSR_MC2_MISC 0x40b
|
||||
#define MSR_MC3_CTL 0x40c
|
||||
#define MSR_MC3_STATUS 0x40d
|
||||
#define MSR_MC3_ADDR 0x40e
|
||||
#define MSR_MC3_MISC 0x40f
|
||||
#define MSR_MC4_CTL 0x410
|
||||
#define MSR_MC4_STATUS 0x411
|
||||
#define MSR_MC4_ADDR 0x412
|
||||
#define MSR_MC4_MISC 0x413
|
||||
|
||||
/*
|
||||
* Constants related to MSR's.
|
||||
@ -242,9 +243,9 @@
|
||||
/*
|
||||
* Constants related to MTRRs
|
||||
*/
|
||||
#define MTRR_N64K 8 /* numbers of fixed-size entries */
|
||||
#define MTRR_N16K 16
|
||||
#define MTRR_N4K 64
|
||||
#define MTRR_N64K 8 /* numbers of fixed-size entries */
|
||||
#define MTRR_N16K 16
|
||||
#define MTRR_N4K 64
|
||||
|
||||
/*
|
||||
* Cyrix configuration registers, accessible as IO ports.
|
||||
@ -277,7 +278,7 @@
|
||||
#define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
|
||||
#define CCR2_WT1 0x10 /* WT region 1 */
|
||||
#define CCR2_WPR1 0x10 /* Write-protect region 1 */
|
||||
#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
|
||||
#define CCR2_BARB 0x20 /* Flushes write-back cache when entering
|
||||
hold state. */
|
||||
#define CCR2_BWRT 0x40 /* Enables burst write cycles */
|
||||
#define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
|
||||
@ -404,11 +405,11 @@
|
||||
#define RCR6 0xe2
|
||||
#define RCR7 0xe3
|
||||
|
||||
#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
|
||||
#define RCR_RCE 0x01 /* Enables caching for ARR7. */
|
||||
#define RCR_WWO 0x02 /* Weak write ordering. */
|
||||
#define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
|
||||
#define RCR_RCE 0x01 /* Enables caching for ARR7. */
|
||||
#define RCR_WWO 0x02 /* Weak write ordering. */
|
||||
#define RCR_WL 0x04 /* Weak locking. */
|
||||
#define RCR_WG 0x08 /* Write gathering. */
|
||||
#define RCR_WG 0x08 /* Write gathering. */
|
||||
#define RCR_WT 0x10 /* Write-through. */
|
||||
#define RCR_NLB 0x20 /* LBA# pin is not asserted. */
|
||||
|
||||
@ -418,40 +419,40 @@
|
||||
#define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
|
||||
|
||||
/* VIA ACE crypto featureset: for via_feature_rng */
|
||||
#define VIA_HAS_RNG 1 /* cpu has RNG */
|
||||
#define VIA_HAS_RNG 1 /* cpu has RNG */
|
||||
|
||||
/* VIA ACE crypto featureset: for via_feature_xcrypt */
|
||||
#define VIA_HAS_AES 1 /* cpu has AES */
|
||||
#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
|
||||
#define VIA_HAS_MM 4 /* cpu has RSA instructions */
|
||||
#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
|
||||
#define VIA_HAS_AES 1 /* cpu has AES */
|
||||
#define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
|
||||
#define VIA_HAS_MM 4 /* cpu has RSA instructions */
|
||||
#define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
|
||||
|
||||
/* Centaur Extended Feature flags */
|
||||
#define VIA_CPUID_HAS_RNG 0x000004
|
||||
#define VIA_CPUID_DO_RNG 0x000008
|
||||
#define VIA_CPUID_HAS_ACE 0x000040
|
||||
#define VIA_CPUID_DO_ACE 0x000080
|
||||
#define VIA_CPUID_HAS_ACE2 0x000100
|
||||
#define VIA_CPUID_DO_ACE2 0x000200
|
||||
#define VIA_CPUID_HAS_PHE 0x000400
|
||||
#define VIA_CPUID_DO_PHE 0x000800
|
||||
#define VIA_CPUID_HAS_PMM 0x001000
|
||||
#define VIA_CPUID_DO_PMM 0x002000
|
||||
#define VIA_CPUID_HAS_RNG 0x000004
|
||||
#define VIA_CPUID_DO_RNG 0x000008
|
||||
#define VIA_CPUID_HAS_ACE 0x000040
|
||||
#define VIA_CPUID_DO_ACE 0x000080
|
||||
#define VIA_CPUID_HAS_ACE2 0x000100
|
||||
#define VIA_CPUID_DO_ACE2 0x000200
|
||||
#define VIA_CPUID_HAS_PHE 0x000400
|
||||
#define VIA_CPUID_DO_PHE 0x000800
|
||||
#define VIA_CPUID_HAS_PMM 0x001000
|
||||
#define VIA_CPUID_DO_PMM 0x002000
|
||||
|
||||
/* VIA ACE xcrypt-* instruction context control options */
|
||||
#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
|
||||
#define VIA_CRYPT_CWLO_ALG_M 0x00000070
|
||||
#define VIA_CRYPT_CWLO_ALG_AES 0x00000000
|
||||
#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
|
||||
#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
|
||||
#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
|
||||
#define VIA_CRYPT_CWLO_NORMAL 0x00000000
|
||||
#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
|
||||
#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
|
||||
#define VIA_CRYPT_CWLO_DECRYPT 0x00000200
|
||||
#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
|
||||
#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
|
||||
#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
|
||||
#define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
|
||||
#define VIA_CRYPT_CWLO_ALG_M 0x00000070
|
||||
#define VIA_CRYPT_CWLO_ALG_AES 0x00000000
|
||||
#define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
|
||||
#define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
|
||||
#define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
|
||||
#define VIA_CRYPT_CWLO_NORMAL 0x00000000
|
||||
#define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
|
||||
#define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
|
||||
#define VIA_CRYPT_CWLO_DECRYPT 0x00000200
|
||||
#define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
|
||||
#define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
|
||||
#define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
|
||||
|
||||
#ifndef LOCORE
|
||||
static __inline u_char
|
||||
|
||||
Loading…
Reference in New Issue
Block a user