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Code Issues Releases Activity

Add support for 200Gb ethernet speeds to mlx5core.

Browse Source 
Submitted by:	slavash@
MFC after:	3 days
Sponsored by:	Mellanox Technologies
This commit is contained in:
Hans Petter Selasky 2019-05-08 10:54:54 +00:00
parent 6d1dc6524e
commit ac87880ac1
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=347299
6 changed files with 490 additions and 106 deletions
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6
sys/dev/mlx5/mlx5_core/mlx5_fw.c
View File

@ -221,6 +221,12 @@ int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
return err;
}
if (MLX5_CAP_GEN(dev, pcam_reg)) {
err = mlx5_get_pcam_reg(dev);
if (err)
return err;
}
err = mlx5_core_query_special_contexts(dev);
if (err)
return err;

12
sys/dev/mlx5/mlx5_core/mlx5_port.c
View File

@ -260,7 +260,7 @@ int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
EXPORT_SYMBOL(mlx5_query_port_eth_proto_oper);
int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
int proto_mask)
int proto_mask, bool ext)
{
u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0};
u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {0};
@ -268,10 +268,14 @@ int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
MLX5_SET(ptys_reg, in, local_port, 1);
MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
if (proto_mask == MLX5_PTYS_EN)
MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
else
if (proto_mask == MLX5_PTYS_EN) {
if (ext)
MLX5_SET(ptys_reg, in, ext_eth_proto_admin, proto_admin);
else
MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
} else {
MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
}
err = mlx5_core_access_reg(dev, in, sizeof(in), out,
sizeof(out), MLX5_REG_PTYS, 0, 1);

468
sys/dev/mlx5/mlx5_en/mlx5_en_main.c
View File

@ -47,117 +47,355 @@ struct mlx5e_channel_param {
struct mlx5e_cq_param tx_cq;
};
static const struct {
struct media {
u32 subtype;
u64 baudrate;
} mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
};
[MLX5E_1000BASE_CX_SGMII] = {
static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
[MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
.subtype = IFM_1000_CX_SGMII,
.baudrate = IF_Mbps(1000ULL),
},
[MLX5E_1000BASE_KX] = {
[MLX5E_1000BASE_KX][MLX5E_KX] = {
.subtype = IFM_1000_KX,
.baudrate = IF_Mbps(1000ULL),
},
[MLX5E_10GBASE_CX4] = {
[MLX5E_10GBASE_CX4][MLX5E_CX4] = {
.subtype = IFM_10G_CX4,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_KX4] = {
[MLX5E_10GBASE_KX4][MLX5E_KX4] = {
.subtype = IFM_10G_KX4,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_KR] = {
[MLX5E_10GBASE_KR][MLX5E_KR] = {
.subtype = IFM_10G_KR,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_20GBASE_KR2] = {
[MLX5E_20GBASE_KR2][MLX5E_KR2] = {
.subtype = IFM_20G_KR2,
.baudrate = IF_Gbps(20ULL),
},
[MLX5E_40GBASE_CR4] = {
[MLX5E_40GBASE_CR4][MLX5E_CR4] = {
.subtype = IFM_40G_CR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_40GBASE_KR4] = {
[MLX5E_40GBASE_KR4][MLX5E_KR4] = {
.subtype = IFM_40G_KR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_56GBASE_R4] = {
[MLX5E_56GBASE_R4][MLX5E_R] = {
.subtype = IFM_56G_R4,
.baudrate = IF_Gbps(56ULL),
},
[MLX5E_10GBASE_CR] = {
[MLX5E_10GBASE_CR][MLX5E_CR1] = {
.subtype = IFM_10G_CR1,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_SR] = {
[MLX5E_10GBASE_SR][MLX5E_SR] = {
.subtype = IFM_10G_SR,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_ER] = {
[MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
.subtype = IFM_10G_ER,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_40GBASE_SR4] = {
[MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
.subtype = IFM_10G_LR,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_40GBASE_SR4][MLX5E_SR4] = {
.subtype = IFM_40G_SR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_40GBASE_LR4] = {
[MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
.subtype = IFM_40G_LR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_100GBASE_CR4] = {
[MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
.subtype = IFM_40G_ER4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_100GBASE_CR4][MLX5E_CR4] = {
.subtype = IFM_100G_CR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_100GBASE_SR4] = {
[MLX5E_100GBASE_SR4][MLX5E_SR4] = {
.subtype = IFM_100G_SR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_100GBASE_KR4] = {
[MLX5E_100GBASE_KR4][MLX5E_KR4] = {
.subtype = IFM_100G_KR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_100GBASE_LR4] = {
[MLX5E_100GBASE_LR4][MLX5E_LR4] = {
.subtype = IFM_100G_LR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_100BASE_TX] = {
[MLX5E_100BASE_TX][MLX5E_TX] = {
.subtype = IFM_100_TX,
.baudrate = IF_Mbps(100ULL),
},
[MLX5E_1000BASE_T] = {
[MLX5E_1000BASE_T][MLX5E_T] = {
.subtype = IFM_1000_T,
.baudrate = IF_Mbps(1000ULL),
},
[MLX5E_10GBASE_T] = {
[MLX5E_10GBASE_T][MLX5E_T] = {
.subtype = IFM_10G_T,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_25GBASE_CR] = {
[MLX5E_25GBASE_CR][MLX5E_CR] = {
.subtype = IFM_25G_CR,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GBASE_KR] = {
[MLX5E_25GBASE_KR][MLX5E_KR] = {
.subtype = IFM_25G_KR,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GBASE_SR] = {
[MLX5E_25GBASE_SR][MLX5E_SR] = {
.subtype = IFM_25G_SR,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_50GBASE_CR2] = {
[MLX5E_50GBASE_CR2][MLX5E_CR2] = {
.subtype = IFM_50G_CR2,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GBASE_KR2] = {
[MLX5E_50GBASE_KR2][MLX5E_KR2] = {
.subtype = IFM_50G_KR2,
.baudrate = IF_Gbps(50ULL),
},
};
static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
[MLX5E_SGMII_100M][MLX5E_SGMII] = {
.subtype = IFM_100_SGMII,
.baudrate = IF_Mbps(100),
},
[MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
.subtype = IFM_1000_KX,
.baudrate = IF_Mbps(1000),
},
[MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
.subtype = IFM_1000_CX_SGMII,
.baudrate = IF_Mbps(1000),
},
[MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
.subtype = IFM_1000_CX,
.baudrate = IF_Mbps(1000),
},
[MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
.subtype = IFM_1000_LX,
.baudrate = IF_Mbps(1000),
},
[MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
.subtype = IFM_1000_SX,
.baudrate = IF_Mbps(1000),
},
[MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
.subtype = IFM_1000_T,
.baudrate = IF_Mbps(1000),
},
[MLX5E_5GBASE_R][MLX5E_T] = {
.subtype = IFM_5000_T,
.baudrate = IF_Mbps(5000),
},
[MLX5E_5GBASE_R][MLX5E_KR] = {
.subtype = IFM_5000_KR,
.baudrate = IF_Mbps(5000),
},
[MLX5E_5GBASE_R][MLX5E_KR1] = {
.subtype = IFM_5000_KR1,
.baudrate = IF_Mbps(5000),
},
[MLX5E_5GBASE_R][MLX5E_KR_S] = {
.subtype = IFM_5000_KR_S,
.baudrate = IF_Mbps(5000),
},
[MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
.subtype = IFM_10G_ER,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
.subtype = IFM_10G_KR,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
.subtype = IFM_10G_LR,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
.subtype = IFM_10G_SR,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
.subtype = IFM_10G_T,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
.subtype = IFM_10G_AOC,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
.subtype = IFM_10G_CR1,
.baudrate = IF_Gbps(10ULL),
},
[MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
.subtype = IFM_40G_CR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
.subtype = IFM_40G_KR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
.subtype = IFM_40G_LR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
.subtype = IFM_40G_SR4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
.subtype = IFM_40G_ER4,
.baudrate = IF_Gbps(40ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
.subtype = IFM_25G_CR,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
.subtype = IFM_25G_KR,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
.subtype = IFM_25G_SR,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
.subtype = IFM_25G_ACC,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
.subtype = IFM_25G_AOC,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
.subtype = IFM_25G_CR1,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
.subtype = IFM_25G_CR_S,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
.subtype = IFM_5000_KR1,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
.subtype = IFM_25G_KR_S,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
.subtype = IFM_25G_LR,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
.subtype = IFM_25G_T,
.baudrate = IF_Gbps(25ULL),
},
[MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
.subtype = IFM_50G_CR2,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
.subtype = IFM_50G_KR2,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
.subtype = IFM_50G_SR2,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
.subtype = IFM_50G_LR2,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
.subtype = IFM_50G_LR,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
.subtype = IFM_50G_SR,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
.subtype = IFM_50G_CP,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
.subtype = IFM_50G_FR,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
.subtype = IFM_50G_KR_PAM4,
.baudrate = IF_Gbps(50ULL),
},
[MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
.subtype = IFM_100G_CR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
.subtype = IFM_100G_KR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
.subtype = IFM_100G_LR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
.subtype = IFM_100G_SR4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
.subtype = IFM_100G_SR2,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
.subtype = IFM_100G_CP2,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
.subtype = IFM_100G_KR2_PAM4,
.baudrate = IF_Gbps(100ULL),
},
[MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
.subtype = IFM_200G_DR4,
.baudrate = IF_Gbps(200ULL),
},
[MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
.subtype = IFM_200G_LR4,
.baudrate = IF_Gbps(200ULL),
},
[MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
.subtype = IFM_200G_SR4,
.baudrate = IF_Gbps(200ULL),
},
[MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
.subtype = IFM_200G_FR4,
.baudrate = IF_Gbps(200ULL),
},
[MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
.subtype = IFM_200G_CR4_PAM4,
.baudrate = IF_Gbps(200ULL),
},
[MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
.subtype = IFM_200G_KR4_PAM4,
.baudrate = IF_Gbps(200ULL),
},
};
MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
static void
@ -169,7 +407,9 @@ mlx5e_update_carrier(struct mlx5e_priv *priv)
int error;
u8 port_state;
u8 is_er_type;
u8 i;
u8 i, j;
bool ext;
struct media media_entry = {};
port_state = mlx5_query_vport_state(mdev,
MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
@ -183,49 +423,58 @@ mlx5e_update_carrier(struct mlx5e_priv *priv)
return;
}
error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
error = mlx5_query_port_ptys(mdev, out, sizeof(out),
MLX5_PTYS_EN, 1);
if (error) {
priv->media_active_last = IFM_ETHER;
priv->ifp->if_baudrate = 1;
if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
__func__, error);
if_printf(priv->ifp, "%s: query port ptys failed: "
"0x%x\n", __func__, error);
return;
}
eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
if (mlx5e_mode_table[i].baudrate == 0)
continue;
if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
u32 subtype = mlx5e_mode_table[i].subtype;
ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
eth_proto_oper);
priv->ifp->if_baudrate =
mlx5e_mode_table[i].baudrate;
i = ilog2(eth_proto_oper);
switch (subtype) {
case IFM_10G_ER:
error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
if (error != 0) {
if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
__func__, error);
}
if (error != 0 || is_er_type == 0)
subtype = IFM_10G_LR;
break;
case IFM_40G_LR4:
error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
if (error != 0) {
if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
__func__, error);
}
if (error == 0 && is_er_type != 0)
subtype = IFM_40G_ER4;
break;
}
priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
media_entry = ext ? mlx5e_ext_mode_table[i][j] :
mlx5e_mode_table[i][j];
if (media_entry.baudrate != 0)
break;
}
}
if (media_entry.subtype == 0) {
if_printf(priv->ifp, "%s: Could not find operational "
"media subtype\n", __func__);
return;
}
switch (media_entry.subtype) {
case IFM_10G_ER:
error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
if (error != 0) {
if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
__func__, error);
}
if (error != 0 || is_er_type == 0)
media_entry.subtype = IFM_10G_LR;
break;
case IFM_40G_LR4:
error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
if (error != 0) {
if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
__func__, error);
}
if (error == 0 && is_er_type != 0)
media_entry.subtype = IFM_40G_ER4;
break;
}
priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
priv->ifp->if_baudrate = media_entry.baudrate;
if_link_state_change(priv->ifp, LINK_STATE_UP);
}
@ -242,10 +491,13 @@ mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
}
static u32
mlx5e_find_link_mode(u32 subtype)
mlx5e_find_link_mode(u32 subtype, bool ext)
{
u32 i;
u32 j;
u32 link_mode = 0;
u32 speeds_num = 0;
struct media media_entry = {};
switch (subtype) {
case IFM_10G_LR:
@ -256,11 +508,19 @@ mlx5e_find_link_mode(u32 subtype)
break;
}
for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
if (mlx5e_mode_table[i].baudrate == 0)
continue;
if (mlx5e_mode_table[i].subtype == subtype)
link_mode |= MLX5E_PROT_MASK(i);
speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
MLX5E_LINK_SPEEDS_NUMBER;
for (i = 0; i != speeds_num; i++) {
for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
media_entry = ext ? mlx5e_ext_mode_table[i][j] :
mlx5e_mode_table[i][j];
if (media_entry.baudrate == 0)
continue;
if (media_entry.subtype == subtype) {
link_mode |= MLX5E_PROT_MASK(i);
}
}
}
return (link_mode);
@ -286,7 +546,8 @@ mlx5e_set_port_pfc(struct mlx5e_priv *priv)
} else if (priv->params.rx_pauseframe_control ||
priv->params.tx_pauseframe_control) {
if_printf(priv->ifp,
"Global pauseframes must be disabled before enabling PFC.\n");
"Global pauseframes must be disabled before "
"enabling PFC.\n");
error = -EINVAL;
} else {
error = mlx5e_set_port_pause_and_pfc(priv);
@ -301,9 +562,11 @@ mlx5e_media_change(struct ifnet *dev)
struct mlx5_core_dev *mdev = priv->mdev;
u32 eth_proto_cap;
u32 link_mode;
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
int was_opened;
int locked;
int error;
bool ext;
locked = PRIV_LOCKED(priv);
if (!locked)
@ -313,14 +576,21 @@ mlx5e_media_change(struct ifnet *dev)
error = EINVAL;
goto done;
}
link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
/* query supported capabilities */
error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
error = mlx5_query_port_ptys(mdev, out, sizeof(out),
MLX5_PTYS_EN, 1);
if (error != 0) {
if_printf(dev, "Query port media capability failed\n");
goto done;
}
ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
/* query supported capabilities */
eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
eth_proto_capability);
/* check for autoselect */
if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
link_mode = eth_proto_cap;
@ -357,7 +627,7 @@ mlx5e_media_change(struct ifnet *dev)
/* reconfigure the hardware */
mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
error = -mlx5e_set_port_pause_and_pfc(priv);
if (was_opened)
mlx5_set_port_status(mdev, MLX5_PORT_UP);
@ -3760,13 +4030,18 @@ mlx5e_create_ifp(struct mlx5_core_dev *mdev)
struct ifnet *ifp;
struct mlx5e_priv *priv;
u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
u8 connector_type;
struct sysctl_oid_list *child;
int ncv = mdev->priv.eq_table.num_comp_vectors;
char unit[16];
struct pfil_head_args pa;
int err;
int i;
int i,j;
u32 eth_proto_cap;
u32 out[MLX5_ST_SZ_DW(ptys_reg)];
bool ext = 0;
u32 speeds_num;
struct media media_entry = {};
if (mlx5e_check_required_hca_cap(mdev)) {
mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
@ -3919,28 +4194,41 @@ mlx5e_create_ifp(struct mlx5_core_dev *mdev)
/* setup default pauseframes configuration */
mlx5e_setup_pauseframes(priv);
err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
if (err) {
/* Setup supported medias */
//TODO: If we failed to query ptys is it ok to proceed??
if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
ext = MLX5_CAP_PCAM_FEATURE(mdev,
ptys_extended_ethernet);
eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
eth_proto_capability);
if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
connector_type = MLX5_GET(ptys_reg, out,
connector_type);
} else {
eth_proto_cap = 0;
if_printf(ifp, "%s: Query port media capability failed, %d\n",
__func__, err);
if_printf(ifp, "%s: Query port media capability failed,"
" %d\n", __func__, err);
}
/* Setup supported medias */
ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
mlx5e_media_change, mlx5e_media_status);
for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
if (mlx5e_mode_table[i].baudrate == 0)
continue;
if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
ifmedia_add(&priv->media,
mlx5e_mode_table[i].subtype |
IFM_ETHER, 0, NULL);
ifmedia_add(&priv->media,
mlx5e_mode_table[i].subtype |
IFM_ETHER | IFM_FDX |
IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
for (i = 0; i != speeds_num; i++) {
for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
media_entry = ext ? mlx5e_ext_mode_table[i][j] :
mlx5e_mode_table[i][j];
if (media_entry.baudrate == 0)
continue;
if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
ifmedia_add(&priv->media,
media_entry.subtype |
IFM_ETHER, 0, NULL);
ifmedia_add(&priv->media,
media_entry.subtype |
IFM_ETHER | IFM_FDX |
IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
}
}
}

4
sys/dev/mlx5/mlx5_ib/mlx5_ib_main.c
View File

@ -180,7 +180,7 @@ static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR):
*active_width = IB_WIDTH_1X;
*active_speed = IB_SPEED_QDR;
break;
@ -193,7 +193,7 @@ static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4):
*active_width = IB_WIDTH_4X;
*active_speed = IB_SPEED_QDR;
break;

22
sys/dev/mlx5/mlx5_ifc.h
View File

@ -7881,28 +7881,29 @@ struct mlx5_ifc_ptys_reg_bits {
u8 reserved_3[0xc];
u8 data_rate_oper[0x10];
u8 fc_proto_capability[0x20];
u8 ext_eth_proto_capability[0x20];
u8 eth_proto_capability[0x20];
u8 ib_link_width_capability[0x10];
u8 ib_proto_capability[0x10];
u8 fc_proto_admin[0x20];
u8 ext_eth_proto_admin[0x20];
u8 eth_proto_admin[0x20];
u8 ib_link_width_admin[0x10];
u8 ib_proto_admin[0x10];
u8 fc_proto_oper[0x20];
u8 ext_eth_proto_oper[0x20];
u8 eth_proto_oper[0x20];
u8 ib_link_width_oper[0x10];
u8 ib_proto_oper[0x10];
u8 reserved_4[0x20];
u8 reserved_4[0x1c];
u8 connector_type[0x4];
u8 eth_proto_lp_advertise[0x20];
@ -8601,8 +8602,17 @@ struct mlx5_ifc_qcam_reg_bits {
};
struct mlx5_ifc_pcam_enhanced_features_bits {
u8 reserved_at_0[0x7e];
u8 reserved_at_0[0x6d];
u8 rx_icrc_encapsulated_counter[0x1];
u8 reserved_at_6e[0x4];
u8 ptys_extended_ethernet[0x1];
u8 reserved_at_73[0x3];
u8 pfcc_mask[0x1];
u8 reserved_at_77[0x3];
u8 per_lane_error_counters[0x1];
u8 rx_buffer_fullness_counters[0x1];
u8 ptys_connector_type[0x1];
u8 reserved_at_7d[0x1];
u8 ppcnt_discard_group[0x1];
u8 ppcnt_statistical_group[0x1];
};

84
sys/dev/mlx5/port.h
View File

@ -58,7 +58,7 @@ enum mlx5_an_status {
#define MLX5_I2C_ADDR_HIGH 0x51
#define MLX5_EEPROM_PAGE_LENGTH 256
enum mlx5e_link_mode {
enum mlx5e_link_speed {
MLX5E_1000BASE_CX_SGMII = 0,
MLX5E_1000BASE_KX = 1,
MLX5E_10GBASE_CX4 = 2,
@ -70,9 +70,9 @@ enum mlx5e_link_mode {
MLX5E_56GBASE_R4 = 8,
MLX5E_10GBASE_CR = 12,
MLX5E_10GBASE_SR = 13,
MLX5E_10GBASE_ER = 14,
MLX5E_10GBASE_ER_LR = 14,
MLX5E_40GBASE_SR4 = 15,
MLX5E_40GBASE_LR4 = 16,
MLX5E_40GBASE_LR4_ER4 = 16,
MLX5E_50GBASE_SR2 = 18,
MLX5E_100GBASE_CR4 = 20,
MLX5E_100GBASE_SR4 = 21,
@ -86,6 +86,78 @@ enum mlx5e_link_mode {
MLX5E_25GBASE_SR = 29,
MLX5E_50GBASE_CR2 = 30,
MLX5E_50GBASE_KR2 = 31,
MLX5E_LINK_SPEEDS_NUMBER,
};
enum mlx5e_ext_link_speed {
MLX5E_SGMII_100M = 0,
MLX5E_1000BASE_X_SGMII = 1,
MLX5E_5GBASE_R = 3,
MLX5E_10GBASE_XFI_XAUI_1 = 4,
MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5,
MLX5E_25GAUI_1_25GBASE_CR_KR = 6,
MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7,
MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9,
MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10,
MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12,
MLX5E_400GAUI_8 = 15,
MLX5E_EXT_LINK_SPEEDS_NUMBER,
};
enum mlx5e_link_mode {
MLX5E_ACC,
MLX5E_AOC,
MLX5E_AUI,
MLX5E_AUI_AC,
MLX5E_AUI2,
MLX5E_AUI2_AC,
MLX5E_AUI4,
MLX5E_AUI4_AC,
MLX5E_CAUI2,
MLX5E_CAUI2_AC,
MLX5E_CAUI4,
MLX5E_CAUI4_AC,
MLX5E_CP,
MLX5E_CP2,
MLX5E_CR,
MLX5E_CR_S,
MLX5E_CR1,
MLX5E_CR2,
MLX5E_CR4,
MLX5E_CR_PAM4,
MLX5E_CR4_PAM4,
MLX5E_CX4,
MLX5E_CX,
MLX5E_CX_SGMII,
MLX5E_DR,
MLX5E_DR4,
MLX5E_ER,
MLX5E_ER4,
MLX5E_FR,
MLX5E_FR4,
MLX5E_KR,
MLX5E_KR1,
MLX5E_KR_PAM4,
MLX5E_KR_S,
MLX5E_KR2,
MLX5E_KR2_PAM4,
MLX5E_KR4,
MLX5E_KR4_PAM4,
MLX5E_KX,
MLX5E_KX4,
MLX5E_LR,
MLX5E_LR2,
MLX5E_LR4,
MLX5E_LX,
MLX5E_R,
MLX5E_SGMII,
MLX5E_SR,
MLX5E_SR2,
MLX5E_SR4,
MLX5E_SX,
MLX5E_T,
MLX5E_TX,
MLX5E_LINK_MODES_NUMBER,
};
@ -113,6 +185,10 @@ enum mlx5_qpts_trust_state {
#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
#define MLX5_GET_ETH_PROTO(reg, out, ext, field) \
((ext) ? MLX5_GET(reg, out, ext_##field) : \
MLX5_GET(reg, out, field))
int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
int ptys_size, int proto_mask, u8 local_port);
@ -127,7 +203,7 @@ int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
u32 *proto_oper, u8 local_port);
int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
int proto_mask);
int proto_mask, bool ext);
int mlx5_set_port_status(struct mlx5_core_dev *dev,
enum mlx5_port_status status);
int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);