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o A divisor of 0 is perfectly valid. Reserve -1 for an invalid

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divisor. This allows us to set the line speed to the maximum
   of 1/4 of the device clock.
o  Disable the baudrate generator before programming the line
   settings, including baudrate, and enable it afterwards.
This commit is contained in:
Marcel Moolenaar 2006-05-12 23:24:45 +00:00
parent cb9dec9ec1
commit ace86f3f27
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=158504
1 changed files with 15 additions and 7 deletions
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22
sys/dev/uart/uart_dev_z8530.c
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@ -68,11 +68,11 @@ z8530_divisor(int rclk, int baudrate)
int act_baud, divisor, error;
if (baudrate == 0)
return (0);
return (-1);
divisor = (rclk + baudrate) / (baudrate << 1) - 2;
if (divisor < 0 || divisor >= 65536)
return (0);
return (-1);
act_baud = rclk / 2 / (divisor + 2);
/* 10 times error in percent: */
@ -80,7 +80,7 @@ z8530_divisor(int rclk, int baudrate)
/* 3.0% maximum error tolerance: */
if (error < -30 || error > 30)
return (0);
return (-1);
return (divisor);
}
@ -117,11 +117,17 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
default: return (EINVAL);
}
/* Set baudrate. */
if (baudrate > 0) {
divisor = z8530_divisor(bas->rclk, baudrate);
if (divisor == 0)
if (divisor == -1)
return (EINVAL);
} else
divisor = -1;
uart_setmreg(bas, WR_MCB2, MCB2_PCLK);
uart_barrier(bas);
if (divisor >= 0) {
uart_setmreg(bas, WR_TCL, divisor & 0xff);
uart_barrier(bas);
uart_setmreg(bas, WR_TCH, (divisor >> 8) & 0xff);
@ -134,6 +140,8 @@ z8530_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
uart_barrier(bas);
uart_setmreg(bas, WR_TPC, tpc);
uart_barrier(bas);
uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
uart_barrier(bas);
*tpcp = tpc;
return (0);
}
@ -157,9 +165,9 @@ z8530_setup(struct uart_bas *bas, int baudrate, int databits, int stopbits,
break;
}
uart_barrier(bas);
/* Set clock sources and enable BRG. */
/* Set clock sources. */
uart_setmreg(bas, WR_CMC, CMC_RC_BRG | CMC_TC_BRG);
uart_setmreg(bas, WR_MCB2, MCB2_PCLK | MCB2_BRGE);
uart_setmreg(bas, WR_MCB2, MCB2_PCLK);
uart_barrier(bas);
/* Set data encoding. */
uart_setmreg(bas, WR_MCB1, MCB1_NRZ);