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Next-to-leading-order perturbation of synchronization operations for
switching the user segment register. All races should now be closed and a minimum of pipelines flushes be required to close them.
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parent
3b18190fe9
commit
ad6b3047a4
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=214607
@ -117,9 +117,9 @@ set_user_sr(pmap_t pm, const void *addr)
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if (curthread->td_pcb->pcb_cpu.aim.usr_vsid == vsid)
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return;
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__asm __volatile ("sync; mtsr %0,%1; sync; isync" :: "n"(USER_SR),
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"r"(vsid));
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__asm __volatile("isync");
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curthread->td_pcb->pcb_cpu.aim.usr_vsid = vsid;
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__asm __volatile("mtsr %0,%1; isync" :: "n"(USER_SR), "r"(vsid));
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}
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#endif
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@ -89,7 +89,6 @@ ENTRY(cpu_switch)
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mflr %r16 /* Save the link register */
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stw %r16,PCB_LR(%r6)
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mfsr %r16,USER_SR /* Save USER_SR for copyin/out */
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isync
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stw %r16,PCB_AIM_USR_VSID(%r6)
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stw %r1,PCB_SP(%r6) /* Save the stack pointer */
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stw %r2,PCB_TOC(%r6) /* Save the TOC pointer */
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@ -162,6 +161,7 @@ blocked_loop:
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lwz %r5,PCB_LR(%r3) /* Load the link register */
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mtlr %r5
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lwz %r5,PCB_AIM_USR_VSID(%r3) /* Load the USER_SR segment reg */
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isync
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mtsr USER_SR,%r5
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isync
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lwz %r1,PCB_SP(%r3) /* Load the stack pointer */
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@ -113,7 +113,6 @@ ENTRY(cpu_switch)
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li %r15,0 /* Save user segment for copyin/out */
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li %r16,USER_SLB_SLOT
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slbmfev %r15, %r16
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isync
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std %r15,PCB_AIM_USR_VSID(%r6)
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mr %r14,%r3 /* Copy the old thread ptr... */
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@ -222,6 +221,7 @@ blocked_loop:
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ori %r5,%r5,USER_ADDR@highera
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sldi %r5,%r5,32
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oris %r5,%r5,USER_ADDR@ha
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isync
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slbie %r5
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lis %r6,USER_SLB_SLBE@highesta
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ori %r6,%r6,USER_SLB_SLBE@highera
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@ -230,8 +230,8 @@ blocked_loop:
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ori %r6,%r6,USER_SLB_SLBE@l
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ld %r5,PCB_AIM_USR_VSID(%r3)
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slbmte %r5,%r6
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isync
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/*
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* Perform a dummy stdcx. to clear any reservations we may have
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* inherited from the previous thread. It doesn't matter if the
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