mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-01 12:19:28 +00:00
Add platform DMA support to SDHCI driver for BCM2835
Submitted by: Daisuke Aoyama <aoyama at peach.ne.jp> Reviewed by: ian@
This commit is contained in:
Oleksandr Tymoshenko
parent
cdafe74e84
commit
adc99a8aa6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=247497
@ -67,8 +67,13 @@ __FBSDID("$FreeBSD$");
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#include <dev/sdhci/sdhci.h>
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#include "sdhci_if.h"
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#include "bcm2835_dma.h"
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#include "bcm2835_vcbus.h"
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#define BCM2835_DEFAULT_SDHCI_FREQ 50
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#define BCM_SDHCI_BUFFER_SIZE 512
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#define DEBUG
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#ifdef DEBUG
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@ -85,9 +90,11 @@ __FBSDID("$FreeBSD$");
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*/
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static int bcm2835_sdhci_min_freq = 400000;
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static int bcm2835_sdhci_hs = 1;
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static int bcm2835_sdhci_pio_mode = 0;
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TUNABLE_INT("hw.bcm2835.sdhci.min_freq", &bcm2835_sdhci_min_freq);
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TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
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TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
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struct bcm_sdhci_dmamap_arg {
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bus_addr_t sc_dma_busaddr;
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@ -111,23 +118,41 @@ struct bcm_sdhci_softc {
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int sc_xfer_done;
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int sc_bus_busy;
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struct sdhci_slot sc_slot;
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int sc_dma_inuse;
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int sc_dma_ch;
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bus_dma_tag_t sc_dma_tag;
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bus_dmamap_t sc_dma_map;
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void *sc_dma_buffer;
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vm_paddr_t sc_dma_buffer_phys;
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vm_paddr_t sc_sdhci_buffer_phys;;
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};
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#define SD_MAX_BLOCKSIZE 1024
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/* XXX */
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static int bcm_sdhci_probe(device_t);
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static int bcm_sdhci_attach(device_t);
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static int bcm_sdhci_detach(device_t);
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static void bcm_sdhci_intr(void *);
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static int bcm_sdhci_get_ro(device_t, device_t);
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static void bcm_sdhci_dma_intr(int ch, void *arg);
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#define bcm_sdhci_lock(_sc) \
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mtx_lock(&_sc->sc_mtx);
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#define bcm_sdhci_unlock(_sc) \
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mtx_unlock(&_sc->sc_mtx);
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static void
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bcm_dmamap_cb(void *arg, bus_dma_segment_t *segs,
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int nseg, int err)
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{
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bus_addr_t *addr;
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if (err)
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return;
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addr = (bus_addr_t*)arg;
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*addr = segs[0].ds_addr;
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}
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static int
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bcm_sdhci_probe(device_t dev)
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{
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@ -146,9 +171,13 @@ bcm_sdhci_attach(device_t dev)
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phandle_t node;
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pcell_t cell;
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int default_freq;
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void *buffer;
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vm_paddr_t buffer_phys;
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void *va;
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sc->sc_dev = dev;
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sc->sc_req = NULL;
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err = 0;
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default_freq = BCM2835_DEFAULT_SDHCI_FREQ;
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node = ofw_bus_get_node(sc->sc_dev);
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@ -191,6 +220,9 @@ bcm_sdhci_attach(device_t dev)
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goto fail;
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}
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if (!bcm2835_sdhci_pio_mode)
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sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
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sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
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if (bcm2835_sdhci_hs)
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sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
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@ -201,6 +233,61 @@ bcm_sdhci_attach(device_t dev)
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sdhci_init_slot(dev, &sc->sc_slot, 0);
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sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST1);
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if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
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sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_FAST2);
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if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
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sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
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if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
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goto fail;
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bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
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/* Allocate DMA buffers */
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err = bus_dma_tag_create(bus_get_dma_tag(dev),
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1, 0, BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR, NULL, NULL,
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BCM_SDHCI_BUFFER_SIZE, 1, BCM_SDHCI_BUFFER_SIZE,
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BUS_DMA_ALLOCNOW, NULL, NULL,
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&sc->sc_dma_tag);
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if (err) {
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device_printf(dev, "failed allocate DMA tag");
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goto fail;
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}
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err = bus_dmamem_alloc(sc->sc_dma_tag, &buffer,
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BUS_DMA_WAITOK | BUS_DMA_COHERENT| BUS_DMA_ZERO,
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&sc->sc_dma_map);
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if (err) {
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device_printf(dev, "cannot allocate DMA memory\n");
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goto fail;
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}
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err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, buffer,
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BCM_SDHCI_BUFFER_SIZE, bcm_dmamap_cb, &buffer_phys,
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BUS_DMA_WAITOK);
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if (err) {
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device_printf(dev, "cannot load DMA memory\n");
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goto fail;
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}
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/*
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* Sanity check: two least bits of address should be zero
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*/
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if ((uintptr_t)buffer & 3) {
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device_printf(dev,
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"DMA address is not word-aligned\n");
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goto fail;
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}
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sc->sc_dma_buffer = buffer;
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sc->sc_dma_buffer_phys = buffer_phys;
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va = (void*)rman_get_start(sc->sc_mem_res);
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sc->sc_sdhci_buffer_phys =
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pmap_kextract((vm_offset_t)va) + SDHCI_BUFFER;
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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@ -354,6 +441,211 @@ bcm_sdhci_min_freq(device_t dev, struct sdhci_slot *slot)
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return bcm2835_sdhci_min_freq;
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}
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static void
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bcm_sdhci_dma_intr(int ch, void *arg)
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{
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struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
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struct sdhci_slot *slot = &sc->sc_slot;
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uint32_t reg, mask;
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void *buffer;
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size_t len;
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int left;
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mtx_lock(&slot->mtx);
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/* copy DMA buffer to VA if READ */
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len = bcm_dma_length(sc->sc_dma_ch);
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if (slot->curcmd->data->flags & MMC_DATA_READ) {
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bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
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BUS_DMASYNC_POSTREAD);
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mask = SDHCI_INT_DATA_AVAIL;
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/* all dma data in single or contiguous page */
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buffer = (uint8_t*)(slot->curcmd->data->data) + slot->offset;
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memcpy(buffer, sc->sc_dma_buffer, len);
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} else {
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bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
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BUS_DMASYNC_POSTWRITE);
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mask = SDHCI_INT_SPACE_AVAIL;
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}
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slot->offset += len;
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sc->sc_dma_inuse = 0;
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left = min(BCM_SDHCI_BUFFER_SIZE,
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slot->curcmd->data->len - slot->offset);
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/* DATA END? */
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reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS);
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if (reg & SDHCI_INT_DATA_END) {
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/* ACK for all outstanding interrupts */
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bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg);
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/* enable INT */
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slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL
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| SDHCI_INT_DATA_END;
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bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
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slot->intmask);
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/* finish this data */
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sdhci_finish_data(slot);
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}
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else {
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/* already available? */
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if (reg & mask) {
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sc->sc_dma_inuse = 1;
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/* ACK for DATA_AVAIL or SPACE_AVAIL */
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bcm_sdhci_write_4(slot->bus, slot,
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SDHCI_INT_STATUS, mask);
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/* continue next DMA transfer */
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if (slot->curcmd->data->flags & MMC_DATA_READ) {
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bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
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BUS_DMASYNC_PREREAD);
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/* DMA start */
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if (bcm_dma_start(sc->sc_dma_ch,
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sc->sc_sdhci_buffer_phys,
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sc->sc_dma_buffer_phys, left) != 0)
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device_printf(sc->sc_dev, "failed DMA start\n");
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} else {
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buffer = (char*)slot->curcmd->data->data + slot->offset;
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memcpy(sc->sc_dma_buffer, buffer, left);
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bus_dmamap_sync(sc->sc_dma_tag,
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sc->sc_dma_map, BUS_DMASYNC_PREWRITE);
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/* DMA start */
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if (bcm_dma_start(sc->sc_dma_ch,
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sc->sc_dma_buffer_phys,
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sc->sc_sdhci_buffer_phys, left) != 0)
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device_printf(sc->sc_dev, "failed DMA start\n");
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}
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} else {
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/* wait for next data by INT */
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/* enable INT */
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slot->intmask |= SDHCI_INT_DATA_AVAIL |
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SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END;
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bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
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slot->intmask);
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}
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}
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mtx_unlock(&slot->mtx);
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}
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static void
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bcm_sdhci_read_dma(struct sdhci_slot *slot)
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{
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struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
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size_t left;
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if (sc->sc_dma_inuse) {
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device_printf(sc->sc_dev, "DMA in use\n");
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return;
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}
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sc->sc_dma_inuse = 1;
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left = min(BCM_SDHCI_BUFFER_SIZE,
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slot->curcmd->data->len - slot->offset);
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KASSERT((left & 3) == 0,
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("%s: len = %d, not word-aligned", __func__, left));
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bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
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BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
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bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
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BCM_DMA_INC_ADDR,
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(left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
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bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
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BUS_DMASYNC_PREREAD);
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/* DMA start */
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if (bcm_dma_start(sc->sc_dma_ch, sc->sc_sdhci_buffer_phys,
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sc->sc_dma_buffer_phys, left) != 0)
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device_printf(sc->sc_dev, "failed DMA start\n");
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}
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static void
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bcm_sdhci_write_dma(struct sdhci_slot *slot)
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{
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struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
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char *buffer;
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size_t left;
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if (sc->sc_dma_inuse) {
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device_printf(sc->sc_dev, "DMA in use\n");
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return;
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}
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sc->sc_dma_inuse = 1;
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left = min(BCM_SDHCI_BUFFER_SIZE,
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slot->curcmd->data->len - slot->offset);
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KASSERT((left & 3) == 0,
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("%s: len = %d, not word-aligned", __func__, left));
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buffer = (char*)slot->curcmd->data->data + slot->offset;
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memcpy(sc->sc_dma_buffer, buffer, left);
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bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
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BCM_DMA_INC_ADDR,
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(left & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT);
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bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC,
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BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
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bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
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BUS_DMASYNC_PREWRITE);
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/* DMA start */
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if (bcm_dma_start(sc->sc_dma_ch, sc->sc_dma_buffer_phys,
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sc->sc_sdhci_buffer_phys, left) != 0)
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device_printf(sc->sc_dev, "failed DMA start\n");
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}
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static int
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bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
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{
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size_t left;
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/* Do not use DMA for transfers less then block size */
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left = min(BCM_DMA_BLOCK_SIZE,
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slot->curcmd->data->len - slot->offset);
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if (left < BCM_DMA_BLOCK_SIZE)
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return (0);
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return (1);
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}
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static void
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bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
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uint32_t *intmask)
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{
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/* Disable INT */
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slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END);
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bcm_sdhci_write_4(dev, slot, SDHCI_SIGNAL_ENABLE, slot->intmask);
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/* DMA transfer FIFO 1KB */
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if (slot->curcmd->data->flags & MMC_DATA_READ)
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bcm_sdhci_read_dma(slot);
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else
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bcm_sdhci_write_dma(slot);
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}
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static void
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bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
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{
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sdhci_finish_data(slot);
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}
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static device_method_t bcm_sdhci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, bcm_sdhci_probe),
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@ -372,8 +664,12 @@ static device_method_t bcm_sdhci_methods[] = {
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DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
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DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
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/* SDHCI registers accessors */
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DEVMETHOD(sdhci_min_freq, bcm_sdhci_min_freq),
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/* Platform transfer methods */
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DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
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DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
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DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
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/* SDHCI registers accessors */
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DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
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DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
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DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
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