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Introduce XHCI support for MT7621 SoC
Tested on a MT7621 board, similar to the WiTi board. More testing will be required to confirm everything is fine, but things look good so far. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5885
This commit is contained in:
Stanislav Galabov
parent
1e7745b401
commit
b37b38e9ab
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=297716
298
sys/mips/mediatek/mtk_xhci.c
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298
sys/mips/mediatek/mtk_xhci.c
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@ -0,0 +1,298 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*-
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* Copyright (c) 2015 Stanislav Galabov. All rights reserved.
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* Copyright (c) 2010,2011 Aleksandr Rybalko. All rights reserved.
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* Copyright (c) 2007-2008 Hans Petter Selasky. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/stdint.h>
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#include <sys/stddef.h>
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#include <sys/param.h>
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#include <sys/queue.h>
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/condvar.h>
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#include <sys/sysctl.h>
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#include <sys/sx.h>
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#include <sys/unistd.h>
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#include <sys/callout.h>
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#include <sys/malloc.h>
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#include <sys/priv.h>
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#include <sys/rman.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usb_core.h>
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#include <dev/usb/usb_busdma.h>
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#include <dev/usb/usb_process.h>
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#include <dev/usb/usb_util.h>
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#include <dev/usb/usb_controller.h>
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#include <dev/usb/usb_bus.h>
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#include <dev/usb/controller/xhci.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define XHCI_HC_DEVSTR "MTK USB 3.0 controller"
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static device_probe_t mtk_xhci_fdt_probe;
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static device_attach_t mtk_xhci_fdt_attach;
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static device_detach_t mtk_xhci_fdt_detach;
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static void mtk_xhci_fdt_init(device_t dev);
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static int
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mtk_xhci_fdt_probe(device_t self)
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{
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if (!ofw_bus_status_okay(self))
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return (ENXIO);
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if (!ofw_bus_is_compatible(self, "mtk,usb-xhci"))
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return (ENXIO);
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device_set_desc(self, XHCI_HC_DEVSTR);
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return (BUS_PROBE_DEFAULT);
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}
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static int
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mtk_xhci_fdt_attach(device_t self)
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{
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struct xhci_softc *sc = device_get_softc(self);
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int err;
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int rid;
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/* initialise some bus fields */
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sc->sc_bus.parent = self;
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sc->sc_bus.devices = sc->sc_devices;
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sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
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sc->sc_bus.dma_bits = 32;
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rid = 0;
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sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_io_res) {
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device_printf(self, "Could not map memory\n");
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goto error;
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}
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sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
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sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
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sc->sc_io_size = rman_get_size(sc->sc_io_res);
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mtk_xhci_fdt_init(self);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE);
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if (sc->sc_irq_res == NULL) {
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device_printf(self, "Could not allocate irq\n");
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goto error;
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}
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sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
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if (!(sc->sc_bus.bdev)) {
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device_printf(self, "Could not add USB device\n");
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goto error;
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}
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device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
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device_set_desc(sc->sc_bus.bdev, XHCI_HC_DEVSTR);
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sprintf(sc->sc_vendor, "Mediatek");
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err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl);
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if (err) {
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device_printf(self, "Could not setup irq, %d\n", err);
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sc->sc_intr_hdl = NULL;
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goto error;
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}
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err = xhci_init(sc, self, 1);
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if (err == 0)
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err = xhci_halt_controller(sc);
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if (err == 0)
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err = xhci_start_controller(sc);
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if (err == 0)
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err = device_probe_and_attach(sc->sc_bus.bdev);
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if (err) {
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device_printf(self, "USB init failed err=%d\n", err);
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goto error;
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}
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return (0);
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error:
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mtk_xhci_fdt_detach(self);
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return (ENXIO);
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}
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static int
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mtk_xhci_fdt_detach(device_t self)
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{
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struct xhci_softc *sc = device_get_softc(self);
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device_t bdev;
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int err;
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if (sc->sc_bus.bdev) {
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bdev = sc->sc_bus.bdev;
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device_detach(bdev);
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device_delete_child(self, bdev);
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}
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/* during module unload there are lots of children leftover */
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device_delete_children(self);
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if (sc->sc_irq_res && sc->sc_intr_hdl) {
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/*
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* only call xhci_detach() after xhci_init()
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*/
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xhci_uninit(sc);
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err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
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if (err)
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device_printf(self, "Could not tear down irq, %d\n",
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err);
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sc->sc_intr_hdl = NULL;
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}
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if (sc->sc_irq_res) {
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bus_release_resource(self, SYS_RES_IRQ, 0,
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sc->sc_irq_res);
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sc->sc_irq_res = NULL;
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}
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if (sc->sc_io_res) {
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bus_release_resource(self, SYS_RES_MEMORY, 0,
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sc->sc_io_res);
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sc->sc_io_res = NULL;
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}
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return (0);
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}
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static device_method_t mtk_xhci_fdt_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mtk_xhci_fdt_probe),
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DEVMETHOD(device_attach, mtk_xhci_fdt_attach),
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DEVMETHOD(device_detach, mtk_xhci_fdt_detach),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static driver_t mtk_xhci_fdt_driver = {
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.name = "xhci",
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.methods = mtk_xhci_fdt_methods,
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.size = sizeof(struct xhci_softc),
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};
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static devclass_t mtk_xhci_fdt_devclass;
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DRIVER_MODULE(xhci, simplebus, mtk_xhci_fdt_driver, mtk_xhci_fdt_devclass, 0,
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0);
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#define USB_HDMA_CFG 0x950
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#define USB_HDMA_CFG_MT7621_VAL 0x10E0E0C
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#define U3_LTSSM_TIMING_PARAM3 0x2514
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#define U3_LTSSM_TIMING_VAL 0x3E8012C
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#define SYNC_HS_EOF 0x938
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#define SYNC_HS_EOF_VAL 0x201F3
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#define USB_IP_SPAR0 0x107C8
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#define USB_IP_SPAR0_VAL 1
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#define U2_PHY_BASE_P0 0x10800
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#define U2_PHY_BASE_P1 0x11000
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#define U2_PHYD_CR1 0x64
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#define U2_PHYD_CR1_MASK (3<<18)
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#define U2_PHYD_CR1_VAL (1<<18)
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#define USB_IP_PW_CTRL 0x10700
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#define USB_IP_PW_CTRL_1 0x10704
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#define USB_IP_CAP 0x10724
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#define USB_U3_CTRL(p) (0x10730 + ((p) * 0x08))
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#define USB_U2_CTRL(p) (0x10750 + ((p) * 0x08))
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#define USB_IP_SW_RST (1 << 0)
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#define USB_IP_PDN (1 << 0)
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#define USB_PORT_DIS (1 << 0)
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#define USB_PORT_PDN (1 << 1)
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#define U3_PORT_NUM(p) (p & 0xFF)
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#define U2_PORT_NUM(p) ((p>>8) & 0xFF)
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#define RD4(_sc, _reg) bus_read_4((_sc)->sc_io_res, (_reg))
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#define WR4(_sc, _reg, _val) bus_write_4((_sc)->sc_io_res, (_reg), (_val))
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#define CLRSET4(_sc, _reg, _clr, _set) \
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WR4((_sc), (_reg), (RD4((_sc), (_reg)) & ~(_clr)) | (_set))
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static void
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mtk_xhci_fdt_init(device_t dev)
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{
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struct xhci_softc *sc;
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uint32_t temp, u3_ports, u2_ports, i;
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sc = device_get_softc(dev);
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temp = RD4(sc, USB_IP_CAP);
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u3_ports = U3_PORT_NUM(temp);
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u2_ports = U2_PORT_NUM(temp);
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device_printf(dev, "%d USB3 ports, %d USB2 ports\n",
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u3_ports, u2_ports);
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CLRSET4(sc, USB_IP_PW_CTRL, 0, USB_IP_SW_RST);
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CLRSET4(sc, USB_IP_PW_CTRL, USB_IP_SW_RST, 0);
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CLRSET4(sc, USB_IP_PW_CTRL_1, USB_IP_PDN, 0);
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for (i = 0; i < u3_ports; i++)
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CLRSET4(sc, USB_U3_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0);
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for (i = 0; i < u2_ports; i++)
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CLRSET4(sc, USB_U2_CTRL(i), USB_PORT_PDN | USB_PORT_DIS, 0);
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DELAY(100000);
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WR4(sc, USB_HDMA_CFG, USB_HDMA_CFG_MT7621_VAL);
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WR4(sc, U3_LTSSM_TIMING_PARAM3, U3_LTSSM_TIMING_VAL);
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WR4(sc, SYNC_HS_EOF, SYNC_HS_EOF_VAL);
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WR4(sc, USB_IP_SPAR0, USB_IP_SPAR0_VAL);
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CLRSET4(sc, U2_PHY_BASE_P0 + U2_PHYD_CR1, U2_PHYD_CR1_MASK,
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U2_PHYD_CR1_VAL);
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CLRSET4(sc, U2_PHY_BASE_P1 + U2_PHYD_CR1, U2_PHYD_CR1_MASK,
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U2_PHYD_CR1_VAL);
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}
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