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mirror of https://git.FreeBSD.org/src.git synced 2024-11-28 08:02:54 +00:00

rtwn_pci(4): add support for RTL8188EE chipset.

Initially based on https://reviews.freebsd.org/D15692;
later deduplicated and improved a bit (Tx reports, IQ calibration support).

Submitted by:	Farhan Khan <khanzf@gmail.com>
MFC after:	4 days
Relnotes:	yes
Differential Revision:	https://reviews.freebsd.org/D15692
This commit is contained in:
Andriy Voskoboinyk 2019-01-02 06:48:53 +00:00
parent a163403b62
commit b3f3786e5d
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=342682
15 changed files with 1327 additions and 20 deletions

View File

@ -93,6 +93,7 @@ The driver (if not compiled with
) may use following firmware files, which are loaded
when an interface is brought up:
.Bl -tag -width Ds -offset indent -compact
.It Pa /boot/kernel/rtwn-rtl8188eefw.ko
.It Pa /boot/kernel/rtwn-rtl8188eufw.ko
.It Pa /boot/kernel/rtwn-rtl8192cfwE_B.ko
.It Pa /boot/kernel/rtwn-rtl8192cfwE.ko

View File

@ -48,11 +48,11 @@ kernel configuration file:
The
.Nm
driver supports PCIe wireless network devices based on the Realtek
RTL8188CE chipset.
RTL8188CE/RTL8188EE chipsets.
.Pp
The RTL8188CE is a highly integrated 802.11n adapter that combines a MAC,
a 1T1R capable baseband and an RF in a single chip.
It operates in the 2GHz spectrum only.
Both RTL8188CE and RTL8188EE are highly integrated 802.11n adapters
that combines a MAC, a 1T1R capable baseband and an RF in a single chip.
They are operate in the 2GHz spectrum only.
.Sh SEE ALSO
.Xr pci 4 ,
.Xr rtwn 4 ,

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@ -0,0 +1,506 @@
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M(-H`````Y/W_$C%-?WQ^"!(M7.Q$@/R0@9,2(,Z0@9,21-F0A;L2(,Y_?'X(
M$BZBD`$`=#_PH^!4_?"0!5/@1"#P(I``D.`@X/DBD(#QX/U_DQ(R'I"`Z.!@
M$I`!+^`PYP5T$/"`!I`!+W20\)``".!$$/U_"!(R'G\!$E?1D`"0X$0!_7^0
M$C(>?Q1^``(RJN\4D`5S\)`!/W00\/U_`W1%+_CF3?[V=#@O]8+D-`'U@^[P
M(G1%+_CF_NWT7O[V=#@O]8+D-`'U@^[P(M,0KP'#P-"0@:#M\)"!G^_PTY0'
M4'#@_W0!J`<(@`+#,]C\]/^0`$?@7_U_1Q(R'I"!G^#_=`&H!PB``L,SV/S_
MD`!&X$_]?T82,AZ0@:#@8!B0@9_@_W0!J`<(@`+#,]C\_Y``1>!/@!>0@9_@
M_W0!J`<(@`+#,]C\]/^0`$7@7_U_18!^D(&?X"3X\.`D!/]T`:@'"(`"PS/8
M_/3_D`!#X%_]?T,2,AZ0@9_@_W0!J`<(@`+#,]C\_Y``0^!/_7]#$C(>D(&@
MX&`=D(&?X"0$_W0!J`<(@`+#,]C\_Y``0N!/_7]"@!R0@9_@)`3_=`&H!PB`
M`L,SV/ST_Y``0N!?_7]"$C(>T-"2KR*0@.3@5/OPY)"`\/"0@.OP(N\D_F`,
M!'`HD(#M=`'PH_`B[7`*D(#[X)"`[?"`!9"`[>WPD(#MX*/PD(#EX$0(\"(2
M3VKO9`%@")`!N'0!\(!GD(#KX/]4`V`(D`&X=`+P@%:0@.G@_N3#GE`(D`&X
M=`3P@$3O,.((D`&X=`CP@#B0@.O@,.0(D`&X=!#P@"F0@.7@$Q-4/R#@")`!
MN'0@\(`6D(#_X&`(D`&X=(#P@`B0`;CD\'\!(I`!N70$\'\`(I`"A^!@")`!
MN'0!\(`7D`*&X"#A")`!N'0$\(`(D`&XY/!_`2*0`;ET"/!_`"+O8#Z0@*/@
M9`%P-I"`Y>!4_O"0!2)T#_"0!@3@5+_PY/\22.:_`0Z0@.3@1$#PD(#J=`;P
M(I`!N70!\)`!N'0(\"*0!2)T;_"0!2?@5+_PD(#J=`+P(N20@0OPD`:IX)"!
M"_#@5,!P#9"`Z^!4_O!4_?`"1Z:0@0O@,.8BD(#GX&0!<"&0@.O@1`'PD(#F
MX%0/9`)@!%%*@`P23CV`!Y"`Z^!4_O"0@0O@D(#K,.<4X$0"$D[KD`%7=`7P
MD(#DX$0$\"+@5/WP(I`$'>!P%)"``^#_Y/T22?F.3H]/D`0?="#P(I"`H^!D
M`6`"0?J0@.?@<`)!^I"`YN#$5`]D`7`BD`:KX)"`[O"0!JK@D(#M\*/@_W`(
MD(#MX/[_@`"0@.[O\)"`Y>!$!/#DD(#P\)"`\J/@D`58\)`!5^3PD`$\=`+P
MD(#KX%3]\%3O\)"`YN#_Q%0/)/U0`H`",=B0@.7@$Q,35!\PX!"0@.W@_Z/@
MM0<&$F=*$DV?(I"`Y.#_$Q-4/S#@$>]4^_"0@.O@5/WP5`=P0H`]D(#PX`3P
MD(#KX%3O\)"`\.#_M`$"@`3OM`(&D`58X`3PD(#XX/^0@/#@TY]`#Y"`H^"T
M`0N0@.7@5/OP(A)'IB+D_N_#$_WO,.`$[B2`_I#]$.WPKP8BJP>J!NTK^^0Z
M^L.0@*#@FY"`G^":4!.CX"0!_Y"`G^`T`/[#ZY_[ZI[ZZI#]$?"O`W0`+_6"
+Y#3[]8/@_R(`,@@`
`
end

View File

@ -17,9 +17,11 @@
*/
void r92ce_attach(struct rtwn_pci_softc *);
void r88ee_attach(struct rtwn_pci_softc *);
enum {
RTWN_CHIP_RTL8192CE,
RTWN_CHIP_RTL8188EE,
RTWN_CHIP_MAX_PCI
};
@ -32,13 +34,15 @@ struct rtwn_pci_ident {
static const struct rtwn_pci_ident rtwn_pci_ident_table[] = {
{ 0x10ec, 0x8176, "Realtek RTL8188CE", RTWN_CHIP_RTL8192CE },
{ 0x10ec, 0x8179, "Realtek RTL8188EE", RTWN_CHIP_RTL8188EE },
{ 0, 0, NULL, RTWN_CHIP_MAX_PCI }
};
typedef void (*chip_pci_attach)(struct rtwn_pci_softc *);
static const chip_pci_attach rtwn_chip_pci_attach[RTWN_CHIP_MAX_PCI] = {
[RTWN_CHIP_RTL8192CE] = r92ce_attach
[RTWN_CHIP_RTL8192CE] = r92ce_attach,
[RTWN_CHIP_RTL8188EE] = r88ee_attach
};
static __inline void

View File

@ -0,0 +1,53 @@
/*-
* Copyright (c) 2018 Farhan Khan <khanzf@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
*/
#ifndef RTL8188EE_H
#define RTL8188EE_H
#include <dev/rtwn/rtl8188e/r88e.h>
/*
* Global definitions.
*/
#define R88EE_PUBQ_NPAGES 115
#define R88EE_HPQ_NPAGES 41
#define R88EE_NPQ_NPAGES 1
#define R88EE_LPQ_NPAGES 13
#define R88EE_TX_PAGE_COUNT \
(R88EE_PUBQ_NPAGES + R88EE_HPQ_NPAGES + \
R88EE_NPQ_NPAGES + R88EE_LPQ_NPAGES)
/*
* Function declarations.
*/
/* r88ee_init.c */
void r88ee_init_bb(struct rtwn_softc *);
void r88ee_init_intr(struct rtwn_softc *);
int r88ee_power_on(struct rtwn_softc *);
void r88ee_power_off(struct rtwn_softc *);
/* r88ee_rx.c */
int r88ee_get_intr_status(struct rtwn_pci_softc *, int *);
void r88ee_enable_intr(struct rtwn_pci_softc *);
void r88ee_start_xfers(struct rtwn_softc *);
void r88ee_post_init(struct rtwn_softc *);
#endif /* RTL8188EE_H */

View File

@ -0,0 +1,242 @@
/*-
* Copyright (c) 2018 Farhan Khan <khanzf@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_wlan.h"
#include <sys/param.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/mbuf.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/queue.h>
#include <sys/taskqueue.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/linker.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <net/if.h>
#include <net/ethernet.h>
#include <net/if_media.h>
#include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_radiotap.h>
#include <dev/rtwn/if_rtwnreg.h>
#include <dev/rtwn/if_rtwnvar.h>
#include <dev/rtwn/if_rtwn_nop.h>
#include <dev/rtwn/pci/rtwn_pci_var.h>
#include <dev/rtwn/rtl8192c/r92c_var.h>
#include <dev/rtwn/rtl8188e/r88e_priv.h>
#include <dev/rtwn/rtl8188e/r88e_rom_image.h> /* for 'macaddr' field */
#include <dev/rtwn/rtl8192c/pci/r92ce.h>
#include <dev/rtwn/rtl8192c/pci/r92ce_tx_desc.h>
#include <dev/rtwn/rtl8188e/pci/r88ee.h>
#include <dev/rtwn/rtl8188e/pci/r88ee_reg.h>
static struct rtwn_r88e_txpwr r88ee_txpwr;
void r88ee_attach(struct rtwn_pci_softc *);
static void
r88ee_set_macaddr(struct rtwn_softc *sc, uint8_t *buf)
{
struct r88e_rom *rom = (struct r88e_rom *)buf;
IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->diff_d0.pci.macaddr);
}
static void
r88ee_postattach(struct rtwn_softc *sc)
{
struct r92c_softc *rs = sc->sc_priv;
struct ieee80211com *ic = &sc->sc_ic;
rs->rs_scan_start = ic->ic_scan_start;
ic->ic_scan_start = r92c_scan_start;
rs->rs_scan_end = ic->ic_scan_end;
ic->ic_scan_end = r92c_scan_end;
}
static void
r88ee_attach_private(struct rtwn_softc *sc)
{
struct r92c_softc *rs;
rs = malloc(sizeof(struct r92c_softc), M_RTWN_PRIV, M_WAITOK | M_ZERO);
rs->rs_txpwr = &r88ee_txpwr;
rs->rs_set_bw20 = r88e_set_bw20;
rs->rs_get_txpower = r88e_get_txpower;
rs->rs_set_gain = r88e_set_gain;
rs->rs_tx_enable_ampdu = r88e_tx_enable_ampdu;
rs->rs_tx_setup_hwseq = r88e_tx_setup_hwseq;
rs->rs_tx_setup_macid = r88e_tx_setup_macid;
rs->rs_set_rom_opts = r88ee_set_macaddr;
rs->rf_read_delay[0] = 1000;
rs->rf_read_delay[1] = 1000;
rs->rf_read_delay[2] = 1000;
sc->sc_priv = rs;
}
static void
r88ee_adj_devcaps(struct rtwn_softc *sc)
{
/* XXX TODO */
}
void
r88ee_attach(struct rtwn_pci_softc *pc)
{
struct rtwn_softc *sc = &pc->pc_sc;
/* PCIe part. */
pc->pc_setup_tx_desc = r92ce_setup_tx_desc;
pc->pc_tx_postsetup = r92ce_tx_postsetup;
pc->pc_copy_tx_desc = r92ce_copy_tx_desc;
pc->pc_enable_intr = r88ee_enable_intr;
pc->pc_get_intr_status = r88ee_get_intr_status;
pc->pc_qmap = 0xe771;
pc->tcr = 0x8200;
/* Common part. */
sc->sc_flags = RTWN_FLAG_EXT_HDR;
sc->sc_start_xfers = r88ee_start_xfers;
sc->sc_set_chan = r92c_set_chan;
sc->sc_fill_tx_desc = r92c_fill_tx_desc;
sc->sc_fill_tx_desc_raw = r92c_fill_tx_desc_raw;
sc->sc_fill_tx_desc_null = r92c_fill_tx_desc_null; /* XXX recheck */
sc->sc_dump_tx_desc = r92ce_dump_tx_desc;
sc->sc_tx_radiotap_flags = r92c_tx_radiotap_flags;
sc->sc_rx_radiotap_flags = r92c_rx_radiotap_flags;
sc->sc_get_rx_stats = r88e_get_rx_stats;
sc->sc_get_rssi_cck = r88e_get_rssi_cck;
sc->sc_get_rssi_ofdm = r88e_get_rssi_ofdm;
sc->sc_classify_intr = r88e_classify_intr;
sc->sc_handle_tx_report = r88e_ratectl_tx_complete;
sc->sc_handle_c2h_report = r88e_handle_c2h_report;
sc->sc_check_frame = rtwn_nop_int_softc_mbuf;
sc->sc_rf_read = r92c_rf_read;
sc->sc_rf_write = r88e_rf_write;
sc->sc_check_condition = r92c_check_condition;
sc->sc_efuse_postread = rtwn_nop_softc;
sc->sc_parse_rom = r88e_parse_rom;
sc->sc_set_led = r88e_set_led;
sc->sc_power_on = r88ee_power_on;
sc->sc_power_off = r88ee_power_off;
#ifndef RTWN_WITHOUT_UCODE
sc->sc_fw_reset = r88e_fw_reset;
sc->sc_fw_download_enable = r88e_fw_download_enable;
#endif
sc->sc_llt_init = r92c_llt_init;
sc->sc_set_page_size = r92c_set_page_size;
sc->sc_lc_calib = r92c_lc_calib;
sc->sc_iq_calib = r88e_iq_calib;
sc->sc_read_chipid_vendor = rtwn_nop_softc_uint32;
sc->sc_adj_devcaps = r88ee_adj_devcaps;
sc->sc_vap_preattach = rtwn_nop_softc_vap;
sc->sc_postattach = r88ee_postattach;
sc->sc_detach_private = r92c_detach_private;
sc->sc_set_media_status = r88e_set_media_status;
#ifndef RTWN_WITHOUT_UCODE
sc->sc_set_rsvd_page = r88e_set_rsvd_page;
sc->sc_set_pwrmode = r88e_set_pwrmode;
sc->sc_set_rssi = r92c_set_rssi;
#endif
sc->sc_beacon_init = r92c_beacon_init;
sc->sc_beacon_enable = r88e_beacon_enable;
sc->sc_beacon_set_rate = rtwn_nop_void_int;
sc->sc_beacon_select = rtwn_nop_softc_int;
sc->sc_temp_measure = r88e_temp_measure;
sc->sc_temp_read = r88e_temp_read;
sc->sc_init_tx_agg = rtwn_nop_softc;
sc->sc_init_rx_agg = rtwn_nop_softc;
sc->sc_init_ampdu = r92ce_init_ampdu;
sc->sc_init_intr = r88ee_init_intr;
sc->sc_init_edca = r92ce_init_edca;
sc->sc_init_bb = r88ee_init_bb;
sc->sc_init_rf = r92c_init_rf;
sc->sc_init_antsel = rtwn_nop_softc;
sc->sc_post_init = r88ee_post_init;
sc->sc_init_bcnq1_boundary = rtwn_nop_int_softc;
sc->mac_prog = &rtl8188e_mac[0];
sc->mac_size = nitems(rtl8188e_mac);
sc->bb_prog = &rtl8188e_bb[0];
sc->bb_size = nitems(rtl8188e_bb);
sc->agc_prog = &rtl8188e_agc[0];
sc->agc_size = nitems(rtl8188e_agc);
sc->rf_prog = &rtl8188e_rf[0];
sc->name = "RTL8188EE";
sc->fwname = "rtwn-rtl8188eefw";
sc->fwsig = 0x88e;
sc->page_count = R88EE_TX_PAGE_COUNT;
sc->pktbuf_count = R88E_TXPKTBUF_COUNT;
sc->ackto = 0x40;
sc->npubqpages = R88EE_PUBQ_NPAGES;
sc->nhqpages = R88EE_HPQ_NPAGES;
sc->nnqpages = R88EE_NPQ_NPAGES;
sc->nlqpages = R88EE_LPQ_NPAGES;
sc->page_size = R92C_TX_PAGE_SIZE;
sc->txdesc_len = sizeof(struct r92ce_tx_desc);
sc->efuse_maxlen = R88E_EFUSE_MAX_LEN;
sc->efuse_maplen = R88E_EFUSE_MAP_LEN;
sc->rx_dma_size = R88E_RX_DMA_BUFFER_SIZE;
sc->macid_limit = R88E_MACID_MAX + 1;
sc->cam_entry_limit = R92C_CAM_ENTRY_COUNT;
sc->fwsize_limit = R92C_MAX_FW_SIZE;
sc->temp_delta = R88E_CALIB_THRESHOLD;
sc->bcn_status_reg[0] = R92C_TDECTRL;
/*
* TODO: some additional setup is required
* to maintain few beacons at the same time.
*
* XXX BCNQ1 mechanism is not needed here; move it to the USB module.
*/
sc->bcn_status_reg[1] = R92C_TDECTRL;
sc->rcr = 0;
sc->ntxchains = 1;
sc->nrxchains = 1;
r88ee_attach_private(sc);
}

View File

@ -0,0 +1,276 @@
/*-
* Copyright (c) 2017 Farhan Khan <khanzf@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_wlan.h"
#include <sys/param.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/mbuf.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/queue.h>
#include <sys/taskqueue.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/linker.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <net/if.h>
#include <net/ethernet.h>
#include <net/if_media.h>
#include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_radiotap.h>
#include <dev/rtwn/if_rtwnvar.h>
#include <dev/rtwn/pci/rtwn_pci_var.h>
#include <dev/rtwn/rtl8192c/r92c.h>
#include <dev/rtwn/rtl8188e/pci/r88ee.h>
#include <dev/rtwn/rtl8188e/pci/r88ee_reg.h>
void
r88ee_init_bb(struct rtwn_softc *sc)
{
/* Enable BB and RF. */
rtwn_setbits_2(sc, R92C_SYS_FUNC_EN, 0,
R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST |
R92C_SYS_FUNC_EN_DIO_RF);
rtwn_write_1(sc, R92C_RF_CTRL,
R92C_RF_CTRL_EN | R92C_RF_CTRL_RSTB | R92C_RF_CTRL_SDMRSTB);
rtwn_write_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_PPLL |
R92C_SYS_FUNC_EN_PCIEA | R92C_SYS_FUNC_EN_DIO_PCIE |
R92C_SYS_FUNC_EN_BB_GLB_RST | R92C_SYS_FUNC_EN_BBRSTB);
r88e_init_bb_common(sc);
}
void
r88ee_init_intr(struct rtwn_softc *sc)
{
/* Disable interrupts. */
rtwn_write_4(sc, R88E_HIMR, 0x00000000);
rtwn_write_4(sc, R88E_HIMRE, 0x00000000);
}
int
r88ee_power_on(struct rtwn_softc *sc)
{
int ntries;
/* Wait for power ready bit. */
for (ntries = 0; ntries < 5000; ntries++) {
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000) {
device_printf(sc->sc_dev,
"timeout waiting for chip power up\n");
return (ETIMEDOUT);
}
/* Unlock ISO/CLK/Power control register. */
rtwn_write_1(sc, R92C_RSV_CTRL, 0);
/* Reset BB. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN,
R92C_SYS_FUNC_EN_BBRSTB | R92C_SYS_FUNC_EN_BB_GLB_RST, 0);
/* schmit trigger */
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
/* Disable HWPDN. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_APDM_HPDN, 0, 1);
/* Disable WL suspend. */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
R92C_APS_FSMCO_AFSM_HSUS | R92C_APS_FSMCO_AFSM_PCIE, 0, 1);
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
0, R92C_APS_FSMCO_APFM_ONMAC, 1);
for (ntries = 0; ntries < 5000; ntries++) {
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_ONMAC))
break;
rtwn_delay(sc, 10);
}
if (ntries == 5000)
return (ETIMEDOUT);
rtwn_setbits_1(sc, R92C_PCIE_CTRL_REG + 2, 0, 0x04);
/* Enable LDO normal mode. */
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, R92C_LPLDO_CTRL_SLEEP, 0);
/* Enable MAC DMA/WMAC/SCHEDULE/SEC blocks. */
rtwn_write_2(sc, R92C_CR, 0);
rtwn_setbits_2(sc, R92C_CR, 0,
R92C_CR_HCI_TXDMA_EN | R92C_CR_TXDMA_EN |
R92C_CR_HCI_RXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN |
((sc->sc_hwcrypto != RTWN_CRYPTO_SW) ? R92C_CR_ENSEC : 0) |
R92C_CR_CALTMR_EN);
rtwn_write_4(sc, R92C_INT_MIG, 0);
rtwn_write_4(sc, R92C_MCUTST_1, 0);
return (0);
}
void
r88ee_power_off(struct rtwn_softc *sc)
{
uint8_t reg;
int ntries;
/* Disable any kind of TX reports. */
rtwn_setbits_1(sc, R88E_TX_RPT_CTRL,
R88E_TX_RPT1_ENA | R88E_TX_RPT2_ENA, 0);
rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0xFF);
/* Move card to Low Power State. */
/* Block all Tx queues. */
rtwn_write_1(sc, R92C_TXPAUSE, R92C_TX_QUEUE_ALL);
for (ntries = 0; ntries < 10; ntries++) {
/* Should be zero if no packet is transmitting. */
if (rtwn_read_4(sc, R88E_SCH_TXCMD) == 0)
break;
rtwn_delay(sc, 5000);
}
if (ntries == 10) {
device_printf(sc->sc_dev, "%s: failed to block Tx queues\n",
__func__);
return;
}
/* CCK and OFDM are disabled, and clock are gated. */
rtwn_setbits_1(sc, R92C_SYS_FUNC_EN, R92C_SYS_FUNC_EN_BBRSTB, 0);
rtwn_delay(sc, 1);
/* Reset MAC TRX */
rtwn_write_1(sc, R92C_CR,
R92C_CR_HCI_TXDMA_EN | R92C_CR_HCI_RXDMA_EN |
R92C_CR_TXDMA_EN | R92C_CR_RXDMA_EN |
R92C_CR_PROTOCOL_EN | R92C_CR_SCHEDULE_EN);
/* Disable h/w encryption. */
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
/* Respond TxOK to scheduler */
rtwn_setbits_1(sc, R92C_DUAL_TSF_RST, 0, 0x20);
/* If firmware in ram code, do reset. */
#ifndef RTWN_WITHOUT_UCODE
if (rtwn_read_1(sc, R92C_MCUFWDL) & R92C_MCUFWDL_RDY)
r88e_fw_reset(sc, RTWN_FW_RESET_SHUTDOWN);
#endif
/* Reset MCU ready status. */
rtwn_write_1(sc, R92C_MCUFWDL, 0);
/* Disable 32k. */
rtwn_setbits_1(sc, R88E_32K_CTRL, 0x01, 0);
/* Move card to Disabled state. */
/* Turn off RF. */
rtwn_write_1(sc, R92C_RF_CTRL, 0);
/* LDO Sleep mode. */
rtwn_setbits_1(sc, R92C_LPLDO_CTRL, 0, R92C_LPLDO_CTRL_SLEEP);
/* Turn off MAC by HW state machine */
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
R92C_APS_FSMCO_APFM_OFF, 1);
for (ntries = 0; ntries < 10; ntries++) {
/* Wait until it will be disabled. */
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
R92C_APS_FSMCO_APFM_OFF) == 0)
break;
rtwn_delay(sc, 5000);
}
if (ntries == 10) {
device_printf(sc->sc_dev, "%s: could not turn off MAC\n",
__func__);
return;
}
/* schmit trigger */
rtwn_setbits_1(sc, R92C_AFE_XTAL_CTRL + 2, 0, 0x80);
/* Reset MCU IO Wrapper. */
reg = rtwn_read_1(sc, R92C_RSV_CTRL + 1);
rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg & ~0x08);
rtwn_write_1(sc, R92C_RSV_CTRL + 1, reg | 0x08);
/* marked as 'For Power Consumption' code. */
rtwn_write_1(sc, R92C_GPIO_OUT, rtwn_read_1(sc, R92C_GPIO_IN));
rtwn_write_1(sc, R92C_GPIO_IOSEL, 0xff);
rtwn_write_1(sc, R92C_GPIO_IO_SEL,
rtwn_read_1(sc, R92C_GPIO_IO_SEL) << 4);
rtwn_setbits_1(sc, R92C_GPIO_MOD, 0, 0x0f);
/* Set LNA, TRSW, EX_PA Pin to output mode. */
rtwn_write_4(sc, R88E_BB_PAD_CTRL, 0x00080808);
}
void
r88ee_post_init(struct rtwn_softc *sc)
{
/* Enable per-packet TX report. */
rtwn_setbits_1(sc, R88E_TX_RPT_CTRL, 0, R88E_TX_RPT1_ENA);
/* Disable Tx if MACID is not associated. */
rtwn_write_4(sc, R88E_MACID_NO_LINK, 0xffffffff);
rtwn_write_4(sc, R88E_MACID_NO_LINK + 4, 0xffffffff);
r88e_macid_enable_link(sc, RTWN_MACID_BC, 1);
/* Perform LO and IQ calibrations. */
r88e_iq_calib(sc);
/* Perform LC calibration. */
r92c_lc_calib(sc);
/* Enable Rx DMA */
rtwn_write_1(sc, R92C_PCIE_CTRL_REG + 1, 0);
if (sc->sc_ratectl_sysctl == RTWN_RATECTL_FW) {
/* No support (yet?) for f/w rate adaptation. */
sc->sc_ratectl = RTWN_RATECTL_NET80211;
} else
sc->sc_ratectl = sc->sc_ratectl_sysctl;
}

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@ -0,0 +1,26 @@
/*-
* Copyright (c) 2018 Farhan Khan <khanzf@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
* $FreeBSD$
*/
#ifndef R88EE_REG_H
#define R88EE_REG_H
#include <dev/rtwn/rtl8192c/pci/r92ce_reg.h>
#include <dev/rtwn/rtl8188e/r88e_reg.h>
#endif /* R88EE_REG_H */

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@ -0,0 +1,143 @@
/*-
* Copyright (c) 2017 Farhan Khan <khanzf@gmail.com>
*
* Permission to use, copy, modify, and distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_wlan.h"
#include <sys/param.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/mbuf.h>
#include <sys/kernel.h>
#include <sys/socket.h>
#include <sys/systm.h>
#include <sys/malloc.h>
#include <sys/queue.h>
#include <sys/taskqueue.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/linker.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <net/if.h>
#include <net/ethernet.h>
#include <net/if_media.h>
#include <net80211/ieee80211_var.h>
#include <net80211/ieee80211_radiotap.h>
#include <dev/rtwn/if_rtwnvar.h>
#include <dev/rtwn/if_rtwn_debug.h>
#include <dev/rtwn/pci/rtwn_pci_var.h>
#include <dev/rtwn/rtl8188e/pci/r88ee.h>
#include <dev/rtwn/rtl8188e/pci/r88ee_reg.h>
int
r88ee_get_intr_status(struct rtwn_pci_softc *pc, int *rings)
{
struct rtwn_softc *sc = &pc->pc_sc;
uint32_t status, status_ex;
int ret;
*rings = 0;
status = rtwn_read_4(sc, R88E_HISR);
status_ex = rtwn_read_4(sc, R88E_HISRE);
RTWN_DPRINTF(sc, RTWN_DEBUG_INTR, "%s: HISR %08X, HISRE %08X\n",
__func__, status, status_ex);
if ((status == 0 || status == 0xffffffff) &&
(status_ex == 0 || status_ex == 0xffffffff))
return (0);
/* Disable interrupts */
rtwn_write_4(sc, R88E_HIMR, 0);
rtwn_write_4(sc, R88E_HIMRE, 0);
/* Ack interrupts */
rtwn_write_4(sc, R88E_HISR, status);
rtwn_write_4(sc, R88E_HISRE, status_ex);
if (status & R88E_HIMR_HIGHDOK)
*rings |= (1 << RTWN_PCI_HIGH_QUEUE);
if (status & R88E_HIMR_MGNTDOK)
*rings |= (1 << RTWN_PCI_MGNT_QUEUE);
if (status & R88E_HIMR_BKDOK)
*rings |= (1 << RTWN_PCI_BK_QUEUE);
if (status & R88E_HIMR_BEDOK)
*rings |= (1 << RTWN_PCI_BE_QUEUE);
if (status & R88E_HIMR_VIDOK)
*rings |= (1 << RTWN_PCI_VI_QUEUE);
if (status & R88E_HIMR_VODOK)
*rings |= (1 << RTWN_PCI_VO_QUEUE);
ret = 0;
if (status_ex & R88E_HIMRE_RXERR)
ret |= RTWN_PCI_INTR_RX_ERROR;
if (status_ex & R88E_HIMRE_RXFOVW)
ret |= RTWN_PCI_INTR_RX_OVERFLOW;
if (status & R88E_HIMR_RDU)
ret |= RTWN_PCI_INTR_RX_DESC_UNAVAIL;
if (status & R88E_HIMR_ROK)
ret |= RTWN_PCI_INTR_RX_DONE;
if (status_ex & R88E_HIMRE_TXERR)
ret |= RTWN_PCI_INTR_TX_ERROR;
if (status_ex & R88E_HIMRE_TXFOVW)
ret |= RTWN_PCI_INTR_TX_OVERFLOW;
if (status & R88E_HIMR_TXRPT)
ret |= RTWN_PCI_INTR_TX_REPORT;
if (status & R88E_HIMR_PSTIMEOUT)
ret |= RTWN_PCI_INTR_PS_TIMEOUT;
return (ret);
}
#define R88E_INT_ENABLE (R88E_HIMR_ROK | R88E_HIMR_RDU | R88E_HIMR_VODOK | \
R88E_HIMR_VIDOK | R88E_HIMR_BEDOK | \
R88E_HIMR_BKDOK | R88E_HIMR_MGNTDOK | \
R88E_HIMR_HIGHDOK | R88E_HIMR_TXRPT)
#define R88E_INT_ENABLE_EX (R88E_HIMRE_RXFOVW | R88E_HIMRE_RXERR)
void
r88ee_enable_intr(struct rtwn_pci_softc *pc)
{
struct rtwn_softc *sc = &pc->pc_sc;
/* Enable interrupts */
rtwn_write_4(sc, R88E_HIMR, R88E_INT_ENABLE);
rtwn_write_4(sc, R88E_HIMRE, R88E_INT_ENABLE_EX);
}
void
r88ee_start_xfers(struct rtwn_softc *sc)
{
/* Clear pending interrupts. */
rtwn_write_4(sc, R88E_HISR, 0xffffffff);
rtwn_write_4(sc, R88E_HISRE, 0xffffffff);
/* Enable interrupts. */
rtwn_write_4(sc, R88E_HIMR, R88E_INT_ENABLE);
rtwn_write_4(sc, R88E_HIMRE, R88E_INT_ENABLE_EX);
}
#undef R88E_INT_ENABLE
#undef R88E_INT_ENABLE_EX

View File

@ -45,16 +45,49 @@
/* Bits for R88E_HIMR. */
#define R88E_HIMR_CPWM 0x00000100
#define R88E_HIMR_CPWM2 0x00000200
#define R88E_HIMR_TBDER 0x04000000
#define R88E_HIMR_PSTIMEOUT 0x20000000
#define R88E_HIMR_ROK 0x00000001 /* receive DMA OK */
#define R88E_HIMR_RDU 0x00000002 /* Rx descriptor unavailable */
#define R88E_HIMR_VODOK 0x00000004 /* AC_VO DMA OK */
#define R88E_HIMR_VIDOK 0x00000008 /* AC_VI DMA OK */
#define R88E_HIMR_BEDOK 0x00000010 /* AC_BE DMA OK */
#define R88E_HIMR_BKDOK 0x00000020 /* AC_BK DMA OK */
#define R88E_HIMR_MGNTDOK 0x00000040 /* management queue DMA OK */
#define R88E_HIMR_HIGHDOK 0x00000080 /* high queue DMA OK */
#define R88E_HIMR_CPWM 0x00000100 /* CPU power mode intr 1 */
#define R88E_HIMR_CPWM2 0x00000200 /* CPU power mode intr 2 */
#define R88E_HIMR_C2HCMD 0x00000400 /* C2H command interrupt */
#define R88E_HIMR_HISR 0x00000800 /* (HISR & HIMR) != 0 */
#define R88E_HIMR_ATIMEND 0x00001000 /* ATIM window end interrupt */
#define R88E_HIMR_HSISR 0x00008000 /* (HSIMR & HSISR) != 0 */
#define R88E_HIMR_BCNDERR 0x00010000 /* beacon queue DMA error */
#define R88E_HIMR_BCNINT 0x00100000 /* beacon DMA interrupt 0 */
#define R88E_HIMR_TSF32 0x01000000 /* TSF 32 bit interrupt */
#define R88E_HIMR_TBDOK 0x02000000 /* beacon transmit OK */
#define R88E_HIMR_TBDER 0x04000000 /* beacon transmit error */
#define R88E_HIMR_GTIMER3 0x08000000 /* GTIMER3 interrupt */
#define R88E_HIMR_GTIMER4 0x10000000 /* GTIMER4 interrupt */
#define R88E_HIMR_PSTIMEOUT 0x20000000 /* powersave timeout */
#define R88E_HIMR_TXRPT 0x40000000 /* Tx report interrupt */
/* Bits for R88E_HIMRE.*/
#define R88E_HIMRE_RXFOVW 0x00000100
#define R88E_HIMRE_TXFOVW 0x00000200
#define R88E_HIMRE_RXERR 0x00000400
#define R88E_HIMRE_TXERR 0x00000800
#define R88E_HIMRE_RXFOVW 0x00000100 /* receive FIFO overflow */
#define R88E_HIMRE_TXFOVW 0x00000200 /* transmit FIFO overflow */
#define R88E_HIMRE_RXERR 0x00000400 /* receive error */
#define R88E_HIMRE_TXERR 0x00000800 /* transmit error */
#define R88E_HIMRE_BCNDOK1 0x00004000 /* beacon queue DMA OK (1) */
#define R88E_HIMRE_BCNDOK2 0x00008000 /* beacon queue DMA OK (2) */
#define R88E_HIMRE_BCNDOK3 0x00010000 /* beacon queue DMA OK (3) */
#define R88E_HIMRE_BCNDOK4 0x00020000 /* beacon queue DMA OK (4) */
#define R88E_HIMRE_BCNDOK5 0x00040000 /* beacon queue DMA OK (5) */
#define R88E_HIMRE_BCNDOK6 0x00080000 /* beacon queue DMA OK (6) */
#define R88E_HIMRE_BCNDOK7 0x00100000 /* beacon queue DMA OK (7) */
#define R88E_HIMRE_BCNDMAINT1 0x00200000 /* beacon DMA interrupt 1 */
#define R88E_HIMRE_BCNDMAINT2 0x00400000 /* beacon DMA interrupt 2 */
#define R88E_HIMRE_BCNDMAINT3 0x00800000 /* beacon DMA interrupt 3 */
#define R88E_HIMRE_BCNDMAINT4 0x01000000 /* beacon DMA interrupt 4 */
#define R88E_HIMRE_BCNDMAINT5 0x02000000 /* beacon DMA interrupt 5 */
#define R88E_HIMRE_BCNDMAINT6 0x04000000 /* beacon DMA interrupt 6 */
#define R88E_HIMRE_BCNDMAINT7 0x08000000 /* beacon DMA interrupt 7 */
/* Bits for R88E_TX_RPT_CTRL. */
#define R88E_TX_RPT1_ENA 0x01

View File

@ -44,11 +44,24 @@ struct r88e_rom {
uint8_t reserved4[3];
uint8_t rf_ant_opt;
uint8_t reserved5[6];
uint16_t vid;
uint16_t pid;
uint8_t usb_opt;
uint8_t reserved6[2];
uint8_t macaddr[IEEE80211_ADDR_LEN];
union {
struct {
uint16_t vid;
uint16_t pid;
uint8_t usb_opt;
uint8_t reserved6[2];
uint8_t macaddr[IEEE80211_ADDR_LEN];
} __packed usb;
struct {
uint8_t macaddr[IEEE80211_ADDR_LEN];
uint16_t vid;
uint16_t pid;
uint8_t reserved6[3];
} __packed pci;
} __packed diff_d0;
uint8_t reserved7[2];
uint8_t string[33]; /* "realtek 802.11n NIC" */
uint8_t reserved8[256];

View File

@ -71,7 +71,7 @@ r88eu_set_macaddr(struct rtwn_softc *sc, uint8_t *buf)
{
struct r88e_rom *rom = (struct r88e_rom *)buf;
IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->macaddr);
IEEE80211_ADDR_COPY(sc->sc_ic.ic_macaddr, rom->diff_d0.usb.macaddr);
}
static void

View File

@ -17,6 +17,10 @@ SRCS += r92ce_attach.c r92ce_calib.c r92ce_fw.c r92ce_init.c r92ce_led.c \
r92ce_rx.c r92ce_tx.c \
r92ce.h r92ce_priv.h r92ce_reg.h r92ce_rx_desc.h r92ce_tx_desc.h
.PATH: ${SRCTOP}/sys/dev/rtwn/rtl8188e/pci
SRCS += r88ee_attach.c r88ee_init.c r88ee_rx.c \
r88ee.h r88ee_reg.h
opt_rtwn.h:
@echo "#define RTWN_DEBUG 1" > ${.TARGET}
.if ${MK_SOURCELESS_UCODE} == "no"

View File

@ -1,6 +1,6 @@
# $FreeBSD$
SUBDIR= rtwnrtl8188eu rtwnrtl8192cT rtwnrtl8192cU rtwnrtl8192eu rtwnrtl8812au \
rtwnrtl8821au rtwnrtl8192cE rtwnrtl8192cEB
rtwnrtl8821au rtwnrtl8192cE rtwnrtl8192cEB rtwnrtl8188ee
.include <bsd.subdir.mk>

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@ -0,0 +1,6 @@
# $FreeBSD$
KMOD= rtwn-rtl8188eefw
IMG= rtwn-rtl8188eefw
.include <bsd.kmod.mk>