mirror of
https://git.FreeBSD.org/src.git
synced 2024-10-19 02:29:40 +00:00
Revamp XLR interrupt handling, the previous scheme does not work well on
SMP. We used to route all PIC based interrupts to cpu 0, and used the per-CPU interrupt mask to enable/disable interrupts. But the interrupt threads can run on any cpu on SMP, and the interrupt thread will re-enable the interrupts on the CPU it runs on when it is done, and not on cpu0 where the PIC will still send interrupts to. The fix is move the disable/enable for PIC based interrupts to PIC, we will ack on PIC only when the interrupt thread is done, and we do not use the per-CPU interrupt mask. The changes also introduce a way for subsystems to add a function that will be called to clear the interrupt on the subsystem. Currently This is used by the PCI/PCIe for doing additional work during the interrupt handling.
This commit is contained in:
Jayachandran C.
parent
98b9eb0db2
commit
b47f51b4a0
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=211893
@ -40,10 +40,9 @@
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* XLR needs custom pre and post handlers for PCI/PCI-e interrupts
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* XXX: maybe follow i386 intsrc model
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*/
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void xlr_cpu_establish_hardintr(const char *, driver_filter_t *,
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driver_intr_t *, void *, int, int, void **, void (*)(void *),
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void (*)(void *), void (*)(void *), int (*)(void *, u_char));
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void xlr_mask_hard_irq(void *);
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void xlr_unmask_hard_irq(void *);
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void xlr_establish_intr(const char *name, driver_filter_t filt,
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driver_intr_t handler, void *arg, int irq, int flags,
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void **cookiep, void (*busack)(int));
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void xlr_enable_irq(int irq);
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#endif /* _RMI_INTERRUPT_H_ */
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@ -49,34 +49,76 @@ __FBSDID("$FreeBSD$");
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#include <mips/rmi/clock.h>
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#include <mips/rmi/pic.h>
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/*#include <machine/intrcnt.h>*/
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struct xlr_intrsrc {
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void (*busack)(int); /* Additional ack */
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struct intr_event *ie; /* event corresponding to intr */
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int irq;
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};
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static struct xlr_intrsrc xlr_interrupts[XLR_MAX_INTR];
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static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
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static struct intr_event *mips_intr_events[XLR_MAX_INTR];
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static int intrcnt_index;
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void
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xlr_mask_hard_irq(void *source)
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xlr_enable_irq(int irq)
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{
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uintptr_t irq = (uintptr_t) source;
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write_c0_eimr64(read_c0_eimr64() & ~(1ULL << irq));
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}
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void
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xlr_unmask_hard_irq(void *source)
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{
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uintptr_t irq = (uintptr_t) source;
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write_c0_eimr64(read_c0_eimr64() | (1ULL << irq));
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}
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void
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xlr_cpu_establish_hardintr(const char *name, driver_filter_t * filt,
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void (*handler) (void *), void *arg, int irq, int flags, void **cookiep,
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void (*pre_ithread)(void *), void (*post_ithread)(void *),
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void (*post_filter)(void *), int (*assign_cpu)(void *, u_char))
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cpu_establish_softintr(const char *name, driver_filter_t * filt,
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void (*handler) (void *), void *arg, int irq, int flags,
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void **cookiep)
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{
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panic("Soft interrupts unsupported!\n");
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}
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void
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cpu_establish_hardintr(const char *name, driver_filter_t * filt,
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void (*handler) (void *), void *arg, int irq, int flags,
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void **cookiep)
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{
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xlr_establish_intr(name, filt, handler, arg, irq, flags,
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cookiep, NULL);
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}
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static void
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xlr_post_filter(void *source)
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{
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struct xlr_intrsrc *src = source;
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if (src->busack)
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src->busack(src->irq);
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pic_ack(PIC_IRQ_TO_INTR(src->irq));
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}
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static void
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xlr_pre_ithread(void *source)
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{
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struct xlr_intrsrc *src = source;
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if (src->busack)
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src->busack(src->irq);
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}
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static void
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xlr_post_ithread(void *source)
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{
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struct xlr_intrsrc *src = source;
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pic_ack(PIC_IRQ_TO_INTR(src->irq));
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}
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void
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xlr_establish_intr(const char *name, driver_filter_t filt,
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driver_intr_t handler, void *arg, int irq, int flags,
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void **cookiep, void (*busack)(int))
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{
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struct intr_event *ie; /* descriptor for the IRQ */
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struct xlr_intrsrc *src = NULL;
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int errcode;
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if (irq < 0 || irq > XLR_MAX_INTR)
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@ -86,43 +128,37 @@ xlr_cpu_establish_hardintr(const char *name, driver_filter_t * filt,
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* FIXME locking - not needed now, because we do this only on
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* startup from CPU0
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*/
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ie = mips_intr_events[irq];
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/* mih->cntp = &intrcnt[irq]; */
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if (ie == NULL) {
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errcode = intr_event_create(&ie, (void *)(uintptr_t) irq, 0,
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irq, pre_ithread, post_ithread, post_filter, assign_cpu,
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"hard intr%d:", irq);
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printf("[%s] Setup intr %d called on cpu %d (%d)\n", name, irq,
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xlr_cpu_id(), PCPU_GET(cpuid));
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src = &xlr_interrupts[irq];
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ie = src->ie;
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if (ie == NULL) {
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/*
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* PIC based interrupts need ack in PIC, and some SoC
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* components need additional acks (e.g. PCI)
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*/
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if (PIC_IRQ_IS_PICINTR(irq))
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errcode = intr_event_create(&ie, src, 0, irq,
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xlr_pre_ithread, xlr_post_ithread, xlr_post_filter,
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NULL, "hard intr%d:", irq);
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else {
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if (filt == NULL)
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panic("Not supported - non filter percpu intr");
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errcode = intr_event_create(&ie, src, 0, irq,
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NULL, NULL, NULL, NULL, "hard intr%d:", irq);
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}
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if (errcode) {
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printf("Could not create event for intr %d\n", irq);
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return;
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}
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mips_intr_events[irq] = ie;
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src->irq = irq;
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src->busack = busack;
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src->ie = ie;
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}
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intr_event_add_handler(ie, name, filt, handler, arg,
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intr_priority(flags), flags, cookiep);
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xlr_unmask_hard_irq((void *)(uintptr_t) irq);
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}
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void
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cpu_establish_hardintr(const char *name, driver_filter_t * filt,
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void (*handler) (void *), void *arg, int irq, int flags, void **cookiep)
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{
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xlr_cpu_establish_hardintr(name, filt, handler, arg, irq,
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flags, cookiep, xlr_mask_hard_irq, xlr_unmask_hard_irq,
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NULL, NULL);
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}
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void
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cpu_establish_softintr(const char *name, driver_filter_t * filt,
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void (*handler) (void *), void *arg, int irq, int flags,
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void **cookiep)
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{
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/* we don't separate them into soft/hard like other mips */
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xlr_cpu_establish_hardintr(name, filt, handler, arg, irq,
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flags, cookiep, xlr_mask_hard_irq, xlr_unmask_hard_irq,
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NULL, NULL);
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xlr_enable_irq(irq);
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}
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void
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@ -148,7 +184,7 @@ cpu_intr(struct trapframe *tf)
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* compare which ACKs the interrupt.
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*/
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if (eirr & (1 << IRQ_TIMER)) {
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intr_event_handle(mips_intr_events[IRQ_TIMER], tf);
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intr_event_handle(xlr_interrupts[IRQ_TIMER].ie, tf);
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critical_exit();
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return;
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}
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@ -158,7 +194,7 @@ cpu_intr(struct trapframe *tf)
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if ((eirr & (1ULL << i)) == 0)
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continue;
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ie = mips_intr_events[i];
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ie = xlr_interrupts[i].ie;
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/* Don't account special IRQs */
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switch (i) {
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case IRQ_IPI:
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@ -167,16 +203,12 @@ cpu_intr(struct trapframe *tf)
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default:
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mips_intrcnt_inc(mips_intr_counters[i]);
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}
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/* Ack the IRQ on the CPU */
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write_c0_eirr64(1ULL << i);
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pic_ack(i);
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if (!ie || TAILQ_EMPTY(&ie->ie_handlers)) {
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printf("stray interrupt %d\n", i);
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continue;
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}
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if (intr_event_handle(ie, tf) != 0) {
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printf("stray interrupt %d\n", i);
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}
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pic_delayed_ack(i);
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}
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critical_exit();
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}
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@ -99,7 +99,7 @@ iodi_setup_intr(device_t dev, device_t child,
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/* FIXME uart 1? */
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cpu_establish_hardintr("uart", filt, intr, arg,
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PIC_UART_0_IRQ, flags, cookiep);
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pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1);
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pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 0);
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} else if (strcmp(device_get_name(child), "rge") == 0) {
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int irq;
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@ -107,11 +107,11 @@ iodi_setup_intr(device_t dev, device_t child,
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irq = (intptr_t)ires->__r_i;
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cpu_establish_hardintr("rge", filt, intr, arg, irq, flags,
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cookiep);
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pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1);
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pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 0);
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} else if (strcmp(device_get_name(child), "ehci") == 0) {
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cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags,
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cookiep);
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pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1);
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pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 0);
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}
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return (0);
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@ -29,16 +29,15 @@
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*
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* RMI_BSD */
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#ifndef _RMI_PIC_H_
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#define _RMI_PIC_H_
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#include <sys/cdefs.h>
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#define _RMI_PIC_H_
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#include <sys/cdefs.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <mips/rmi/iomap.h>
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#define PIC_IRT_WD_INDEX 0
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#define PIC_IRT_TIMER_INDEX(i) (1 + (i))
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#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX
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#define PIC_IRT_UART_0_INDEX 9
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#define PIC_IRT_UART_1_INDEX 10
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#define PIC_IRT_I2C_0_INDEX 11
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@ -70,7 +69,6 @@
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#define PIC_IRT_PCIE_FATAL_INDEX 29
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#define PIC_IRT_GPIO_B_INDEX 30
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#define PIC_IRT_USB_INDEX 31
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#define PIC_NUM_IRTS 32
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#define PIC_CLOCK_TIMER 7
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@ -102,7 +100,6 @@
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#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
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#define PIC_TIMER_HZ 66000000U
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/*
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* We use a simple mapping form PIC interrupts to CPU IRQs.
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* The PIC interrupts 0-31 are mapped to CPU irq's 8-39.
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@ -111,7 +108,7 @@
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*/
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#define PIC_IRQ_BASE 8
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#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
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#define PIC_IRT_FIRST_IRQ PIC_IRQ_BASE
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#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
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#define PIC_WD_IRQ (PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
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#define PIC_TIMER_IRQ(i) (PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i))
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@ -137,7 +134,6 @@
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#define PIC_BRIDGE_BERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
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#define PIC_BRIDGE_TB_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
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#define PIC_BRIDGE_AERR_NMI_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
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#define PIC_BRIDGE_ERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
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#define PIC_PCIE_LINK0_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
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#define PIC_PCIE_LINK1_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
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@ -148,9 +144,10 @@
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#define PIC_GPIO_B_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
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#define PIC_USB_IRQ (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
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#define PIC_IRT_LAST_IRQ PIC_USB_IRQ
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#define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_IRQ(0)) && ((irq) <= PIC_TIMER_IRQ(7)))
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#define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && ((irq) <= PIC_IRT_LAST_IRQ))
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#define PIC_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \
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(irq) < PIC_IRQ_BASE + PIC_NUM_IRTS)
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#define PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) && \
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(i) <= PIC_IRT_TIMER_INDEX(7))
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extern struct mtx xlr_pic_lock;
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@ -187,35 +184,11 @@ pic_update_control(__uint32_t control)
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}
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static __inline void
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pic_ack(int irq)
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pic_ack(int picintr)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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/* ack the pic, if needed */
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if (!PIC_IRQ_IS_IRT(irq))
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return;
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if (PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
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mtx_unlock_spin(&xlr_pic_lock);
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}
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return;
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}
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static __inline void
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pic_delayed_ack(int irq)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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if (!PIC_IRQ_IS_IRT(irq))
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return;
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if (!PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
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mtx_lock_spin(&xlr_pic_lock);
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xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
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mtx_unlock_spin(&xlr_pic_lock);
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}
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return;
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xlr_write_reg(mmio, PIC_INT_ACK, 1 << picintr);
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}
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static __inline
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@ -230,13 +203,11 @@ void pic_send_ipi(int cpu, int ipi)
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}
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static __inline
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void pic_setup_intr(int picintr, int irq, uint32_t cpumask)
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void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level)
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{
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xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
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int level;
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mtx_lock_spin(&xlr_pic_lock);
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level = PIC_IRQ_IS_EDGE_TRIGGERED(irq);
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xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
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xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1 << 31) | (level << 30) |
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(1 << 6) | irq));
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@ -305,7 +305,7 @@ xlr_pic_init(void)
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/* Initialize all IRT entries */
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for (i = 0; i < PIC_NUM_IRTS; i++) {
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irq = PIC_INTR_TO_IRQ(i);
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level = PIC_IRQ_IS_EDGE_TRIGGERED(irq);
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level = PIC_IS_EDGE_TRIGGERED(i);
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/* Bind all PIC irqs to cpu 0 */
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xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
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@ -575,11 +575,11 @@ platform_init_ap(int cpuid)
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stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
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mips_wr_status(stat);
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xlr_unmask_hard_irq((void *)IRQ_IPI);
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xlr_unmask_hard_irq((void *)IRQ_TIMER);
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xlr_enable_irq(IRQ_IPI);
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xlr_enable_irq(IRQ_TIMER);
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if (xlr_thr_id() == 0) {
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xlr_msgring_cpu_init();
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xlr_unmask_hard_irq((void *)IRQ_MSGRING);
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xlr_enable_irq(IRQ_MSGRING);
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}
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return;
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@ -403,24 +403,15 @@ xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr,
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}
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static void
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bridge_pcix_ack(void *arg)
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bridge_pcix_ack(int irq)
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{
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xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
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}
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static void
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bridge_pcix_mask_ack(void *arg)
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bridge_pcie_ack(int irq)
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{
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xlr_mask_hard_irq(arg);
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bridge_pcix_ack(arg);
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}
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static void
|
||||
bridge_pcie_ack(void *arg)
|
||||
{
|
||||
int irq = (intptr_t)arg;
|
||||
uint32_t reg;
|
||||
xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
|
||||
|
||||
@ -443,14 +434,6 @@ bridge_pcie_ack(void *arg)
|
||||
xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff);
|
||||
}
|
||||
|
||||
static void
|
||||
bridge_pcie_mask_ack(void *arg)
|
||||
{
|
||||
|
||||
xlr_mask_hard_irq(arg);
|
||||
bridge_pcie_ack(arg);
|
||||
}
|
||||
|
||||
static int
|
||||
mips_platform_pci_setup_intr(device_t dev, device_t child,
|
||||
struct resource *irq, int flags,
|
||||
@ -475,17 +458,13 @@ mips_platform_pci_setup_intr(device_t dev, device_t child,
|
||||
return (0);
|
||||
|
||||
if (xlr_board_info.is_xls == 0) {
|
||||
xlr_cpu_establish_hardintr(device_get_name(child), filt,
|
||||
intr, arg, PIC_PCIX_IRQ, flags, cookiep,
|
||||
bridge_pcix_mask_ack, xlr_unmask_hard_irq,
|
||||
bridge_pcix_ack, NULL);
|
||||
pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1);
|
||||
xlr_establish_intr(device_get_name(child), filt,
|
||||
intr, arg, PIC_PCIX_IRQ, flags, cookiep, bridge_pcix_ack);
|
||||
pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 0);
|
||||
} else {
|
||||
xlr_cpu_establish_hardintr(device_get_name(child), filt,
|
||||
intr, arg, xlrirq, flags, cookiep,
|
||||
bridge_pcie_mask_ack, xlr_unmask_hard_irq,
|
||||
bridge_pcie_ack, NULL);
|
||||
pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1);
|
||||
xlr_establish_intr(device_get_name(child), filt,
|
||||
intr, arg, xlrirq, flags, cookiep, bridge_pcie_ack);
|
||||
pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 0);
|
||||
}
|
||||
|
||||
return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user