Initial import of Ralink/Mediatek MIPS SoC support #2

This revision adds the following to the Mediatek/Ralink support:

- initial support for "clocks" FDT property, currently based on fdt_clock
- initial support for "resets" FDT property, currently based on the
  fdt_reset interface from D5826
- initial support for "pinctrl,bits" functionality via FDT. May be extended
  in the future to cover a better and fuller pinctrl implementation

Approved by:	adrian (mentor)
Sponsored by:	Smartcom - Bulgaria AD
Differential Revision:	https://reviews.freebsd.org/D5827

sys/mips/mediatek/mtk_clock.c

@@ -0,0 +1,156 @@
+/*-
+ * Copyright (c) 2016 Stanislav Galabov
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+#include <dev/fdt/fdt_clock.h>
+
+#include <mips/mediatek/mtk_sysctl.h>
+
+#include "fdt_clock_if.h"
+
+static const struct ofw_compat_data compat_data[] = {
+	{ "ralink,rt2880-clock",	1 },
+
+	/* Sentinel */
+	{ NULL,				0 }
+};
+
+static int
+mtk_clock_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+		return (ENXIO);
+
+	device_set_desc(dev, "MTK Clock Controller");
+
+	return (0);
+}
+
+static int
+mtk_clock_attach(device_t dev)
+{
+
+	if (device_get_unit(dev) != 0) {
+		device_printf(dev, "Only one clock control allowed\n");
+		return (ENXIO);
+	}
+
+	fdt_clock_register_provider(dev);
+
+	return (0);
+}
+
+#define CLOCK_ENABLE	1
+#define CLOCK_DISABLE	0
+
+static int
+mtk_clock_set(device_t dev, int index, int value)
+{
+	uint32_t mask;
+
+	/* Clock config register holds 32 clock gating bits */
+	if (index < 0 || index > 31)
+		return (EINVAL);
+
+	mask = (1u << index);
+
+	if (value == CLOCK_ENABLE)
+		mtk_sysctl_clr_set(SYSCTL_CLKCFG1, 0, mask);
+	else
+		mtk_sysctl_clr_set(SYSCTL_CLKCFG1, mask, 0);
+
+	return (0);
+}
+
+static int
+mtk_clock_enable(device_t dev, int index)
+{
+
+	return mtk_clock_set(dev, index, CLOCK_ENABLE);
+}
+
+static int
+mtk_clock_disable(device_t dev, int index)
+{
+
+	return mtk_clock_set(dev, index, CLOCK_DISABLE);
+}
+
+static int
+mtk_clock_get_info(device_t dev, int index, struct fdt_clock_info *info)
+{
+	uint32_t mask;
+
+	if (index < 0 || index > 31 || info == NULL)
+		return (EINVAL);
+
+	if (mtk_sysctl_get(SYSCTL_CLKCFG1) & mask)
+		info->flags = FDT_CIFLAG_RUNNING;
+	else
+		info->flags = 0;
+
+	return (0);
+}
+
+static device_method_t mtk_clock_methods[] = {
+	DEVMETHOD(device_probe,		mtk_clock_probe),
+	DEVMETHOD(device_attach,	mtk_clock_attach),
+
+	/* fdt_clock interface */
+	DEVMETHOD(fdt_clock_enable,	mtk_clock_enable),
+	DEVMETHOD(fdt_clock_disable,	mtk_clock_disable),
+	DEVMETHOD(fdt_clock_get_info,	mtk_clock_get_info),
+
+	DEVMETHOD_END
+};
+
+static driver_t mtk_clock_driver = {
+	"clkctrl",
+	mtk_clock_methods,
+	0,
+};
+static devclass_t mtk_clock_devclass;
+
+EARLY_DRIVER_MODULE(mtk_clock, simplebus, mtk_clock_driver, mtk_clock_devclass,
+    0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_EARLY);
+
+MODULE_DEPEND(mtk_clock, mtk_sysctl, 1, 1, 1);

sys/mips/mediatek/mtk_pinctrl.c

@@ -0,0 +1,114 @@
+/*-
+ * Copyright (c) 2016 Stanislav Galabov
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/fdt/fdt_pinctrl.h>
+#include <mips/mediatek/mtk_sysctl.h>
+
+#include "fdt_pinctrl_if.h"
+
+static const struct ofw_compat_data compat_data[] = {
+	{ "ralink,rt2880-pinctrl",	1 },
+
+	/* Sentinel */
+	{ NULL,				0 }
+};
+
+static int
+mtk_pinctrl_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+		return (ENXIO);
+
+	device_set_desc(dev, "MTK Pin Controller");
+
+	return (0);
+}
+
+static int
+mtk_pinctrl_attach(device_t dev)
+{
+
+	if (device_get_unit(dev) != 0) {
+		device_printf(dev, "Only one pin control allowed\n");
+		return (ENXIO);
+	}
+
+	fdt_pinctrl_register(dev, "pinctrl-single,bits");
+	fdt_pinctrl_configure_tree(dev);
+
+	if (bootverbose)
+		device_printf(dev, "GPIO mode: 0x%08x\n",
+		    mtk_sysctl_get(SYSCTL_GPIOMODE));
+
+	return (0);
+}
+
+static int
+mtk_pinctrl_configure(device_t dev, phandle_t cfgxref)
+{
+
+	return (EINVAL);
+}
+
+static device_method_t mtk_pinctrl_methods[] = {
+	DEVMETHOD(device_probe,			mtk_pinctrl_probe),
+	DEVMETHOD(device_attach,		mtk_pinctrl_attach),
+
+	/* fdt_pinctrl interface */
+	DEVMETHOD(fdt_pinctrl_configure,	mtk_pinctrl_configure),
+
+	DEVMETHOD_END
+};
+
+static driver_t mtk_pinctrl_driver = {
+	"pinctrl",
+	mtk_pinctrl_methods,
+	0,
+};
+static devclass_t mtk_pinctrl_devclass;
+
+EARLY_DRIVER_MODULE(mtk_pinctrl, simplebus, mtk_pinctrl_driver,
+    mtk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_EARLY);
+
+MODULE_DEPEND(mtk_pinctrl, mtk_sysctl, 1, 1, 1);

sys/mips/mediatek/mtk_reset.c

@@ -0,0 +1,139 @@
+/*-
+ * Copyright (c) 2016 Stanislav Galabov
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions, and the following disclaimer,
+ *    without modification, immediately at the beginning of the file.
+ * 2. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/bus.h>
+#include <sys/module.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/openfirm.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <mips/mediatek/fdt_reset.h>
+#include <mips/mediatek/mtk_sysctl.h>
+
+#include "fdt_reset_if.h"
+
+static const struct ofw_compat_data compat_data[] = {
+	{ "ralink,rt2880-reset",	1 },
+
+	/* Sentinel */
+	{ NULL,				0 }
+};
+
+static int
+mtk_reset_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+		return (ENXIO);
+
+	device_set_desc(dev, "MTK Reset Controller");
+
+	return (0);
+}
+
+static int
+mtk_reset_attach(device_t dev)
+{
+
+	if (device_get_unit(dev) != 0) {
+		device_printf(dev, "Only one reset control allowed\n");
+		return (ENXIO);
+	}
+
+	fdt_reset_register_provider(dev);
+
+	return (0);
+}
+
+#define RESET_ASSERT	1
+#define RESET_DEASSERT	0
+
+static int
+mtk_reset_set(device_t dev, int index, int value)
+{
+	uint32_t mask;
+
+	/* index 0 is SoC reset, indices 1 - 31 are valid peripheral resets */
+	if (index < 1 || index > 31)
+		return (EINVAL);
+
+	mask = (1u << index);
+
+	if (value == RESET_ASSERT)
+		mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 0, mask);
+	else
+		mtk_sysctl_clr_set(SYSCTL_RSTCTRL, mask, 0);
+
+	return (0);
+}
+
+static int
+mtk_reset_assert(device_t dev, int index)
+{
+
+	return mtk_reset_set(dev, index, RESET_ASSERT);
+}
+
+static int
+mtk_reset_deassert(device_t dev, int index)
+{
+
+	return mtk_reset_set(dev, index, RESET_DEASSERT);
+}
+
+static device_method_t mtk_reset_methods[] = {
+	DEVMETHOD(device_probe,		mtk_reset_probe),
+	DEVMETHOD(device_attach,	mtk_reset_attach),
+
+	/* fdt_reset interface */
+	DEVMETHOD(fdt_reset_assert,	mtk_reset_assert),
+	DEVMETHOD(fdt_reset_deassert,	mtk_reset_deassert),
+
+	DEVMETHOD_END
+};
+
+static driver_t mtk_reset_driver = {
+	"rstctrl",
+	mtk_reset_methods,
+	0,
+};
+static devclass_t mtk_reset_devclass;
+
+EARLY_DRIVER_MODULE(mtk_reset, simplebus, mtk_reset_driver, mtk_reset_devclass,
+    0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_EARLY);
+
+MODULE_DEPEND(mtk_reset, mtk_sysctl, 1, 1, 1);