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The improvements to clock statistics by Tor Egge
Wrappered and enabled by the define BETTER_CLOCK (on by default in smpyests.h) apic_vector.s also contains a small change I (smp) made to eliminate the double level INT problem. It seems stable, but I haven't the tools in place to prove it fixes the problem. Reviewed by: smp@csn.net Submitted by: Tor Egge <Tor.Egge@idi.ntnu.no>
This commit is contained in:
Steve Passe
parent
af65141672
commit
baf41202ca
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=31638
@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: apic_vector.s,v 1.22 1997/09/21 21:40:53 gibbs Exp $
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* $Id: apic_vector.s,v 1.38 1997/12/04 19:46:26 smp Exp smp $
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*/
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@ -190,7 +190,12 @@ IDTVEC(vec_name) ; \
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#define UNMASK_IRQ(irq_num) \
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IMASK_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), _apic_imen ; \
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je 9f ; \
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jne 7f ; /* bit set, masked */ \
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testl $IRQ_BIT(irq_num), _apic_pin_trigger ; \
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jz 9f ; /* edge, don't EOI */ \
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movl $0, lapic_eoi ; /* should be safe */ \
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jmp 9f ; /* skip unmasking */ \
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7: \
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andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
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movl _ioapic,%ecx ; /* ioapic[0]addr */ \
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movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \
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@ -239,7 +244,7 @@ IDTVEC(vec_name) ; \
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orl $IRQ_BIT(irq_num), _cil ; \
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AVCPL_UNLOCK ; \
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; \
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movl $0, lapic_eoi ; /* XXX too soon? */ \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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@ -314,7 +319,7 @@ IDTVEC(vec_name) ; \
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jne 2f ; /* this INT masked */ \
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AVCPL_UNLOCK ; \
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; \
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movl $0, lapic_eoi ; /* XXX too soon? */ \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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@ -406,6 +411,132 @@ _Xinvltlb:
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iret
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#ifdef BETTER_CLOCK
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/*
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* Executed by a CPU when it receives an Xcpucheckstate IPI from another CPU,
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*
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* - Stores current cpu state in checkstate_cpustate[cpuid]
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* 0 == user, 1 == sys, 2 == intr
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* - Stores current process in checkstate_curproc[cpuid]
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*
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* - Signals its receipt by setting bit cpuid in checkstate_probed_cpus.
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*
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* stack: 0 -> ds, 4 -> ebx, 8 -> eax, 12 -> eip, 16 -> cs, 20 -> eflags
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpucheckstate
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.globl _checkstate_cpustate
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.globl _checkstate_curproc
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.globl _checkstate_pc
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_Xcpucheckstate:
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pushl %eax
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pushl %ebx
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pushl %ds /* save current data segment */
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movl $KDSEL, %eax
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movl %ax, %ds /* use KERNEL data segment */
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movl $0, lapic_eoi /* End Of Interrupt to APIC */
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movl $0, %ebx
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movl 16(%esp), %eax
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andl $3, %eax
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cmpl $3, %eax
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je 1f
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#ifdef VM86
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testl $PSL_VM, 20(%esp)
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jne 1f
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#endif
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incl %ebx /* system or interrupt */
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#ifdef CPL_AND_CML
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cmpl $0, _inside_intr
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je 1f
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incl %ebx /* interrupt */
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#endif
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1:
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movl _cpuid, %eax
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movl %ebx, _checkstate_cpustate(,%eax,4)
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movl _curproc, %ebx
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movl %ebx, _checkstate_curproc(,%eax,4)
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movl 12(%esp), %ebx
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movl %ebx, _checkstate_pc(,%eax,4)
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lock /* checkstate_probed_cpus |= (1<<id) */
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btsl %eax, _checkstate_probed_cpus
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popl %ds /* restore previous data segment */
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popl %ebx
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popl %eax
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iret
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/*
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* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
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*
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* - Signals its receipt by clearing bit cpuid in checkstate_need_ast.
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*
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* - We need a better method of triggering asts on other cpus.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpuast
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_Xcpuast:
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PUSH_FRAME
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movl $KDSEL, %eax
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movl %ax, %ds /* use KERNEL data segment */
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movl %ax, %es
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movl _cpuid, %eax
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lock /* checkstate_need_ast &= ~(1<<id) */
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btrl %eax, _checkstate_need_ast
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movl $0, lapic_eoi /* End Of Interrupt to APIC */
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lock
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btsl %eax, _checkstate_pending_ast
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jc 1f
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FAKE_MCOUNT(12*4(%esp))
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/*
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* Giant locks do not come cheap.
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* A lot of cycles are going to be wasted here.
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*/
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call _get_isrlock
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AVCPL_LOCK
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#ifdef CPL_AND_CML
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movl _cml, %eax
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#else
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movl _cpl, %eax
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#endif
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pushl %eax
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AVCPL_UNLOCK
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lock
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incb _intr_nesting_level
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sti
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pushl $0
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lock
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orl $SWI_AST_PENDING, _ipending
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movl _cpuid, %eax
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lock
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btrl %eax, _checkstate_pending_ast
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MEXITCOUNT
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jmp _doreti
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1:
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/* We are already in the process of delivering an ast for this CPU */
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POP_FRAME
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iret
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#endif /* BETTER_CLOCK */
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/*
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* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
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*
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@ -561,6 +692,17 @@ _stopped_cpus:
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_started_cpus:
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.long 0
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#ifdef BETTER_CLOCK
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.globl _checkstate_probed_cpus
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.globl _checkstate_need_ast
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_checkstate_probed_cpus:
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.long 0
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_checkstate_need_ast:
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.long 0
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_checkstate_pending_ast:
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.long 0
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#endif
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.globl _apic_pin_trigger
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_apic_pin_trigger:
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.space (NAPIC * 4), 0
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@ -31,7 +31,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)isa_device.h 7.1 (Berkeley) 5/9/91
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* $Id: intr_machdep.h,v 1.10 1997/08/29 18:37:23 smp Exp smp $
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* $Id: intr_machdep.h,v 1.7 1997/08/29 18:45:21 fsmp Exp $
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*/
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#ifndef _I386_ISA_INTR_MACHDEP_H_
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@ -107,6 +107,12 @@
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/* TLB shootdowns */
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#define XINVLTLB_OFFSET (ICU_OFFSET + 112)
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#ifdef BETTER_CLOCK
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/* inter-cpu clock handling */
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#define XCPUCHECKSTATE_OFFSET (ICU_OFFSET + 113)
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#define XCPUAST_OFFSET (ICU_OFFSET + 114)
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#endif
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/* IPI to signal CPUs to stop and wait for another CPU to restart them */
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#define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
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@ -160,6 +166,10 @@ inthand_t
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inthand_t
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Xinvltlb, /* TLB shootdowns */
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#ifdef BETTER_CLOCK
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Xcpucheckstate, /* Check cpu state */
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Xcpuast, /* Additional software trap on other cpu */
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#endif
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Xcpustop, /* CPU stops & waits for another CPU to restart it */
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Xspuriousint; /* handle APIC "spurious INTs" */
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@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: apic_vector.s,v 1.22 1997/09/21 21:40:53 gibbs Exp $
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* $Id: apic_vector.s,v 1.38 1997/12/04 19:46:26 smp Exp smp $
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*/
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@ -190,7 +190,12 @@ IDTVEC(vec_name) ; \
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#define UNMASK_IRQ(irq_num) \
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IMASK_LOCK ; /* into critical reg */ \
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testl $IRQ_BIT(irq_num), _apic_imen ; \
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je 9f ; \
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jne 7f ; /* bit set, masked */ \
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testl $IRQ_BIT(irq_num), _apic_pin_trigger ; \
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jz 9f ; /* edge, don't EOI */ \
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movl $0, lapic_eoi ; /* should be safe */ \
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jmp 9f ; /* skip unmasking */ \
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7: \
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andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
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movl _ioapic,%ecx ; /* ioapic[0]addr */ \
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movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \
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@ -239,7 +244,7 @@ IDTVEC(vec_name) ; \
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orl $IRQ_BIT(irq_num), _cil ; \
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AVCPL_UNLOCK ; \
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; \
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movl $0, lapic_eoi ; /* XXX too soon? */ \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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@ -314,7 +319,7 @@ IDTVEC(vec_name) ; \
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jne 2f ; /* this INT masked */ \
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AVCPL_UNLOCK ; \
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; \
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movl $0, lapic_eoi ; /* XXX too soon? */ \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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@ -406,6 +411,132 @@ _Xinvltlb:
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iret
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#ifdef BETTER_CLOCK
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/*
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* Executed by a CPU when it receives an Xcpucheckstate IPI from another CPU,
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*
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* - Stores current cpu state in checkstate_cpustate[cpuid]
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* 0 == user, 1 == sys, 2 == intr
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* - Stores current process in checkstate_curproc[cpuid]
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*
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* - Signals its receipt by setting bit cpuid in checkstate_probed_cpus.
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*
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* stack: 0 -> ds, 4 -> ebx, 8 -> eax, 12 -> eip, 16 -> cs, 20 -> eflags
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpucheckstate
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.globl _checkstate_cpustate
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.globl _checkstate_curproc
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.globl _checkstate_pc
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_Xcpucheckstate:
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pushl %eax
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pushl %ebx
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pushl %ds /* save current data segment */
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movl $KDSEL, %eax
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movl %ax, %ds /* use KERNEL data segment */
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movl $0, lapic_eoi /* End Of Interrupt to APIC */
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movl $0, %ebx
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movl 16(%esp), %eax
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andl $3, %eax
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cmpl $3, %eax
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je 1f
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#ifdef VM86
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testl $PSL_VM, 20(%esp)
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jne 1f
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#endif
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incl %ebx /* system or interrupt */
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#ifdef CPL_AND_CML
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cmpl $0, _inside_intr
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je 1f
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incl %ebx /* interrupt */
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#endif
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1:
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movl _cpuid, %eax
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movl %ebx, _checkstate_cpustate(,%eax,4)
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movl _curproc, %ebx
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movl %ebx, _checkstate_curproc(,%eax,4)
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movl 12(%esp), %ebx
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movl %ebx, _checkstate_pc(,%eax,4)
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lock /* checkstate_probed_cpus |= (1<<id) */
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btsl %eax, _checkstate_probed_cpus
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popl %ds /* restore previous data segment */
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popl %ebx
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popl %eax
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iret
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/*
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* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
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*
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* - Signals its receipt by clearing bit cpuid in checkstate_need_ast.
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*
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* - We need a better method of triggering asts on other cpus.
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*/
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.text
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SUPERALIGN_TEXT
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.globl _Xcpuast
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_Xcpuast:
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PUSH_FRAME
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movl $KDSEL, %eax
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movl %ax, %ds /* use KERNEL data segment */
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movl %ax, %es
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movl _cpuid, %eax
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lock /* checkstate_need_ast &= ~(1<<id) */
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btrl %eax, _checkstate_need_ast
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movl $0, lapic_eoi /* End Of Interrupt to APIC */
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lock
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btsl %eax, _checkstate_pending_ast
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jc 1f
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FAKE_MCOUNT(12*4(%esp))
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/*
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* Giant locks do not come cheap.
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* A lot of cycles are going to be wasted here.
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*/
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call _get_isrlock
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AVCPL_LOCK
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#ifdef CPL_AND_CML
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movl _cml, %eax
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#else
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movl _cpl, %eax
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#endif
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pushl %eax
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AVCPL_UNLOCK
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lock
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incb _intr_nesting_level
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sti
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pushl $0
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lock
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orl $SWI_AST_PENDING, _ipending
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movl _cpuid, %eax
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lock
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btrl %eax, _checkstate_pending_ast
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MEXITCOUNT
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jmp _doreti
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1:
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/* We are already in the process of delivering an ast for this CPU */
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POP_FRAME
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iret
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#endif /* BETTER_CLOCK */
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/*
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* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
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*
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@ -561,6 +692,17 @@ _stopped_cpus:
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_started_cpus:
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.long 0
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#ifdef BETTER_CLOCK
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.globl _checkstate_probed_cpus
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.globl _checkstate_need_ast
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_checkstate_probed_cpus:
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.long 0
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_checkstate_need_ast:
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.long 0
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_checkstate_pending_ast:
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.long 0
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#endif
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.globl _apic_pin_trigger
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_apic_pin_trigger:
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.space (NAPIC * 4), 0
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@ -1,6 +1,6 @@
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/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: apic_vector.s,v 1.22 1997/09/21 21:40:53 gibbs Exp $
|
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* $Id: apic_vector.s,v 1.38 1997/12/04 19:46:26 smp Exp smp $
|
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*/
|
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|
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|
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@ -190,7 +190,12 @@ IDTVEC(vec_name) ; \
|
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#define UNMASK_IRQ(irq_num) \
|
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IMASK_LOCK ; /* into critical reg */ \
|
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testl $IRQ_BIT(irq_num), _apic_imen ; \
|
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je 9f ; \
|
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jne 7f ; /* bit set, masked */ \
|
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testl $IRQ_BIT(irq_num), _apic_pin_trigger ; \
|
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jz 9f ; /* edge, don't EOI */ \
|
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movl $0, lapic_eoi ; /* should be safe */ \
|
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jmp 9f ; /* skip unmasking */ \
|
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7: \
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andl $~IRQ_BIT(irq_num), _apic_imen ;/* clear mask bit */ \
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movl _ioapic,%ecx ; /* ioapic[0]addr */ \
|
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movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \
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@ -239,7 +244,7 @@ IDTVEC(vec_name) ; \
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orl $IRQ_BIT(irq_num), _cil ; \
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AVCPL_UNLOCK ; \
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; \
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movl $0, lapic_eoi ; /* XXX too soon? */ \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
|
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@ -314,7 +319,7 @@ IDTVEC(vec_name) ; \
|
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jne 2f ; /* this INT masked */ \
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AVCPL_UNLOCK ; \
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; \
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movl $0, lapic_eoi ; /* XXX too soon? */ \
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;;; movl $0, lapic_eoi ; /* XXX too soon? */ \
|
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incb _intr_nesting_level ; \
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; \
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/* entry point used by doreti_unpend for HWIs. */ \
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@ -406,6 +411,132 @@ _Xinvltlb:
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iret
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||||
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||||
|
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#ifdef BETTER_CLOCK
|
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|
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/*
|
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* Executed by a CPU when it receives an Xcpucheckstate IPI from another CPU,
|
||||
*
|
||||
* - Stores current cpu state in checkstate_cpustate[cpuid]
|
||||
* 0 == user, 1 == sys, 2 == intr
|
||||
* - Stores current process in checkstate_curproc[cpuid]
|
||||
*
|
||||
* - Signals its receipt by setting bit cpuid in checkstate_probed_cpus.
|
||||
*
|
||||
* stack: 0 -> ds, 4 -> ebx, 8 -> eax, 12 -> eip, 16 -> cs, 20 -> eflags
|
||||
*/
|
||||
|
||||
.text
|
||||
SUPERALIGN_TEXT
|
||||
.globl _Xcpucheckstate
|
||||
.globl _checkstate_cpustate
|
||||
.globl _checkstate_curproc
|
||||
.globl _checkstate_pc
|
||||
_Xcpucheckstate:
|
||||
pushl %eax
|
||||
pushl %ebx
|
||||
pushl %ds /* save current data segment */
|
||||
|
||||
movl $KDSEL, %eax
|
||||
movl %ax, %ds /* use KERNEL data segment */
|
||||
|
||||
movl $0, lapic_eoi /* End Of Interrupt to APIC */
|
||||
|
||||
movl $0, %ebx
|
||||
movl 16(%esp), %eax
|
||||
andl $3, %eax
|
||||
cmpl $3, %eax
|
||||
je 1f
|
||||
#ifdef VM86
|
||||
testl $PSL_VM, 20(%esp)
|
||||
jne 1f
|
||||
#endif
|
||||
incl %ebx /* system or interrupt */
|
||||
#ifdef CPL_AND_CML
|
||||
cmpl $0, _inside_intr
|
||||
je 1f
|
||||
incl %ebx /* interrupt */
|
||||
#endif
|
||||
1:
|
||||
movl _cpuid, %eax
|
||||
movl %ebx, _checkstate_cpustate(,%eax,4)
|
||||
movl _curproc, %ebx
|
||||
movl %ebx, _checkstate_curproc(,%eax,4)
|
||||
movl 12(%esp), %ebx
|
||||
movl %ebx, _checkstate_pc(,%eax,4)
|
||||
|
||||
lock /* checkstate_probed_cpus |= (1<<id) */
|
||||
btsl %eax, _checkstate_probed_cpus
|
||||
|
||||
popl %ds /* restore previous data segment */
|
||||
popl %ebx
|
||||
popl %eax
|
||||
iret
|
||||
|
||||
/*
|
||||
* Executed by a CPU when it receives an Xcpuast IPI from another CPU,
|
||||
*
|
||||
* - Signals its receipt by clearing bit cpuid in checkstate_need_ast.
|
||||
*
|
||||
* - We need a better method of triggering asts on other cpus.
|
||||
*/
|
||||
|
||||
.text
|
||||
SUPERALIGN_TEXT
|
||||
.globl _Xcpuast
|
||||
_Xcpuast:
|
||||
PUSH_FRAME
|
||||
movl $KDSEL, %eax
|
||||
movl %ax, %ds /* use KERNEL data segment */
|
||||
movl %ax, %es
|
||||
|
||||
movl _cpuid, %eax
|
||||
lock /* checkstate_need_ast &= ~(1<<id) */
|
||||
btrl %eax, _checkstate_need_ast
|
||||
movl $0, lapic_eoi /* End Of Interrupt to APIC */
|
||||
|
||||
lock
|
||||
btsl %eax, _checkstate_pending_ast
|
||||
jc 1f
|
||||
|
||||
FAKE_MCOUNT(12*4(%esp))
|
||||
|
||||
/*
|
||||
* Giant locks do not come cheap.
|
||||
* A lot of cycles are going to be wasted here.
|
||||
*/
|
||||
call _get_isrlock
|
||||
|
||||
AVCPL_LOCK
|
||||
#ifdef CPL_AND_CML
|
||||
movl _cml, %eax
|
||||
#else
|
||||
movl _cpl, %eax
|
||||
#endif
|
||||
pushl %eax
|
||||
AVCPL_UNLOCK
|
||||
lock
|
||||
incb _intr_nesting_level
|
||||
sti
|
||||
|
||||
pushl $0
|
||||
|
||||
lock
|
||||
orl $SWI_AST_PENDING, _ipending
|
||||
|
||||
movl _cpuid, %eax
|
||||
lock
|
||||
btrl %eax, _checkstate_pending_ast
|
||||
|
||||
MEXITCOUNT
|
||||
jmp _doreti
|
||||
1:
|
||||
/* We are already in the process of delivering an ast for this CPU */
|
||||
POP_FRAME
|
||||
iret
|
||||
|
||||
#endif /* BETTER_CLOCK */
|
||||
|
||||
|
||||
/*
|
||||
* Executed by a CPU when it receives an Xcpustop IPI from another CPU,
|
||||
*
|
||||
@ -561,6 +692,17 @@ _stopped_cpus:
|
||||
_started_cpus:
|
||||
.long 0
|
||||
|
||||
#ifdef BETTER_CLOCK
|
||||
.globl _checkstate_probed_cpus
|
||||
.globl _checkstate_need_ast
|
||||
_checkstate_probed_cpus:
|
||||
.long 0
|
||||
_checkstate_need_ast:
|
||||
.long 0
|
||||
_checkstate_pending_ast:
|
||||
.long 0
|
||||
#endif
|
||||
|
||||
.globl _apic_pin_trigger
|
||||
_apic_pin_trigger:
|
||||
.space (NAPIC * 4), 0
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: @(#)isa_device.h 7.1 (Berkeley) 5/9/91
|
||||
* $Id: intr_machdep.h,v 1.10 1997/08/29 18:37:23 smp Exp smp $
|
||||
* $Id: intr_machdep.h,v 1.7 1997/08/29 18:45:21 fsmp Exp $
|
||||
*/
|
||||
|
||||
#ifndef _I386_ISA_INTR_MACHDEP_H_
|
||||
@ -107,6 +107,12 @@
|
||||
/* TLB shootdowns */
|
||||
#define XINVLTLB_OFFSET (ICU_OFFSET + 112)
|
||||
|
||||
#ifdef BETTER_CLOCK
|
||||
/* inter-cpu clock handling */
|
||||
#define XCPUCHECKSTATE_OFFSET (ICU_OFFSET + 113)
|
||||
#define XCPUAST_OFFSET (ICU_OFFSET + 114)
|
||||
#endif
|
||||
|
||||
/* IPI to signal CPUs to stop and wait for another CPU to restart them */
|
||||
#define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
|
||||
|
||||
@ -160,6 +166,10 @@ inthand_t
|
||||
|
||||
inthand_t
|
||||
Xinvltlb, /* TLB shootdowns */
|
||||
#ifdef BETTER_CLOCK
|
||||
Xcpucheckstate, /* Check cpu state */
|
||||
Xcpuast, /* Additional software trap on other cpu */
|
||||
#endif
|
||||
Xcpustop, /* CPU stops & waits for another CPU to restart it */
|
||||
Xspuriousint; /* handle APIC "spurious INTs" */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user