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Nail the short cable problem the exact way National says it should be.
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0608b4a20c
commit
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=139806
@ -1908,14 +1908,14 @@ sis_initl(struct sis_softc *sc)
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}
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/*
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* Page 78 of the DP83815 data sheet (september 2002 version)
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* Short Cable Receive Errors (MP21.E)
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* also: Page 78 of the DP83815 data sheet (september 2002 version)
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* recommends the following register settings "for optimum
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* performance." for rev 15C. The driver from NS also sets
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* the PHY_CR register for later versions.
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*/
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if (sc->sis_type == SIS_TYPE_83815) {
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if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr <= NS_SRR_15D) {
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
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/* DC speed = 01 */
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CSR_WRITE_4(sc, NS_PHY_CR, 0x189C);
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if (sc->sis_srr == NS_SRR_15C) {
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/* set val for c2 */
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@ -2004,29 +2004,24 @@ sis_initl(struct sis_softc *sc)
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SIS_CLRBIT(sc, SIS_RX_CFG, SIS_RXCFG_RX_TXPKTS);
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}
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if (sc->sis_type == SIS_TYPE_83815 && sc->sis_srr < NS_SRR_16A &&
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if (sc->sis_type == SIS_TYPE_83815 &&
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IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) {
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uint32_t reg;
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/*
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* Some DP83815s experience problems when used with short
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* (< 30m/100ft) Ethernet cables in 100BaseTX mode. This
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* sequence adjusts the DSP's signal attenuation to fix the
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* problem.
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* Short Cable Receive Errors (MP21.E)
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*/
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0x0001);
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reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
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/* Allow coefficient to be read */
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CSR_WRITE_4(sc, NS_PHY_DSPCFG, (reg & 0xfff) | 0x1000);
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DELAY(100);
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reg = CSR_READ_4(sc, NS_PHY_TDATA);
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if ((reg & 0x0080) == 0 ||
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(reg > 0xd8 && reg <= 0xff)) {
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device_printf(sc->sis_self, "Applying short cable fix (reg=%x)\n", reg);
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reg = CSR_READ_4(sc, NS_PHY_DSPCFG) & 0xfff;
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CSR_WRITE_4(sc, NS_PHY_DSPCFG, reg | 0x1000);
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DELAY(100000);
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reg = CSR_READ_4(sc, NS_PHY_TDATA) & 0xff;
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if ((reg & 0x0080) == 0 || (reg > 0xd8 && reg <= 0xff)) {
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device_printf(sc->sis_self,
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"Applying short cable fix (reg=%x)\n", reg);
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CSR_WRITE_4(sc, NS_PHY_TDATA, 0x00e8);
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/* Adjust coefficient and prevent change */
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SIS_SETBIT(sc, NS_PHY_DSPCFG, 0x20);
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reg = CSR_READ_4(sc, NS_PHY_DSPCFG);
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SIS_SETBIT(sc, NS_PHY_DSPCFG, reg | 0x20);
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}
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CSR_WRITE_4(sc, NS_PHY_PAGE, 0);
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}
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