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Document the AR9285/AR9485 LNA configuration information that's
stored in the ctl/ext RSSI field for chain 2. Tested: * AR9285, STA
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=251399
@ -157,6 +157,32 @@ struct ath_rx_status {
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#define HAL_RX_IS_APSD 0x0100 /* Is ASPD trigger frame */
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#define HAL_RX_STBC 0x0200 /* Is an STBC frame */
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/*
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* This is the format of RSSI[2] on the AR9285/AR9485.
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* It encodes the LNA configuration information.
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*
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* For boards with an external diversity antenna switch,
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* HAL_RX_LNA_EXTCFG encodes which configuration was
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* used (antenna 1 or antenna 2.) This feeds into the
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* switch table and ensures that the given antenna was
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* connected to an LNA.
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*/
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#define HAL_RX_LNA_LNACFG 0x80 /* 1 = main LNA config used, 0 = ALT */
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#define HAL_RX_LNA_EXTCFG 0x40 /* 0 = external diversity ant1, 1 = ant2 */
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#define HAL_RX_LNA_CFG_USED 0x30 /* 2 bits; LNA config used on RX */
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#define HAL_RX_LNA_CFG_USED_S 4
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#define HAL_RX_LNA_CFG_MAIN 0x0c /* 2 bits; "Main" LNA config */
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#define HAL_RX_LNA_CFG_ALT 0x02 /* 2 bits; "Alt" LNA config */
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/*
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* This is the format of RSSI_EXT[2] on the AR9285/AR9485.
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* It encodes the switch table configuration and fast diversity
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* value.
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*/
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#define HAL_RX_LNA_FASTDIV 0x40 /* 1 = fast diversity measurement done */
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#define HAL_RX_LNA_SWITCH_0 0x30 /* 2 bits; sw_0[1:0] */
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#define HAL_RX_LNA_SWITCH_COM 0x0f /* 4 bits, sw_com[3:0] */
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enum {
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HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
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HAL_PHYERR_TIMING = 1, /* Timing error */
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