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ARM: cpufunc_domains, cpufunc_faultstatus and cpufunc_faultaddress
functions are equal for all ARM variants. Remove them from cpu_functions table.
This commit is contained in:
Michal Meloun
parent
0d87509689
commit
bf488b9dde
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=295096
@ -105,16 +105,12 @@ int ctrl;
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struct cpu_functions arm9_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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arm9_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/* TLB functions */
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@ -164,16 +160,12 @@ struct cpu_functions arm9_cpufuncs = {
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struct cpu_functions armv5_ec_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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armv5_ec_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/* TLB functions */
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@ -222,16 +214,12 @@ struct cpu_functions armv5_ec_cpufuncs = {
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struct cpu_functions sheeva_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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sheeva_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/* TLB functions */
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@ -281,16 +269,12 @@ struct cpu_functions sheeva_cpufuncs = {
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struct cpu_functions pj4bv7_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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armv7_drain_writebuf, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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armv7_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/* TLB functions */
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@ -341,16 +325,12 @@ struct cpu_functions pj4bv7_cpufuncs = {
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struct cpu_functions xscale_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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xscale_cpwait, /* cpwait */
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/* MMU functions */
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xscale_control, /* control */
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cpufunc_domains, /* domain */
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xscale_setttb, /* setttb */
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cpufunc_faultstatus, /* faultstatus */
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cpufunc_faultaddress, /* faultaddress */
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/* TLB functions */
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@ -401,16 +381,12 @@ struct cpu_functions xscale_cpufuncs = {
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struct cpu_functions xscalec3_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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xscale_cpwait, /* cpwait */
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/* MMU functions */
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xscale_control, /* control */
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cpufunc_domains, /* domain */
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xscalec3_setttb, /* setttb */
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cpufunc_faultstatus, /* faultstatus */
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cpufunc_faultaddress, /* faultaddress */
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/* TLB functions */
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@ -460,16 +436,12 @@ struct cpu_functions xscalec3_cpufuncs = {
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struct cpu_functions fa526_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* domain */
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fa526_setttb, /* setttb */
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cpufunc_faultstatus, /* faultstatus */
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cpufunc_faultaddress, /* faultaddress */
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/* TLB functions */
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@ -519,16 +491,12 @@ struct cpu_functions fa526_cpufuncs = {
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struct cpu_functions arm1176_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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arm11x6_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/* TLB functions */
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@ -578,16 +546,12 @@ struct cpu_functions arm1176_cpufuncs = {
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struct cpu_functions cortexa_cpufuncs = {
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/* CPU functions */
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cpufunc_id, /* id */
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cpufunc_nullop, /* cpwait */
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/* MMU functions */
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cpufunc_control, /* control */
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cpufunc_domains, /* Domain */
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armv7_setttb, /* Setttb */
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cpufunc_faultstatus, /* Faultstatus */
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cpufunc_faultaddress, /* Faultaddress */
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/*
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* TLB functions. ARMv7 does all TLB ops based on a unified TLB model
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@ -681,7 +645,7 @@ get_cachetype_cp15()
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__asm __volatile("mrc p15, 0, %0, c0, c0, 1"
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: "=r" (ctype));
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cpuid = cpufunc_id();
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cpuid = cpu_ident();
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/*
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* ...and thus spake the ARM ARM:
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*
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@ -788,7 +752,7 @@ get_cachetype_cp15()
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int
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set_cpufuncs()
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{
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cputype = cpufunc_id();
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cputype = cpu_ident();
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cputype &= CPU_ID_CPU_MASK;
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#ifdef CPU_ARM9
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@ -1074,7 +1038,7 @@ arm11x6_setup(void)
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uint32_t sbz=0;
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uint32_t cpuid;
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cpuid = cpufunc_id();
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cpuid = cpu_ident();
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cpuctrl =
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CPU_CONTROL_MMU_ENABLE |
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@ -62,16 +62,11 @@ END(cpufunc_nullop)
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*
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*/
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ENTRY(cpufunc_id)
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ENTRY(cpu_ident)
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mrc p15, 0, r0, c0, c0, 0
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RET
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END(cpufunc_id)
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ENTRY(cpufunc_cpuid)
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mrc p15, 0, r0, c0, c0, 0
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RET
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END(cpufunc_cpuid)
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ENTRY(cpu_get_control)
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mrc p15, 0, r0, c1, c0, 0
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RET
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@ -82,15 +77,15 @@ ENTRY(cpu_read_cache_config)
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RET
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END(cpu_read_cache_config)
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ENTRY(cpufunc_faultstatus)
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ENTRY(cpu_faultstatus)
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mrc p15, 0, r0, c5, c0, 0
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RET
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END(cpufunc_faultstatus)
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END(cpu_faultstatus)
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ENTRY(cpufunc_faultaddress)
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ENTRY(cpu_faultaddress)
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mrc p15, 0, r0, c6, c0, 0
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RET
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END(cpufunc_faultaddress)
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END(cpu_faultaddress)
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/*
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* Generic functions to write the internal coprocessor registers
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@ -110,10 +105,10 @@ ENTRY(cpufunc_control)
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END(cpufunc_control)
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#endif
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ENTRY(cpufunc_domains)
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ENTRY(cpu_domains)
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mcr p15, 0, r0, c3, c0, 0
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RET
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END(cpufunc_domains)
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END(cpu_domains)
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/*
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* Generic functions to read/modify/write the internal coprocessor registers
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@ -60,16 +60,12 @@ struct cpu_functions {
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/* CPU functions */
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u_int (*cf_id) (void);
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void (*cf_cpwait) (void);
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/* MMU functions */
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u_int (*cf_control) (u_int bic, u_int eor);
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void (*cf_domains) (u_int domains);
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void (*cf_setttb) (u_int ttb);
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u_int (*cf_faultstatus) (void);
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u_int (*cf_faultaddress) (void);
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/* TLB functions */
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@ -170,14 +166,10 @@ struct cpu_functions {
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extern struct cpu_functions cpufuncs;
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extern u_int cputype;
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#define cpu_ident() cpufuncs.cf_id()
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#define cpu_cpwait() cpufuncs.cf_cpwait()
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#define cpu_control(c, e) cpufuncs.cf_control(c, e)
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#define cpu_domains(d) cpufuncs.cf_domains(d)
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#define cpu_setttb(t) cpufuncs.cf_setttb(t)
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#define cpu_faultstatus() cpufuncs.cf_faultstatus()
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#define cpu_faultaddress() cpufuncs.cf_faultaddress()
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#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
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#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
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@ -214,12 +206,11 @@ int set_cpufuncs (void);
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#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
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void cpufunc_nullop (void);
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u_int cpufunc_id (void);
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u_int cpufunc_cpuid (void);
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u_int cpu_ident (void);
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u_int cpufunc_control (u_int clear, u_int bic);
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void cpufunc_domains (u_int domains);
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u_int cpufunc_faultstatus (void);
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u_int cpufunc_faultaddress (void);
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void cpu_domains (u_int domains);
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u_int cpu_faultstatus (void);
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u_int cpu_faultaddress (void);
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u_int cpu_pfr (int);
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#if defined(CPU_FA526)
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