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Add CCM functions to enable HDMI framer and IPU units (video controller)
Reviewed by: andrew, ian Differential Revision: https://reviews.freebsd.org/D4168
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3c62527d03
commit
c0f3a6c2bb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=292565
@ -348,6 +348,43 @@ imx_ccm_ahb_hz(void)
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return (132000000);
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}
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void
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imx_ccm_ipu_enable(int ipu)
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{
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struct ccm_softc *sc;
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uint32_t reg;
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sc = ccm_sc;
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reg = RD4(sc, CCM_CCGR3);
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if (ipu == 1)
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reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0;
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else
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reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0;
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WR4(sc, CCM_CCGR3, reg);
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}
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void
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imx_ccm_hdmi_enable(void)
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{
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struct ccm_softc *sc;
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uint32_t reg;
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sc = ccm_sc;
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reg = RD4(sc, CCM_CCGR2);
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reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR;
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WR4(sc, CCM_CCGR2, reg);
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/* Set HDMI clock to 280MHz */
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reg = RD4(sc, CCM_CHSCCDR);
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reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
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CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT);
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reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT);
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WR4(sc, CCM_CHSCCDR, reg);
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reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT);
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WR4(sc, CCM_CHSCCDR, reg);
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}
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uint32_t
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imx_ccm_get_cacrr(void)
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{
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@ -30,6 +30,9 @@
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#define IMX6_CCMREG_H
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#define CCM_CACCR 0x010
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#define CCM_CBCDR 0x014
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#define CBCDR_MMDC_CH1_AXI_PODF_SHIFT 3
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#define CBCDR_MMDC_CH1_AXI_PODF_MASK (7 << 3)
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#define CCM_CSCMR1 0x01C
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#define SSI1_CLK_SEL_S 10
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#define SSI2_CLK_SEL_S 12
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@ -39,6 +42,7 @@
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#define SSI_CLK_SEL_454_PFD 1
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#define SSI_CLK_SEL_PLL4 2
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#define CCM_CSCMR2 0x020
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#define CSCMR2_LDB_DI0_IPU_DIV_SHIFT 10
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#define CCM_CS1CDR 0x028
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#define SSI1_CLK_PODF_SHIFT 0
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#define SSI1_CLK_PRED_SHIFT 6
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@ -49,6 +53,18 @@
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#define CCM_CS2CDR 0x02C
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#define SSI2_CLK_PODF_SHIFT 0
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#define SSI2_CLK_PRED_SHIFT 6
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#define LDB_DI0_CLK_SEL_SHIFT 9
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#define LDB_DI0_CLK_SEL_MASK (3 << LDB_DI0_CLK_SEL_SHIFT)
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#define CCM_CHSCCDR 0x034
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#define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
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#define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT 6
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#define CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
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#define CHSCCDR_IPU1_DI0_PODF_SHIFT 3
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#define CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
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#define CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT 0
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#define CHSCCDR_CLK_SEL_LDB_DI0 3
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#define CHSCCDR_PODF_DIVIDE_BY_3 2
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#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
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#define CCM_CSCDR2 0x038
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#define CCM_CLPCR 0x054
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#define CCM_CLPCR_LPM_MASK 0x03
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@ -52,6 +52,8 @@ uint32_t imx_ccm_ahb_hz(void);
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void imx_ccm_usb_enable(device_t _usbdev);
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void imx_ccm_usbphy_enable(device_t _phydev);
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void imx_ccm_ssi_configure(device_t _ssidev);
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void imx_ccm_hdmi_enable(void);
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void imx_ccm_ipu_enable(int ipu);
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/* Routines to get and set the arm clock root divisor register. */
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uint32_t imx_ccm_get_cacrr(void);
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