mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-15 10:17:20 +00:00
Restructure the MSR handling so it is entirely handled by processor-specific
code. There are only a handful of MSRs common between the two so there isn't too much duplicate functionality. The VT-x code has the following types of MSRs: - MSRs that are unconditionally saved/restored on every guest/host context switch (e.g., MSR_GSBASE). - MSRs that are restored to guest values on entry to vmx_run() and saved before returning. This is an optimization for MSRs that are not used in host kernel context (e.g., MSR_KGSBASE). - MSRs that are emulated and every access by the guest causes a trap into the hypervisor (e.g., MSR_IA32_MISC_ENABLE). Reviewed by: grehan
This commit is contained in:
Neel Natu
parent
17bb5fd106
commit
c3498942a5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=271888
@ -195,7 +195,6 @@ void vm_nmi_clear(struct vm *vm, int vcpuid);
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int vm_inject_extint(struct vm *vm, int vcpu);
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int vm_extint_pending(struct vm *vm, int vcpuid);
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void vm_extint_clear(struct vm *vm, int vcpuid);
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uint64_t *vm_guest_msrs(struct vm *vm, int cpu);
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struct vlapic *vm_lapic(struct vm *vm, int cpu);
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struct vioapic *vm_ioapic(struct vm *vm);
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struct vhpet *vm_hpet(struct vm *vm);
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@ -44,7 +44,6 @@ __FBSDID("$FreeBSD$");
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#include "vmx_cpufunc.h"
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#include "vmm_ipi.h"
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#include "vmx_msr.h"
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#include "ept.h"
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#define EPT_SUPPORTS_EXEC_ONLY(cap) ((cap) & (1UL << 0))
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@ -54,6 +54,10 @@ int vmcs_getdesc(struct vmcs *vmcs, int running, int ident,
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int vmcs_setdesc(struct vmcs *vmcs, int running, int ident,
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struct seg_desc *desc);
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/*
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* Avoid header pollution caused by inline use of 'vtophys()' in vmx_cpufunc.h
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*/
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#ifdef _VMX_CPUFUNC_H_
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static __inline uint64_t
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vmcs_read(uint32_t encoding)
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{
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@ -73,6 +77,7 @@ vmcs_write(uint32_t encoding, uint64_t val)
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error = vmwrite(encoding, val);
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KASSERT(error == 0, ("vmcs_write(%u) error %d", encoding, error));
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}
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#endif /* _VMX_CPUFUNC_H_ */
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#define vmexit_instruction_length() vmcs_read(VMCS_EXIT_INSTRUCTION_LENGTH)
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#define vmcs_guest_rip() vmcs_read(VMCS_GUEST_RIP)
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@ -52,20 +52,20 @@ __FBSDID("$FreeBSD$");
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#include <machine/vmm.h>
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#include <machine/vmm_dev.h>
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#include <machine/vmm_instruction_emul.h>
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#include "vmm_lapic.h"
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#include "vmm_host.h"
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#include "vmm_ioport.h"
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#include "vmm_ipi.h"
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#include "vmm_msr.h"
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#include "vmm_ktr.h"
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#include "vmm_stat.h"
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#include "vatpic.h"
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#include "vlapic.h"
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#include "vlapic_priv.h"
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#include "vmx_msr.h"
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#include "ept.h"
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#include "vmx_cpufunc.h"
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#include "vmx.h"
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#include "vmx_msr.h"
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#include "x86.h"
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#include "vmx_controls.h"
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@ -116,12 +116,6 @@ __FBSDID("$FreeBSD$");
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VM_ENTRY_INTO_SMM | \
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VM_ENTRY_DEACTIVATE_DUAL_MONITOR)
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#define guest_msr_rw(vmx, msr) \
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msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_RW)
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#define guest_msr_ro(vmx, msr) \
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msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_READ)
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#define HANDLED 1
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#define UNHANDLED 0
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@ -208,6 +202,7 @@ SYSCTL_UINT(_hw_vmm_vmx, OID_AUTO, vpid_alloc_failed, CTLFLAG_RD,
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static int vmx_getdesc(void *arg, int vcpu, int reg, struct seg_desc *desc);
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static int vmx_getreg(void *arg, int vcpu, int reg, uint64_t *retval);
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static int vmxctx_setreg(struct vmxctx *vmxctx, int reg, uint64_t val);
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static void vmx_inject_pir(struct vlapic *vlapic);
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#ifdef KTR
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@ -474,22 +469,6 @@ vpid_init(void)
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vpid_unr = new_unrhdr(VM_MAXCPU + 1, 0xffff, NULL);
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}
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static void
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msr_save_area_init(struct msr_entry *g_area, int *g_count)
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{
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int cnt;
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static struct msr_entry guest_msrs[] = {
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{ MSR_KGSBASE, 0, 0 },
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};
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cnt = sizeof(guest_msrs) / sizeof(guest_msrs[0]);
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if (cnt > GUEST_MSR_MAX_ENTRIES)
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panic("guest msr save area overrun");
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bcopy(guest_msrs, g_area, sizeof(guest_msrs));
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*g_count = cnt;
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}
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static void
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vmx_disable(void *arg __unused)
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{
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@ -655,7 +634,6 @@ vmx_init(int ipinum)
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} else {
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if (bootverbose)
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printf("vmm: PAT MSR access not supported\n");
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guest_msr_valid(MSR_PAT);
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vmx_patmsr = 0;
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}
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}
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@ -800,6 +778,8 @@ vmx_init(int ipinum)
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vpid_init();
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vmx_msr_init();
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/* enable VMX operation */
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smp_rendezvous(NULL, vmx_enable, NULL, NULL);
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@ -869,7 +849,7 @@ static void *
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vmx_vminit(struct vm *vm, pmap_t pmap)
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{
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uint16_t vpid[VM_MAXCPU];
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int i, error, guest_msr_count;
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int i, error;
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struct vmx *vmx;
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struct vmcs *vmcs;
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@ -958,6 +938,8 @@ vmx_vminit(struct vm *vm, pmap_t pmap)
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error, i);
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}
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vmx_msr_guest_init(vmx, i);
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error = vmcs_init(vmcs);
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KASSERT(error == 0, ("vmcs_init error %d", error));
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@ -996,13 +978,6 @@ vmx_vminit(struct vm *vm, pmap_t pmap)
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vmx->state[i].lastcpu = NOCPU;
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vmx->state[i].vpid = vpid[i];
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msr_save_area_init(vmx->guest_msrs[i], &guest_msr_count);
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error = vmcs_set_msr_save(vmcs, vtophys(vmx->guest_msrs[i]),
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guest_msr_count);
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if (error != 0)
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panic("vmcs_set_msr_save error %d", error);
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/*
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* Set up the CR0/4 shadows, and init the read shadow
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* to the power-on register value from the Intel Sys Arch.
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@ -2077,6 +2052,46 @@ vmx_task_switch_reason(uint64_t qual)
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}
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}
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static int
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emulate_wrmsr(struct vmx *vmx, int vcpuid, u_int num, uint64_t val, bool *retu)
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{
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int error;
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if (lapic_msr(num))
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error = lapic_wrmsr(vmx->vm, vcpuid, num, val, retu);
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else
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error = vmx_wrmsr(vmx, vcpuid, num, val, retu);
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return (error);
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}
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static int
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emulate_rdmsr(struct vmx *vmx, int vcpuid, u_int num, bool *retu)
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{
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struct vmxctx *vmxctx;
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uint64_t result;
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uint32_t eax, edx;
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int error;
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if (lapic_msr(num))
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error = lapic_rdmsr(vmx->vm, vcpuid, num, &result, retu);
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else
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error = vmx_rdmsr(vmx, vcpuid, num, &result, retu);
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if (error == 0) {
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eax = result;
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vmxctx = &vmx->ctx[vcpuid];
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error = vmxctx_setreg(vmxctx, VM_REG_GUEST_RAX, eax);
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KASSERT(error == 0, ("vmxctx_setreg(rax) error %d", error));
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edx = result >> 32;
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error = vmxctx_setreg(vmxctx, VM_REG_GUEST_RDX, edx);
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KASSERT(error == 0, ("vmxctx_setreg(rdx) error %d", error));
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}
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return (error);
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}
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static int
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vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
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{
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@ -2215,7 +2230,7 @@ vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
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retu = false;
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ecx = vmxctx->guest_rcx;
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VCPU_CTR1(vmx->vm, vcpu, "rdmsr 0x%08x", ecx);
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error = emulate_rdmsr(vmx->vm, vcpu, ecx, &retu);
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error = emulate_rdmsr(vmx, vcpu, ecx, &retu);
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if (error) {
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vmexit->exitcode = VM_EXITCODE_RDMSR;
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vmexit->u.msr.code = ecx;
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@ -2224,7 +2239,7 @@ vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
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} else {
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/* Return to userspace with a valid exitcode */
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KASSERT(vmexit->exitcode != VM_EXITCODE_BOGUS,
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("emulate_wrmsr retu with bogus exitcode"));
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("emulate_rdmsr retu with bogus exitcode"));
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}
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break;
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case EXIT_REASON_WRMSR:
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@ -2235,7 +2250,7 @@ vmx_exit_process(struct vmx *vmx, int vcpu, struct vm_exit *vmexit)
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edx = vmxctx->guest_rdx;
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VCPU_CTR2(vmx->vm, vcpu, "wrmsr 0x%08x value 0x%016lx",
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ecx, (uint64_t)edx << 32 | eax);
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error = emulate_wrmsr(vmx->vm, vcpu, ecx,
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error = emulate_wrmsr(vmx, vcpu, ecx,
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(uint64_t)edx << 32 | eax, &retu);
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if (error) {
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vmexit->exitcode = VM_EXITCODE_WRMSR;
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@ -2523,6 +2538,8 @@ vmx_run(void *arg, int vcpu, register_t startrip, pmap_t pmap,
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KASSERT(vmxctx->pmap == pmap,
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("pmap %p different than ctx pmap %p", pmap, vmxctx->pmap));
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vmx_msr_guest_enter(vmx, vcpu);
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VMPTRLD(vmcs);
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/*
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@ -2624,6 +2641,8 @@ vmx_run(void *arg, int vcpu, register_t startrip, pmap_t pmap,
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vmexit->exitcode);
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VMCLEAR(vmcs);
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vmx_msr_guest_exit(vmx, vcpu);
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return (0);
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}
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@ -33,8 +33,6 @@
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struct pmap;
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#define GUEST_MSR_MAX_ENTRIES 64 /* arbitrary */
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struct vmxctx {
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register_t guest_rdi; /* Guest state */
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register_t guest_rsi;
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@ -97,13 +95,23 @@ struct pir_desc {
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} __aligned(64);
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CTASSERT(sizeof(struct pir_desc) == 64);
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/* Index into the 'guest_msrs[]' array */
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enum {
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IDX_MSR_LSTAR,
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IDX_MSR_CSTAR,
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IDX_MSR_STAR,
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IDX_MSR_SF_MASK,
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IDX_MSR_KGSBASE,
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GUEST_MSR_NUM /* must be the last enumeration */
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};
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/* virtual machine softc */
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struct vmx {
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struct vmcs vmcs[VM_MAXCPU]; /* one vmcs per virtual cpu */
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struct apic_page apic_page[VM_MAXCPU]; /* one apic page per vcpu */
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char msr_bitmap[PAGE_SIZE];
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struct pir_desc pir_desc[VM_MAXCPU];
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struct msr_entry guest_msrs[VM_MAXCPU][GUEST_MSR_MAX_ENTRIES];
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uint64_t guest_msrs[VM_MAXCPU][GUEST_MSR_NUM];
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struct vmxctx ctx[VM_MAXCPU];
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struct vmxcap cap[VM_MAXCPU];
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struct vmxstate state[VM_MAXCPU];
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@ -113,7 +121,6 @@ struct vmx {
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};
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CTASSERT((offsetof(struct vmx, vmcs) & PAGE_MASK) == 0);
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CTASSERT((offsetof(struct vmx, msr_bitmap) & PAGE_MASK) == 0);
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CTASSERT((offsetof(struct vmx, guest_msrs) & 15) == 0);
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CTASSERT((offsetof(struct vmx, pir_desc[0]) & 63) == 0);
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#define VMX_GUEST_VMEXIT 0
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@ -31,10 +31,13 @@ __FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/cpuset.h>
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#include <machine/cpufunc.h>
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#include <machine/specialreg.h>
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#include <machine/vmm.h>
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#include "vmx.h"
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#include "vmx_msr.h"
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static boolean_t
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@ -171,3 +174,115 @@ msr_bitmap_change_access(char *bitmap, u_int msr, int access)
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return (0);
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}
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static uint64_t misc_enable;
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static uint64_t host_msrs[GUEST_MSR_NUM];
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void
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vmx_msr_init(void)
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{
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/*
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* It is safe to cache the values of the following MSRs because
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* they don't change based on curcpu, curproc or curthread.
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*/
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host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
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host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
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host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
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host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
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/*
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* Initialize emulated MSRs
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*/
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misc_enable = rdmsr(MSR_IA32_MISC_ENABLE);
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/*
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* Set mandatory bits
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* 11: branch trace disabled
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* 12: PEBS unavailable
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* Clear unsupported features
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* 16: SpeedStep enable
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* 18: enable MONITOR FSM
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*/
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misc_enable |= (1 << 12) | (1 << 11);
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misc_enable &= ~((1 << 18) | (1 << 16));
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}
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void
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vmx_msr_guest_init(struct vmx *vmx, int vcpuid)
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{
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/*
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* The permissions bitmap is shared between all vcpus so initialize it
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* once when initializing the vBSP.
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*/
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if (vcpuid == 0) {
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guest_msr_rw(vmx, MSR_LSTAR);
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guest_msr_rw(vmx, MSR_CSTAR);
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guest_msr_rw(vmx, MSR_STAR);
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guest_msr_rw(vmx, MSR_SF_MASK);
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guest_msr_rw(vmx, MSR_KGSBASE);
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}
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return;
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}
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void
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vmx_msr_guest_enter(struct vmx *vmx, int vcpuid)
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{
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uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];
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/* Save host MSRs (if any) and restore guest MSRs */
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wrmsr(MSR_LSTAR, guest_msrs[IDX_MSR_LSTAR]);
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wrmsr(MSR_CSTAR, guest_msrs[IDX_MSR_CSTAR]);
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wrmsr(MSR_STAR, guest_msrs[IDX_MSR_STAR]);
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wrmsr(MSR_SF_MASK, guest_msrs[IDX_MSR_SF_MASK]);
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wrmsr(MSR_KGSBASE, guest_msrs[IDX_MSR_KGSBASE]);
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}
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void
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vmx_msr_guest_exit(struct vmx *vmx, int vcpuid)
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{
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uint64_t *guest_msrs = vmx->guest_msrs[vcpuid];
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/* Save guest MSRs */
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guest_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR);
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guest_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR);
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guest_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR);
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guest_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK);
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guest_msrs[IDX_MSR_KGSBASE] = rdmsr(MSR_KGSBASE);
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/* Restore host MSRs */
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wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]);
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wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]);
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wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]);
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wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]);
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/* MSR_KGSBASE will be restored on the way back to userspace */
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}
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int
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vmx_rdmsr(struct vmx *vmx, int vcpuid, u_int num, uint64_t *val, bool *retu)
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{
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int error = 0;
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switch (num) {
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case MSR_IA32_MISC_ENABLE:
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*val = misc_enable;
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break;
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default:
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error = EINVAL;
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break;
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}
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return (error);
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}
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int
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vmx_wrmsr(struct vmx *vmx, int vcpuid, u_int num, uint64_t val, bool *retu)
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{
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int error = 0;
|
||||
|
||||
switch (num) {
|
||||
default:
|
||||
error = EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
||||
@ -29,6 +29,15 @@
|
||||
#ifndef _VMX_MSR_H_
|
||||
#define _VMX_MSR_H_
|
||||
|
||||
struct vmx;
|
||||
|
||||
void vmx_msr_init(void);
|
||||
void vmx_msr_guest_init(struct vmx *vmx, int vcpuid);
|
||||
void vmx_msr_guest_enter(struct vmx *vmx, int vcpuid);
|
||||
void vmx_msr_guest_exit(struct vmx *vmx, int vcpuid);
|
||||
int vmx_rdmsr(struct vmx *, int vcpuid, u_int num, uint64_t *val, bool *retu);
|
||||
int vmx_wrmsr(struct vmx *, int vcpuid, u_int num, uint64_t val, bool *retu);
|
||||
|
||||
uint32_t vmx_revision(void);
|
||||
|
||||
int vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,
|
||||
@ -52,4 +61,10 @@ int vmx_set_ctlreg(int ctl_reg, int true_ctl_reg, uint32_t ones_mask,
|
||||
void msr_bitmap_initialize(char *bitmap);
|
||||
int msr_bitmap_change_access(char *bitmap, u_int msr, int access);
|
||||
|
||||
#define guest_msr_rw(vmx, msr) \
|
||||
msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_RW)
|
||||
|
||||
#define guest_msr_ro(vmx, msr) \
|
||||
msr_bitmap_change_access((vmx)->msr_bitmap, (msr), MSR_BITMAP_ACCESS_READ)
|
||||
|
||||
#endif
|
||||
|
||||
@ -74,7 +74,6 @@ __FBSDID("$FreeBSD$");
|
||||
#include "vhpet.h"
|
||||
#include "vioapic.h"
|
||||
#include "vlapic.h"
|
||||
#include "vmm_msr.h"
|
||||
#include "vmm_ipi.h"
|
||||
#include "vmm_stat.h"
|
||||
#include "vmm_lapic.h"
|
||||
@ -105,7 +104,6 @@ struct vcpu {
|
||||
struct savefpu *guestfpu; /* (a,i) guest fpu state */
|
||||
uint64_t guest_xcr0; /* (i) guest %xcr0 register */
|
||||
void *stats; /* (a,i) statistics */
|
||||
uint64_t guest_msrs[VMM_MSR_NUM]; /* (i) emulated MSRs */
|
||||
struct vm_exit exitinfo; /* (x) exit reason and collateral */
|
||||
};
|
||||
|
||||
@ -188,7 +186,6 @@ static struct vmm_ops *ops;
|
||||
#define fpu_stop_emulating() clts()
|
||||
|
||||
static MALLOC_DEFINE(M_VM, "vm", "vm");
|
||||
CTASSERT(VMM_MSR_NUM <= 64); /* msr_mask can keep track of up to 64 msrs */
|
||||
|
||||
/* statistics */
|
||||
static VMM_STAT(VCPU_TOTAL_RUNTIME, "vcpu total runtime");
|
||||
@ -249,7 +246,6 @@ vcpu_init(struct vm *vm, int vcpu_id, bool create)
|
||||
vcpu->guest_xcr0 = XFEATURE_ENABLED_X87;
|
||||
fpu_save_area_reset(vcpu->guestfpu);
|
||||
vmm_stat_init(vcpu->stats);
|
||||
guest_msrs_init(vm, vcpu_id);
|
||||
}
|
||||
|
||||
struct vm_exit *
|
||||
@ -293,7 +289,6 @@ vmm_init(void)
|
||||
else
|
||||
return (ENXIO);
|
||||
|
||||
vmm_msr_init();
|
||||
vmm_resume_p = vmm_resume;
|
||||
|
||||
return (VMM_INIT(vmm_ipinum));
|
||||
@ -1440,7 +1435,6 @@ vm_run(struct vm *vm, struct vm_run *vmrun)
|
||||
pcb = PCPU_GET(curpcb);
|
||||
set_pcb_flags(pcb, PCB_FULL_IRET);
|
||||
|
||||
restore_guest_msrs(vm, vcpuid);
|
||||
restore_guest_fpustate(vcpu);
|
||||
|
||||
vcpu_require_state(vm, vcpuid, VCPU_RUNNING);
|
||||
@ -1448,7 +1442,6 @@ vm_run(struct vm *vm, struct vm_run *vmrun)
|
||||
vcpu_require_state(vm, vcpuid, VCPU_FROZEN);
|
||||
|
||||
save_guest_fpustate(vcpu);
|
||||
restore_host_msrs(vm, vcpuid);
|
||||
|
||||
vmm_stat_incr(vm, vcpuid, VCPU_TOTAL_RUNTIME, rdtsc() - tscval);
|
||||
|
||||
@ -1890,12 +1883,6 @@ vm_set_capability(struct vm *vm, int vcpu, int type, int val)
|
||||
return (VMSETCAP(vm->cookie, vcpu, type, val));
|
||||
}
|
||||
|
||||
uint64_t *
|
||||
vm_guest_msrs(struct vm *vm, int cpu)
|
||||
{
|
||||
return (vm->vcpu[cpu].guest_msrs);
|
||||
}
|
||||
|
||||
struct vlapic *
|
||||
vm_lapic(struct vm *vm, int cpu)
|
||||
{
|
||||
|
||||
@ -1,273 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 NetApp, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#include <sys/cdefs.h>
|
||||
__FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/smp.h>
|
||||
|
||||
#include <machine/specialreg.h>
|
||||
|
||||
#include <machine/vmm.h>
|
||||
#include "vmm_lapic.h"
|
||||
#include "vmm_msr.h"
|
||||
|
||||
#define VMM_MSR_F_EMULATE 0x01
|
||||
#define VMM_MSR_F_READONLY 0x02
|
||||
#define VMM_MSR_F_INVALID 0x04 /* guest_msr_valid() can override this */
|
||||
|
||||
struct vmm_msr {
|
||||
int num;
|
||||
int flags;
|
||||
uint64_t hostval;
|
||||
};
|
||||
|
||||
static struct vmm_msr vmm_msr[] = {
|
||||
{ MSR_LSTAR, 0 },
|
||||
{ MSR_CSTAR, 0 },
|
||||
{ MSR_STAR, 0 },
|
||||
{ MSR_SF_MASK, 0 },
|
||||
{ MSR_PAT, VMM_MSR_F_EMULATE | VMM_MSR_F_INVALID },
|
||||
{ MSR_BIOS_SIGN,VMM_MSR_F_EMULATE },
|
||||
{ MSR_MCG_CAP, VMM_MSR_F_EMULATE | VMM_MSR_F_READONLY },
|
||||
{ MSR_IA32_PLATFORM_ID, VMM_MSR_F_EMULATE | VMM_MSR_F_READONLY },
|
||||
{ MSR_IA32_MISC_ENABLE, VMM_MSR_F_EMULATE | VMM_MSR_F_READONLY },
|
||||
};
|
||||
|
||||
#define vmm_msr_num (sizeof(vmm_msr) / sizeof(vmm_msr[0]))
|
||||
CTASSERT(VMM_MSR_NUM >= vmm_msr_num);
|
||||
|
||||
#define readonly_msr(idx) \
|
||||
((vmm_msr[(idx)].flags & VMM_MSR_F_READONLY) != 0)
|
||||
|
||||
#define emulated_msr(idx) \
|
||||
((vmm_msr[(idx)].flags & VMM_MSR_F_EMULATE) != 0)
|
||||
|
||||
#define invalid_msr(idx) \
|
||||
((vmm_msr[(idx)].flags & VMM_MSR_F_INVALID) != 0)
|
||||
|
||||
void
|
||||
vmm_msr_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < vmm_msr_num; i++) {
|
||||
if (emulated_msr(i))
|
||||
continue;
|
||||
/*
|
||||
* XXX this assumes that the value of the host msr does not
|
||||
* change after we have cached it.
|
||||
*/
|
||||
vmm_msr[i].hostval = rdmsr(vmm_msr[i].num);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
guest_msrs_init(struct vm *vm, int cpu)
|
||||
{
|
||||
int i;
|
||||
uint64_t *guest_msrs, misc;
|
||||
|
||||
guest_msrs = vm_guest_msrs(vm, cpu);
|
||||
|
||||
for (i = 0; i < vmm_msr_num; i++) {
|
||||
switch (vmm_msr[i].num) {
|
||||
case MSR_LSTAR:
|
||||
case MSR_CSTAR:
|
||||
case MSR_STAR:
|
||||
case MSR_SF_MASK:
|
||||
case MSR_BIOS_SIGN:
|
||||
case MSR_MCG_CAP:
|
||||
guest_msrs[i] = 0;
|
||||
break;
|
||||
case MSR_PAT:
|
||||
guest_msrs[i] = PAT_VALUE(0, PAT_WRITE_BACK) |
|
||||
PAT_VALUE(1, PAT_WRITE_THROUGH) |
|
||||
PAT_VALUE(2, PAT_UNCACHED) |
|
||||
PAT_VALUE(3, PAT_UNCACHEABLE) |
|
||||
PAT_VALUE(4, PAT_WRITE_BACK) |
|
||||
PAT_VALUE(5, PAT_WRITE_THROUGH) |
|
||||
PAT_VALUE(6, PAT_UNCACHED) |
|
||||
PAT_VALUE(7, PAT_UNCACHEABLE);
|
||||
break;
|
||||
case MSR_IA32_MISC_ENABLE:
|
||||
misc = rdmsr(MSR_IA32_MISC_ENABLE);
|
||||
/*
|
||||
* Set mandatory bits
|
||||
* 11: branch trace disabled
|
||||
* 12: PEBS unavailable
|
||||
* Clear unsupported features
|
||||
* 16: SpeedStep enable
|
||||
* 18: enable MONITOR FSM
|
||||
*/
|
||||
misc |= (1 << 12) | (1 << 11);
|
||||
misc &= ~((1 << 18) | (1 << 16));
|
||||
guest_msrs[i] = misc;
|
||||
break;
|
||||
case MSR_IA32_PLATFORM_ID:
|
||||
guest_msrs[i] = 0;
|
||||
break;
|
||||
default:
|
||||
panic("guest_msrs_init: missing initialization for msr "
|
||||
"0x%0x", vmm_msr[i].num);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
msr_num_to_idx(u_int num)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < vmm_msr_num; i++)
|
||||
if (vmm_msr[i].num == num)
|
||||
return (i);
|
||||
|
||||
return (-1);
|
||||
}
|
||||
|
||||
int
|
||||
emulate_wrmsr(struct vm *vm, int cpu, u_int num, uint64_t val, bool *retu)
|
||||
{
|
||||
int idx;
|
||||
uint64_t *guest_msrs;
|
||||
|
||||
if (lapic_msr(num))
|
||||
return (lapic_wrmsr(vm, cpu, num, val, retu));
|
||||
|
||||
idx = msr_num_to_idx(num);
|
||||
if (idx < 0 || invalid_msr(idx))
|
||||
return (EINVAL);
|
||||
|
||||
if (!readonly_msr(idx)) {
|
||||
guest_msrs = vm_guest_msrs(vm, cpu);
|
||||
|
||||
/* Stash the value */
|
||||
guest_msrs[idx] = val;
|
||||
|
||||
/* Update processor state for non-emulated MSRs */
|
||||
if (!emulated_msr(idx))
|
||||
wrmsr(vmm_msr[idx].num, val);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int
|
||||
emulate_rdmsr(struct vm *vm, int cpu, u_int num, bool *retu)
|
||||
{
|
||||
int error, idx;
|
||||
uint32_t eax, edx;
|
||||
uint64_t result, *guest_msrs;
|
||||
|
||||
if (lapic_msr(num)) {
|
||||
error = lapic_rdmsr(vm, cpu, num, &result, retu);
|
||||
goto done;
|
||||
}
|
||||
|
||||
idx = msr_num_to_idx(num);
|
||||
if (idx < 0 || invalid_msr(idx)) {
|
||||
error = EINVAL;
|
||||
goto done;
|
||||
}
|
||||
|
||||
guest_msrs = vm_guest_msrs(vm, cpu);
|
||||
result = guest_msrs[idx];
|
||||
|
||||
/*
|
||||
* If this is not an emulated msr register make sure that the processor
|
||||
* state matches our cached state.
|
||||
*/
|
||||
if (!emulated_msr(idx) && (rdmsr(num) != result)) {
|
||||
panic("emulate_rdmsr: msr 0x%0x has inconsistent cached "
|
||||
"(0x%016lx) and actual (0x%016lx) values", num,
|
||||
result, rdmsr(num));
|
||||
}
|
||||
|
||||
error = 0;
|
||||
|
||||
done:
|
||||
if (error == 0) {
|
||||
eax = result;
|
||||
edx = result >> 32;
|
||||
error = vm_set_register(vm, cpu, VM_REG_GUEST_RAX, eax);
|
||||
if (error)
|
||||
panic("vm_set_register(rax) error %d", error);
|
||||
error = vm_set_register(vm, cpu, VM_REG_GUEST_RDX, edx);
|
||||
if (error)
|
||||
panic("vm_set_register(rdx) error %d", error);
|
||||
}
|
||||
return (error);
|
||||
}
|
||||
|
||||
void
|
||||
restore_guest_msrs(struct vm *vm, int cpu)
|
||||
{
|
||||
int i;
|
||||
uint64_t *guest_msrs;
|
||||
|
||||
guest_msrs = vm_guest_msrs(vm, cpu);
|
||||
|
||||
for (i = 0; i < vmm_msr_num; i++) {
|
||||
if (emulated_msr(i))
|
||||
continue;
|
||||
else
|
||||
wrmsr(vmm_msr[i].num, guest_msrs[i]);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
restore_host_msrs(struct vm *vm, int cpu)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < vmm_msr_num; i++) {
|
||||
if (emulated_msr(i))
|
||||
continue;
|
||||
else
|
||||
wrmsr(vmm_msr[i].num, vmm_msr[i].hostval);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Must be called by the CPU-specific code before any guests are
|
||||
* created
|
||||
*/
|
||||
void
|
||||
guest_msr_valid(int msr)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < vmm_msr_num; i++) {
|
||||
if (vmm_msr[i].num == msr && invalid_msr(i)) {
|
||||
vmm_msr[i].flags &= ~VMM_MSR_F_INVALID;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1,44 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2011 NetApp, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _VMM_MSR_H_
|
||||
#define _VMM_MSR_H_
|
||||
|
||||
#define VMM_MSR_NUM 16
|
||||
struct vm;
|
||||
|
||||
void vmm_msr_init(void);
|
||||
int emulate_wrmsr(struct vm *vm, int vcpu, u_int msr, uint64_t val,
|
||||
bool *retu);
|
||||
int emulate_rdmsr(struct vm *vm, int vcpu, u_int msr, bool *retu);
|
||||
void guest_msrs_init(struct vm *vm, int cpu);
|
||||
void guest_msr_valid(int msr);
|
||||
void restore_host_msrs(struct vm *vm, int cpu);
|
||||
void restore_guest_msrs(struct vm *vm, int cpu);
|
||||
|
||||
#endif
|
||||
@ -19,7 +19,6 @@ SRCS+= vmm.c \
|
||||
vmm_ipi.c \
|
||||
vmm_lapic.c \
|
||||
vmm_mem.c \
|
||||
vmm_msr.c \
|
||||
vmm_stat.c \
|
||||
vmm_util.c \
|
||||
x86.c \
|
||||
|
||||
@ -437,6 +437,10 @@
|
||||
#define MSR_MC4_STATUS 0x411
|
||||
#define MSR_MC4_ADDR 0x412
|
||||
#define MSR_MC4_MISC 0x413
|
||||
#define MSR_PKG_ENERGY_STATUS 0x611
|
||||
#define MSR_DRAM_ENERGY_STATUS 0x619
|
||||
#define MSR_PP0_ENERGY_STATUS 0x639
|
||||
#define MSR_PP1_ENERGY_STATUS 0x641
|
||||
|
||||
/*
|
||||
* VMX MSRs
|
||||
|
||||
@ -803,6 +803,12 @@ main(int argc, char *argv[])
|
||||
exit(1);
|
||||
}
|
||||
|
||||
error = init_msr();
|
||||
if (error) {
|
||||
fprintf(stderr, "init_msr error %d", error);
|
||||
exit(1);
|
||||
}
|
||||
|
||||
init_mem();
|
||||
init_inout();
|
||||
pci_irq_init(ctx);
|
||||
|
||||
@ -31,33 +31,84 @@ __FBSDID("$FreeBSD$");
|
||||
|
||||
#include <sys/types.h>
|
||||
|
||||
#include <machine/cpufunc.h>
|
||||
#include <machine/vmm.h>
|
||||
#include <machine/specialreg.h>
|
||||
|
||||
#include <vmmapi.h>
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "xmsr.h"
|
||||
|
||||
static int cpu_vendor_intel, cpu_vendor_amd;
|
||||
|
||||
int
|
||||
emulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t code, uint64_t val)
|
||||
{
|
||||
|
||||
switch (code) {
|
||||
case 0xd04: /* Sandy Bridge uncore PMC MSRs */
|
||||
case 0xc24:
|
||||
return (0);
|
||||
case 0x79:
|
||||
return (0); /* IA32_BIOS_UPDT_TRIG MSR */
|
||||
default:
|
||||
break;
|
||||
if (cpu_vendor_intel) {
|
||||
switch (code) {
|
||||
case 0xd04: /* Sandy Bridge uncore PMCs */
|
||||
case 0xc24:
|
||||
return (0);
|
||||
case MSR_BIOS_UPDT_TRIG:
|
||||
return (0);
|
||||
case MSR_BIOS_SIGN:
|
||||
return (0);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
return (-1);
|
||||
}
|
||||
|
||||
int
|
||||
emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t code, uint64_t *val)
|
||||
emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t num, uint64_t *val)
|
||||
{
|
||||
int error = 0;
|
||||
|
||||
return (-1);
|
||||
if (cpu_vendor_intel) {
|
||||
switch (num) {
|
||||
case MSR_BIOS_SIGN:
|
||||
case MSR_IA32_PLATFORM_ID:
|
||||
case MSR_PKG_ENERGY_STATUS:
|
||||
case MSR_PP0_ENERGY_STATUS:
|
||||
case MSR_PP1_ENERGY_STATUS:
|
||||
case MSR_DRAM_ENERGY_STATUS:
|
||||
*val = 0;
|
||||
break;
|
||||
default:
|
||||
error = -1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
return (error);
|
||||
}
|
||||
|
||||
int
|
||||
init_msr(void)
|
||||
{
|
||||
int error;
|
||||
u_int regs[4];
|
||||
char cpu_vendor[13];
|
||||
|
||||
do_cpuid(0, regs);
|
||||
((u_int *)&cpu_vendor)[0] = regs[1];
|
||||
((u_int *)&cpu_vendor)[1] = regs[3];
|
||||
((u_int *)&cpu_vendor)[2] = regs[2];
|
||||
cpu_vendor[12] = '\0';
|
||||
|
||||
error = 0;
|
||||
if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
|
||||
cpu_vendor_amd = 1;
|
||||
} else if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
|
||||
cpu_vendor_intel = 1;
|
||||
} else {
|
||||
fprintf(stderr, "Unknown cpu vendor \"%s\"\n", cpu_vendor);
|
||||
error = -1;
|
||||
}
|
||||
return (error);
|
||||
}
|
||||
|
||||
@ -29,6 +29,7 @@
|
||||
#ifndef _XMSR_H_
|
||||
#define _XMSR_H_
|
||||
|
||||
int init_msr(void);
|
||||
int emulate_wrmsr(struct vmctx *ctx, int vcpu, uint32_t code, uint64_t val);
|
||||
int emulate_rdmsr(struct vmctx *ctx, int vcpu, uint32_t code, uint64_t *val);
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user