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Code Issues Releases Activity

Remove support for IDT. Only the RouterBoard RB533 used this chip, and

Browse Source 
it's at least 5 years out of production. I couldn't find a used one on
ebay and other secondary markets just now, nor when I tried 4 years
ago. It dates from the initial project/mips2 merge 8 years ago, and
hasn't been updated since.

Discussed on: mips@ (with some dissent)
This commit is contained in:
Warner Losh 2018-01-01 04:10:36 +00:00
parent ada611f6ad
commit c3dbef68d5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=327460
12 changed files with 0 additions and 3606 deletions
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55
sys/mips/conf/IDT
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@ -1,55 +0,0 @@
# $FreeBSD$
cpu CPU_MIPS4KC
ident RB532
# Don't build any modules yet.
makeoptions MODULES_OVERRIDE=""
include "../idt/std.idt"
hints "IDT.hints" #Default places to look for devices.
makeoptions DEBUG=-g #Build kernel with gdb(1) debug symbols
options DDB
options KDB
options SCHED_4BSD #4BSD scheduler
options INET #InterNETworking
options TCP_HHOOK # hhook(9) framework for TCP
options NFSCL #Network Filesystem Client
options NFS_ROOT #NFS usable as /, requires NFSCL
options PSEUDOFS #Pseudo-filesystem framework
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=kr0
options BOOTP_COMPAT
# Debugging for use in -current
#options DEADLKRES #Enable the deadlock resolver
options INVARIANTS #Enable calls of extra sanity checking
options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
device loop
device pci
device ether
device miibus
device vr
device kr
device uart
device md
# Wireless NIC cards
device wlan # 802.11 support
device wlan_wep # 802.11 WEP support
device wlan_tkip # 802.11 TKIP support
device ath # Atheros NIC's
device ath_pci # Atheros pci/cardbus glue
device ath_hal # pci/cardbus chip support
options AH_SUPPORT_AR5416 # enable AR5416 tx/rx descriptors
device ath_rate_sample # SampleRate tx rate control for ath
options ATH_DEBUG
device bpf

10
sys/mips/idt/files.idt
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@ -1,10 +0,0 @@
# $FreeBSD$
mips/idt/idt_machdep.c standard
mips/idt/idtpci.c optional pci
mips/idt/if_kr.c optional kr
mips/idt/obio.c standard
mips/idt/uart_cpu_rc32434.c optional uart
mips/idt/uart_bus_rc32434.c optional uart
mips/mips/intr_machdep.c standard
mips/mips/tick.c standard

180
sys/mips/idt/idt_machdep.c
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@ -1,180 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id: $
*
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/systm.h>
#include <sys/imgact.h>
#include <sys/bio.h>
#include <sys/buf.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/cons.h>
#include <sys/exec.h>
#include <sys/ucontext.h>
#include <sys/proc.h>
#include <sys/kdb.h>
#include <sys/ptrace.h>
#include <sys/reboot.h>
#include <sys/signalvar.h>
#include <sys/sysent.h>
#include <sys/sysproto.h>
#include <sys/user.h>
#include <vm/vm.h>
#include <vm/vm_object.h>
#include <vm/vm_page.h>
#include <machine/cache.h>
#include <machine/clock.h>
#include <machine/cpu.h>
#include <machine/cpuinfo.h>
#include <machine/cpufunc.h>
#include <machine/cpuregs.h>
#include <machine/hwfunc.h>
#include <machine/intr_machdep.h>
#include <machine/locore.h>
#include <machine/md_var.h>
#include <machine/pte.h>
#include <machine/sigframe.h>
#include <machine/trap.h>
#include <machine/vmparam.h>
extern int *edata;
extern int *end;
void
platform_cpu_init()
{
/* Nothing special */
}
void
platform_reset(void)
{
volatile unsigned int * p = (void *)0xb8008000;
/*
* TODO: we should take care of TLB stuff here. Otherwise
* board does not boots properly next time
*/
/* Write 0x8000_0001 to the Reset register */
*p = 0x80000001;
__asm __volatile("li $25, 0xbfc00000");
__asm __volatile("j $25");
}
void
platform_start(__register_t a0, __register_t a1,
__register_t a2 __unused, __register_t a3 __unused)
{
uint64_t platform_counter_freq;
vm_offset_t kernend;
int argc = a0;
char **argv = (char **)a1;
int i, mem;
/* clear the BSS and SBSS segments */
kernend = (vm_offset_t)&end;
memset(&edata, 0, kernend - (vm_offset_t)(&edata));
mips_postboot_fixup();
/* Initialize pcpu stuff */
mips_pcpu0_init();
/*
* Looking for mem=XXM argument
*/
mem = 0; /* Just something to start with */
for (i=0; i < argc; i++) {
if (strncmp(argv[i], "mem=", 4) == 0) {
mem = strtol(argv[i] + 4, NULL, 0);
break;
}
}
bootverbose = 1;
if (mem > 0)
realmem = btoc(mem << 20);
else
realmem = btoc(32 << 20);
for (i = 0; i < 10; i++) {
phys_avail[i] = 0;
}
/* phys_avail regions are in bytes */
phys_avail[0] = MIPS_KSEG0_TO_PHYS(kernel_kseg0_end);
phys_avail[1] = ctob(realmem);
dump_avail[0] = phys_avail[0];
dump_avail[1] = phys_avail[1];
physmem = realmem;
/*
* ns8250 uart code uses DELAY so ticker should be inititalized
* before cninit. And tick_init_params refers to hz, so * init_param1
* should be called first.
*/
init_param1();
/* TODO: parse argc,argv */
platform_counter_freq = 330000000UL;
mips_timer_init_params(platform_counter_freq, 1);
cninit();
/* Panic here, after cninit */
if (mem == 0)
panic("No mem=XX parameter in arguments");
printf("cmd line: ");
for (i=0; i < argc; i++)
printf("%s ", argv[i]);
printf("\n");
init_param2(physmem);
mips_cpu_init();
pmap_bootstrap();
mips_proc0_init();
mutex_init();
kdb_init();
#ifdef KDB
if (boothowto & RB_KDB)
kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
#endif
}

559
sys/mips/idt/idtpci.c
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@ -1,559 +0,0 @@
/* $NetBSD: idtpci.c,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2007 David Young.
* Copyright (c) 2007 Oleskandr Tymoshenko. All rights reserved.
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
* 3. The name of the author may not be used to endorse or promote
* products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
* OF SUCH DAMAGE.
*/
/*-
* Copyright (c) 2006 Itronix Inc.
* All rights reserved.
*
* Written by Garrett D'Amore for Itronix Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of Itronix Inc. may not be used to endorse
* or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/interrupt.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcib_private.h>
#include "pcib_if.h"
#include <mips/idt/idtreg.h>
#ifdef IDTPCI_DEBUG
int idtpci_debug = 1;
#define IDTPCI_DPRINTF(__fmt, ...) \
do { \
if (idtpci_debug) \
printf((__fmt), __VA_ARGS__); \
} while (/*CONSTCOND*/0)
#else /* !IDTPCI_DEBUG */
#define IDTPCI_DPRINTF(__fmt, ...) do { } while (/*CONSTCOND*/0)
#endif /* IDTPCI_DEBUG */
#define IDTPCI_TAG_BUS_MASK 0x007f0000
#define IDTPCI_TAG_DEVICE_MASK 0x00007800
#define IDTPCI_TAG_FUNCTION_MASK 0x00000300
#define IDTPCI_TAG_REGISTER_MASK 0x0000007c
#define IDTPCI_MAX_DEVICE
#define REG_READ(o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_PCI + (o)))
#define REG_WRITE(o,v) (REG_READ(o)) = (v)
unsigned int korina_fixup[24] = {
0x00000157, 0x00000000, 0x00003c04, 0x00000008, 0x18800001, 0x18000001,
0x48000008, 0x00000000, 0x00000000, 0x00000000, 0x011d0214, 0x00000000,
0x00000000, 0x00000000, 0x38080101, 0x00008080, 0x00000d6e, 0x00000000,
0x00000051, 0x00000000, 0x00000055, 0x18000000, 0x00000000, 0x00000000
};
struct idtpci_softc {
device_t sc_dev;
int sc_busno;
struct rman sc_mem_rman[2];
struct rman sc_io_rman[2];
struct rman sc_irq_rman;
};
static uint32_t
idtpci_make_addr(int bus, int slot, int func, int reg)
{
return 0x80000000 | (bus << 16) | (slot << 11) | (func << 8) | reg;
}
static int
idtpci_probe(device_t dev)
{
return (0);
}
static int
idtpci_attach(device_t dev)
{
int busno = 0;
struct idtpci_softc *sc = device_get_softc(dev);
unsigned int pci_data, force_endianess = 0;
int i;
bus_addr_t addr;
sc->sc_dev = dev;
sc->sc_busno = busno;
/* TODO: Check for host mode */
/* Enabled PCI, IG mode, EAP mode */
REG_WRITE(IDT_PCI_CNTL, IDT_PCI_CNTL_IGM | IDT_PCI_CNTL_EAP |
IDT_PCI_CNTL_EN);
/* Wait while "Reset in progress bit" set */
while(1) {
pci_data = REG_READ(IDT_PCI_STATUS);
if((pci_data & IDT_PCI_STATUS_RIP) == 0)
break;
}
/* Reset status register */
REG_WRITE(IDT_PCI_STATUS, 0);
/* Mask interrupts related to status register */
REG_WRITE(IDT_PCI_STATUS_MASK, 0xffffffff);
/* Disable PCI decoupled access */
REG_WRITE(IDT_PCI_DAC, 0);
/* Zero status and mask DA interrupts */
REG_WRITE(IDT_PCI_DAS, 0);
REG_WRITE(IDT_PCI_DASM, 0x7f);
/* Init PCI messaging unit */
/* Disable messaging interrupts */
REG_WRITE(IDT_PCI_IIC, 0);
REG_WRITE(IDT_PCI_IIM, 0xffffffff);
REG_WRITE(IDT_PCI_OIC, 0);
REG_WRITE(IDT_PCI_OIM, 0);
#ifdef __MIPSEB__
force_endianess = IDT_PCI_LBA_FE;
#endif
/* LBA0 -- memory window */
REG_WRITE(IDT_PCI_LBA0, IDT_PCIMEM0_BASE);
REG_WRITE(IDT_PCI_LBA0_MAP, IDT_PCIMEM0_BASE);
REG_WRITE(IDT_PCI_LBA0_CNTL, IDT_PCI_LBA_SIZE_16MB | force_endianess);
pci_data = REG_READ(IDT_PCI_LBA0_CNTL);
/* LBA1 -- memory window */
REG_WRITE(IDT_PCI_LBA1, IDT_PCIMEM1_BASE);
REG_WRITE(IDT_PCI_LBA1_MAP, IDT_PCIMEM1_BASE);
REG_WRITE(IDT_PCI_LBA1_CNTL, IDT_PCI_LBA_SIZE_256MB | force_endianess);
pci_data = REG_READ(IDT_PCI_LBA1_CNTL);
/* LBA2 -- IO window */
REG_WRITE(IDT_PCI_LBA2, IDT_PCIMEM2_BASE);
REG_WRITE(IDT_PCI_LBA2_MAP, IDT_PCIMEM2_BASE);
REG_WRITE(IDT_PCI_LBA2_CNTL, IDT_PCI_LBA_SIZE_4MB | IDT_PCI_LBA_MSI |
force_endianess);
pci_data = REG_READ(IDT_PCI_LBA2_CNTL);
/* LBA3 -- IO window */
REG_WRITE(IDT_PCI_LBA3, IDT_PCIMEM3_BASE);
REG_WRITE(IDT_PCI_LBA3_MAP, IDT_PCIMEM3_BASE);
REG_WRITE(IDT_PCI_LBA3_CNTL, IDT_PCI_LBA_SIZE_1MB | IDT_PCI_LBA_MSI |
force_endianess);
pci_data = REG_READ(IDT_PCI_LBA3_CNTL);
pci_data = REG_READ(IDT_PCI_CNTL) & ~IDT_PCI_CNTL_TNR;
REG_WRITE(IDT_PCI_CNTL, pci_data);
pci_data = REG_READ(IDT_PCI_CNTL);
/* Rewrite Target Control register with default values */
REG_WRITE(IDT_PCI_TC, (IDT_PCI_TC_DTIMER << 8) | IDT_PCI_TC_RTIMER);
/* Perform Korina fixup */
addr = idtpci_make_addr(0, 0, 0, 4);
for (i = 0; i < 24; i++) {
REG_WRITE(IDT_PCI_CFG_ADDR, addr);
REG_WRITE(IDT_PCI_CFG_DATA, korina_fixup[i]);
__asm__ volatile ("sync");
REG_WRITE(IDT_PCI_CFG_ADDR, 0);
REG_WRITE(IDT_PCI_CFG_DATA, 0);
addr += 4;
}
/* Use KSEG1 to access IO ports for it is uncached */
sc->sc_io_rman[0].rm_type = RMAN_ARRAY;
sc->sc_io_rman[0].rm_descr = "IDTPCI I/O Ports window 1";
if (rman_init(&sc->sc_io_rman[0]) != 0 ||
rman_manage_region(&sc->sc_io_rman[0],
IDT_PCIMEM2_BASE, IDT_PCIMEM2_BASE + IDT_PCIMEM2_SIZE - 1) != 0) {
panic("idtpci_attach: failed to set up I/O rman");
}
sc->sc_io_rman[1].rm_type = RMAN_ARRAY;
sc->sc_io_rman[1].rm_descr = "IDTPCI I/O Ports window 2";
if (rman_init(&sc->sc_io_rman[1]) != 0 ||
rman_manage_region(&sc->sc_io_rman[1],
IDT_PCIMEM3_BASE, IDT_PCIMEM3_BASE + IDT_PCIMEM3_SIZE - 1) != 0) {
panic("idtpci_attach: failed to set up I/O rman");
}
/* Use KSEG1 to access PCI memory for it is uncached */
sc->sc_mem_rman[0].rm_type = RMAN_ARRAY;
sc->sc_mem_rman[0].rm_descr = "IDTPCI PCI Memory window 1";
if (rman_init(&sc->sc_mem_rman[0]) != 0 ||
rman_manage_region(&sc->sc_mem_rman[0],
IDT_PCIMEM0_BASE, IDT_PCIMEM0_BASE + IDT_PCIMEM0_SIZE) != 0) {
panic("idtpci_attach: failed to set up memory rman");
}
sc->sc_mem_rman[1].rm_type = RMAN_ARRAY;
sc->sc_mem_rman[1].rm_descr = "IDTPCI PCI Memory window 2";
if (rman_init(&sc->sc_mem_rman[1]) != 0 ||
rman_manage_region(&sc->sc_mem_rman[1],
IDT_PCIMEM1_BASE, IDT_PCIMEM1_BASE + IDT_PCIMEM1_SIZE) != 0) {
panic("idtpci_attach: failed to set up memory rman");
}
sc->sc_irq_rman.rm_type = RMAN_ARRAY;
sc->sc_irq_rman.rm_descr = "IDTPCI PCI IRQs";
if (rman_init(&sc->sc_irq_rman) != 0 ||
rman_manage_region(&sc->sc_irq_rman, PCI_IRQ_BASE,
PCI_IRQ_END) != 0)
panic("idtpci_attach: failed to set up IRQ rman");
device_add_child(dev, "pci", -1);
return (bus_generic_attach(dev));
}
static int
idtpci_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
static uint32_t
idtpci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
int bytes)
{
uint32_t data;
uint32_t shift, mask;
bus_addr_t addr;
IDTPCI_DPRINTF("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__,
bus, slot, func, reg, bytes);
addr = idtpci_make_addr(bus, slot, func, reg);
REG_WRITE(IDT_PCI_CFG_ADDR, addr);
data = REG_READ(IDT_PCI_CFG_DATA);
switch (reg % 4) {
case 3:
shift = 24;
break;
case 2:
shift = 16;
break;
case 1:
shift = 8;
break;
default:
shift = 0;
break;
}
switch (bytes) {
case 1:
mask = 0xff;
data = (data >> shift) & mask;
break;
case 2:
mask = 0xffff;
if (reg % 4 == 0)
data = data & mask;
else
data = (data >> 16) & mask;
break;
case 4:
break;
default:
panic("%s: wrong bytes count", __func__);
break;
}
__asm__ volatile ("sync");
IDTPCI_DPRINTF("%s: read 0x%x\n", __func__, data);
return (data);
}
static void
idtpci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
uint32_t data, int bytes)
{
bus_addr_t addr;
uint32_t reg_data;
uint32_t shift, mask;
IDTPCI_DPRINTF("%s: tag (%x, %x, %x) reg %d(%d) data %08x\n", __func__,
bus, slot, func, reg, bytes, data);
if (bytes != 4) {
reg_data = idtpci_read_config(dev, bus, slot, func, reg, 4);
switch (reg % 4) {
case 3:
shift = 24;
break;
case 2:
shift = 16;
break;
case 1:
shift = 8;
break;
default:
shift = 0;
break;
}
switch (bytes) {
case 1:
mask = 0xff;
data = (reg_data & ~ (mask << shift)) | (data << shift);
break;
case 2:
mask = 0xffff;
if (reg % 4 == 0)
data = (reg_data & ~mask) | data;
else
data = (reg_data & ~ (mask << shift)) |
(data << shift);
break;
case 4:
break;
default:
panic("%s: wrong bytes count", __func__);
break;
}
}
addr = idtpci_make_addr(bus, slot, func, reg);
REG_WRITE(IDT_PCI_CFG_ADDR, addr);
REG_WRITE(IDT_PCI_CFG_DATA, data);
__asm__ volatile ("sync");
REG_WRITE(IDT_PCI_CFG_ADDR, 0);
REG_WRITE(IDT_PCI_CFG_DATA, 0);
}
static int
idtpci_route_interrupt(device_t pcib, device_t device, int pin)
{
static int idt_pci_table[2][12] =
{
{ 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
{ 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
};
int dev, bus, irq;
dev = pci_get_slot(device);
bus = pci_get_bus(device);
if (bootverbose)
device_printf(pcib, "routing pin %d for %s\n", pin,
device_get_nameunit(device));
if (bus >= 0 && bus <= 1 &&
dev >= 0 && dev <= 11) {
irq = IP_IRQ(6, idt_pci_table[bus][dev] + 4);
if (bootverbose)
printf("idtpci: %d/%d/%d -> IRQ%d\n",
pci_get_bus(device), dev, pci_get_function(device),
irq);
return (irq);
} else
printf("idtpci: no mapping for %d/%d/%d\n",
pci_get_bus(device), dev, pci_get_function(device));
return (-1);
}
static int
idtpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
struct idtpci_softc *sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_DOMAIN:
*result = 0;
return (0);
case PCIB_IVAR_BUS:
*result = sc->sc_busno;
return (0);
}
return (ENOENT);
}
static int
idtpci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
{
struct idtpci_softc * sc = device_get_softc(dev);
switch (which) {
case PCIB_IVAR_BUS:
sc->sc_busno = result;
return (0);
}
return (ENOENT);
}
static struct resource *
idtpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct idtpci_softc *sc = device_get_softc(bus);
struct resource *rv = NULL;
struct rman *rm1, *rm2;
switch (type) {
case SYS_RES_IRQ:
rm1 = &sc->sc_irq_rman;
rm2 = NULL;
break;
case SYS_RES_MEMORY:
rm1 = &sc->sc_mem_rman[0];
rm2 = &sc->sc_mem_rman[1];
break;
case SYS_RES_IOPORT:
rm1 = &sc->sc_io_rman[0];
rm2 = &sc->sc_io_rman[1];
break;
default:
return (NULL);
}
rv = rman_reserve_resource(rm1, start, end, count, flags, child);
/* Try second window if it exists */
if ((rv == NULL) && (rm2 != NULL))
rv = rman_reserve_resource(rm2, start, end, count, flags,
child);
if (rv == NULL)
return (NULL);
rman_set_rid(rv, *rid);
if (flags & RF_ACTIVE) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return (rv);
}
static int
idtpci_teardown_intr(device_t dev, device_t child, struct resource *res,
void *cookie)
{
return (intr_event_remove_handler(cookie));
}
static device_method_t idtpci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, idtpci_probe),
DEVMETHOD(device_attach, idtpci_attach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
/* Bus interface */
DEVMETHOD(bus_read_ivar, idtpci_read_ivar),
DEVMETHOD(bus_write_ivar, idtpci_write_ivar),
DEVMETHOD(bus_alloc_resource, idtpci_alloc_resource),
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
DEVMETHOD(bus_teardown_intr, idtpci_teardown_intr),
/* pcib interface */
DEVMETHOD(pcib_maxslots, idtpci_maxslots),
DEVMETHOD(pcib_read_config, idtpci_read_config),
DEVMETHOD(pcib_write_config, idtpci_write_config),
DEVMETHOD(pcib_route_interrupt, idtpci_route_interrupt),
DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
DEVMETHOD_END
};
static driver_t idtpci_driver = {
"pcib",
idtpci_methods,
sizeof(struct idtpci_softc),
};
static devclass_t idtpci_devclass;
DRIVER_MODULE(idtpci, obio, idtpci_driver, idtpci_devclass, 0, 0);

155
sys/mips/idt/idtreg.h
View File

@ -1,155 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef __IDTREG_H__
#define __IDTREG_H__
/* Interrupt controller */
#define IDT_BASE_ICU 0x18038000
#define ICU_IPEND2 0x00
#define ICU_ITEST2 0x04
#define ICU_IMASK2 0x08
#define ICU_IPEND3 0x0C
#define ICU_ITEST3 0x10
#define ICU_IMASK3 0x14
#define ICU_IPEND4 0x18
#define ICU_ITEST4 0x1c
#define ICU_IMASK4 0x20
#define ICU_IPEND5 0x24
#define ICU_ITEST5 0x28
#define ICU_IMASK5 0x2c
#define ICU_IPEND6 0x30
#define ICU_ITEST6 0x34
#define ICU_IMASK6 0x38
#define ICU_NMIPS 0x3c
#define IDT_BASE_GPIO 0x18050000
#define GPIO_FUNC 0x00
#define GPIO_CFG 0x04
#define GPIO_DATA 0x08
#define GPIO_ILEVEL 0x0C
#define GPIO_ISTAT 0x10
#define GPIO_NMIEN 0x14
#define IDT_BASE_UART0 0x18058000
/* PCI controller */
#define IDT_BASE_PCI 0x18080000
#define IDT_PCI_CNTL 0x00
#define IDT_PCI_CNTL_EN 0x001
#define IDT_PCI_CNTL_TNR 0x002
#define IDT_PCI_CNTL_SCE 0x004
#define IDT_PCI_CNTL_IEN 0x008
#define IDT_PCI_CNTL_AAA 0x010
#define IDT_PCI_CNTL_EAP 0x020
#define IDT_PCI_CNTL_IGM 0x200
#define IDT_PCI_STATUS 0x04
#define IDT_PCI_STATUS_RIP 0x20000
#define IDT_PCI_STATUS_MASK 0x08
#define IDT_PCI_CFG_ADDR 0x0C
#define IDT_PCI_CFG_DATA 0x10
/* LBA stuff */
#define IDT_PCI_LBA0 0x14
#define IDT_PCI_LBA0_CNTL 0x18
#define IDT_PCI_LBA_MSI 0x01
#define IDT_PCI_LBA_SIZE_1MB (0x14 << 2)
#define IDT_PCI_LBA_SIZE_2MB (0x15 << 2)
#define IDT_PCI_LBA_SIZE_4MB (0x16 << 2)
#define IDT_PCI_LBA_SIZE_8MB (0x17 << 2)
#define IDT_PCI_LBA_SIZE_16MB (0x18 << 2)
#define IDT_PCI_LBA_SIZE_32MB (0x19 << 2)
#define IDT_PCI_LBA_SIZE_64MB (0x1A << 2)
#define IDT_PCI_LBA_SIZE_128MB (0x1B << 2)
#define IDT_PCI_LBA_SIZE_256MB (0x1C << 2)
#define IDT_PCI_LBA_FE 0x80
#define IDT_PCI_LBA_RT 0x100
#define IDT_PCI_LBA0_MAP 0x1C
#define IDT_PCI_LBA1 0x20
#define IDT_PCI_LBA1_CNTL 0x24
#define IDT_PCI_LBA1_MAP 0x28
#define IDT_PCI_LBA2 0x2C
#define IDT_PCI_LBA2_CNTL 0x30
#define IDT_PCI_LBA2_MAP 0x34
#define IDT_PCI_LBA3 0x38
#define IDT_PCI_LBA3_CNTL 0x3C
#define IDT_PCI_LBA3_MAP 0x40
/* decoupled registers */
#define IDT_PCI_DAC 0x44
#define IDT_PCI_DAS 0x48
#define IDT_PCI_DASM 0x4C
#define IDT_PCI_TC 0x5C
#define IDT_PCI_TC_RTIMER 0x10
#define IDT_PCI_TC_DTIMER 0x08
/* Messaging unit of PCI controller */
#define IDT_PCI_IIC 0x8024
#define IDT_PCI_IIM 0x8028
#define IDT_PCI_OIC 0x8030
#define IDT_PCI_OIM 0x8034
/* PCI-related stuff */
#define IDT_PCIMEM0_BASE 0x50000000
#define IDT_PCIMEM0_SIZE 0x01000000
#define IDT_PCIMEM1_BASE 0x60000000
#define IDT_PCIMEM1_SIZE 0x10000000
#define IDT_PCIMEM2_BASE 0x18C00000
#define IDT_PCIMEM2_SIZE 0x00400000
#define IDT_PCIMEM3_BASE 0x18800000
#define IDT_PCIMEM3_SIZE 0x00100000
/* Interrupts-related stuff */
#define IRQ_BASE 8
/* Convert <IPbit, irq_offset> pair to IRQ number */
#define IP_IRQ(IPbit, offset) ((IPbit - 2) * 32 + (offset) + IRQ_BASE)
/* The last one available IRQ */
#define IRQ_END IP_IRQ(6, 31)
#define ICU_GROUP_REG_OFFSET 0x0C
#define ICU_IP(irq) (((irq) - IRQ_BASE) & 0x1f)
#define ICU_IP_BIT(irq) (1 << ICU_IP(irq))
#define ICU_GROUP(irq) (((irq) - IRQ_BASE) >> 5)
#define ICU_GROUP_MASK_REG(group) \
(ICU_IMASK2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
#define ICU_GROUP_IPEND_REG(group) \
(ICU_IPEND2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
#define ICU_IRQ_MASK_REG(irq) \
(ICU_IMASK2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
#define ICU_IRQ_IPEND_REG(irq) \
(ICU_IPEND2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
#define PCI_IRQ_BASE IP_IRQ(6, 4)
#define PCI_IRQ_END IP_IRQ(6, 7)
#endif /* __IDTREG_H__ */

1613
sys/mips/idt/if_kr.c
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286
sys/mips/idt/if_krreg.h
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@ -1,286 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (C) 2007
* Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef __IF_KRREG_H__
#define __IF_KRREG_H__
#define KR_ETHINTFC 0x0000 /* Ethernet interface control */
#define ETH_INTFC_EN 0x0001
#define ETH_INTFC_RIP 0x0004
#define ETH_INTFC_EN 0x0001
#define KR_ETHFIFOTT 0x0004 /* Ethernet FIFO transmit threshold */
#define KR_ETHARC 0x0008 /* Ethernet address recognition control */
#define KR_ETHHASH0 0x000C /* Ethernet hash table 0 */
#define KR_ETHHASH1 0x0010 /* Ethernet hash table 1 */
#define KR_ETHPFS 0x0024 /* Ethernet pause frame status */
#define KR_ETHMCP 0x0028 /* Ethernet management clock prescalar */
#define KR_ETHSAL0 0x0100 /* Ethernet station address 0 low */
#define KR_ETHSAH0 0x0104 /* Ethernet station address 0 high */
#define KR_ETHSAL1 0x0108 /* Ethernet station address 1 low */
#define KR_ETHSAH1 0x010C /* Ethernet station address 1 high */
#define KR_ETHSAL2 0x0110 /* Ethernet station address 2 low */
#define KR_ETHSAH2 0x0114 /* Ethernet station address 2 high */
#define KR_ETHSAL3 0x0118 /* Ethernet station address 3 low */
#define KR_ETHSAH3 0x011C /* Ethernet station address 3 high */
#define KR_ETHRBC 0x0120 /* Ethernet receive byte count */
#define KR_ETHRPC 0x0124 /* Ethernet receive packet count */
#define KR_ETHRUPC 0x0128 /* Ethernet receive undersized packet cnt */
#define KR_ETHRFC 0x012C /* Ethernet receive fragment count */
#define KR_ETHTBC 0x0130 /* Ethernet transmit byte count */
#define KR_ETHGPF 0x0134 /* Ethernet generate pause frame */
#define KR_ETHMAC1 0x0200 /* Ethernet MAC configuration 1 */
#define KR_ETH_MAC1_RE 0x01
#define KR_ETH_MAC1_PAF 0x02
#define KR_ETH_MAC1_MR 0x80
#define KR_ETHMAC2 0x0204 /* Ethernet MAC configuration 2 */
#define KR_ETH_MAC2_FD 0x01
#define KR_ETH_MAC2_FLC 0x02
#define KR_ETH_MAC2_HFE 0x04
#define KR_ETH_MAC2_DC 0x08
#define KR_ETH_MAC2_CEN 0x10
#define KR_ETH_MAC2_PEN 0x20
#define KR_ETH_MAC2_VPE 0x08
#define KR_ETHIPGT 0x0208 /* Ethernet back-to-back inter-packet gap */
#define KR_ETHIPGR 0x020C /* Ethernet non back-to-back inter-packet gap */
#define KR_ETHCLRT 0x0210 /* Ethernet collision window retry */
#define KR_ETHMAXF 0x0214 /* Ethernet maximum frame length */
#define KR_ETHMTEST 0x021C /* Ethernet MAC test */
#define KR_MIIMCFG 0x0220 /* MII management configuration */
#define KR_MIIMCFG_R 0x8000
#define KR_MIIMCMD 0x0224 /* MII management command */
#define KR_MIIMCMD_RD 0x01
#define KR_MIIMCMD_SCN 0x02
#define KR_MIIMADDR 0x0228 /* MII management address */
#define KR_MIIMWTD 0x022C /* MII management write data */
#define KR_MIIMRDD 0x0230 /* MII management read data */
#define KR_MIIMIND 0x0234 /* MII management indicators */
#define KR_MIIMIND_BSY 0x1
#define KR_MIIMIND_SCN 0x2
#define KR_MIIMIND_NV 0x4
#define KR_ETHCFSA0 0x0240 /* Ethernet control frame station address 0 */
#define KR_ETHCFSA1 0x0244 /* Ethernet control frame station address 1 */
#define KR_ETHCFSA2 0x0248 /* Ethernet control frame station address 2 */
#define KR_ETHIPGT_HALF_DUPLEX 0x12
#define KR_ETHIPGT_FULL_DUPLEX 0x15
#define KR_TIMEOUT 0xf000
#define KR_MII_TIMEOUT 0xf000
#define KR_RX_IRQ 40
#define KR_TX_IRQ 41
#define KR_RX_UND_IRQ 42
#define KR_TX_OVR_IRQ 43
#define RC32434_DMA_BASE_ADDR MIPS_PHYS_TO_KSEG1(0x18040000)
#define DMA_C 0x00
#define DMA_C_R 0x01
#define DMA_C_ABORT 0x10
#define DMA_S 0x04
#define DMA_S_F 0x01
#define DMA_S_D 0x02
#define DMA_S_C 0x04
#define DMA_S_E 0x08
#define DMA_S_H 0x10
#define DMA_SM 0x08
#define DMA_SM_F 0x01
#define DMA_SM_D 0x02
#define DMA_SM_C 0x04
#define DMA_SM_E 0x08
#define DMA_SM_H 0x10
#define DMA_DPTR 0x0C
#define DMA_NDPTR 0x10
#define RC32434_DMA_CHAN_SIZE 0x14
#define KR_DMA_RXCHAN 0
#define KR_DMA_TXCHAN 1
#define KR_DMA_READ_REG(chan, reg) \
(*(volatile uint32_t *) \
(RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg))
#define KR_DMA_WRITE_REG(chan, reg, val) \
((*(volatile uint32_t *) \
(RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) = val)
#define KR_DMA_SETBITS_REG(chan, reg, bits) \
KR_DMA_WRITE_REG((chan), (reg), KR_DMA_READ_REG((chan), (reg)) | (bits))
#define KR_DMA_CLEARBITS_REG(chan, reg, bits) \
KR_DMA_WRITE_REG((chan), (reg), \
KR_DMA_READ_REG((chan), (reg)) & ~(bits))
struct kr_desc {
uint32_t kr_ctl;
uint32_t kr_ca;
uint32_t kr_devcs;
uint32_t kr_link;
};
#define KR_DMASIZE(len) ((len) & ((1 << 18)-1))
#define KR_PKTSIZE(len) ((len & 0xffff0000) >> 16)
#define KR_CTL_COF 0x02000000
#define KR_CTL_COD 0x04000000
#define KR_CTL_IOF 0x08000000
#define KR_CTL_IOD 0x10000000
#define KR_CTL_T 0x20000000
#define KR_CTL_D 0x40000000
#define KR_CTL_F 0x80000000
#define KR_DMARX_DEVCS_RSV 0x00000001
#define KR_DMARX_DEVCS_LD 0x00000002
#define KR_DMARX_DEVCS_ROK 0x00000004
#define KR_DMARX_DEVCS_FM 0x00000008
#define KR_DMARX_DEVCS_MP 0x00000010
#define KR_DMARX_DEVCS_BP 0x00000020
#define KR_DMARX_DEVCS_VLT 0x00000040
#define KR_DMARX_DEVCS_CF 0x00000080
#define KR_DMARX_DEVCS_OVR 0x00000100
#define KR_DMARX_DEVCS_CRC 0x00000200
#define KR_DMARX_DEVCS_CV 0x00000400
#define KR_DMARX_DEVCS_DB 0x00000800
#define KR_DMARX_DEVCS_LE 0x00001000
#define KR_DMARX_DEVCS_LOR 0x00002000
#define KR_DMARX_DEVCS_CES 0x00004000
#define KR_DMATX_DEVCS_FD 0x00000001
#define KR_DMATX_DEVCS_LD 0x00000002
#define KR_DMATX_DEVCS_OEN 0x00000004
#define KR_DMATX_DEVCS_PEN 0x00000008
#define KR_DMATX_DEVCS_CEN 0x00000010
#define KR_DMATX_DEVCS_HEN 0x00000020
#define KR_DMATX_DEVCS_TOK 0x00000040
#define KR_DMATX_DEVCS_MP 0x00000080
#define KR_DMATX_DEVCS_BP 0x00000100
#define KR_DMATX_DEVCS_UND 0x00000200
#define KR_DMATX_DEVCS_OF 0x00000400
#define KR_DMATX_DEVCS_ED 0x00000800
#define KR_DMATX_DEVCS_EC 0x00001000
#define KR_DMATX_DEVCS_LC 0x00002000
#define KR_DMATX_DEVCS_TD 0x00004000
#define KR_DMATX_DEVCS_CRC 0x00008000
#define KR_DMATX_DEVCS_LE 0x00010000
#define KR_RX_RING_CNT 128
#define KR_TX_RING_CNT 128
#define KR_TX_RING_SIZE sizeof(struct kr_desc) * KR_TX_RING_CNT
#define KR_RX_RING_SIZE sizeof(struct kr_desc) * KR_RX_RING_CNT
#define KR_RING_ALIGN sizeof(struct kr_desc)
#define KR_RX_ALIGN sizeof(uint32_t)
#define KR_MAXFRAGS 8
#define KR_TX_INTR_THRESH 8
#define KR_TX_RING_ADDR(sc, i) \
((sc)->kr_rdata.kr_tx_ring_paddr + sizeof(struct kr_desc) * (i))
#define KR_RX_RING_ADDR(sc, i) \
((sc)->kr_rdata.kr_rx_ring_paddr + sizeof(struct kr_desc) * (i))
#define KR_INC(x,y) (x) = (((x) + 1) % y)
struct kr_txdesc {
struct mbuf *tx_m;
bus_dmamap_t tx_dmamap;
};
struct kr_rxdesc {
struct mbuf *rx_m;
bus_dmamap_t rx_dmamap;
struct kr_desc *desc;
/* Use this values on error instead of allocating new mbuf */
uint32_t saved_ctl, saved_ca;
};
struct kr_chain_data {
bus_dma_tag_t kr_parent_tag;
bus_dma_tag_t kr_tx_tag;
struct kr_txdesc kr_txdesc[KR_TX_RING_CNT];
bus_dma_tag_t kr_rx_tag;
struct kr_rxdesc kr_rxdesc[KR_RX_RING_CNT];
bus_dma_tag_t kr_tx_ring_tag;
bus_dma_tag_t kr_rx_ring_tag;
bus_dmamap_t kr_tx_ring_map;
bus_dmamap_t kr_rx_ring_map;
bus_dmamap_t kr_rx_sparemap;
int kr_tx_pkts;
int kr_tx_prod;
int kr_tx_cons;
int kr_tx_cnt;
int kr_rx_cons;
};
struct kr_ring_data {
struct kr_desc *kr_rx_ring;
struct kr_desc *kr_tx_ring;
bus_addr_t kr_rx_ring_paddr;
bus_addr_t kr_tx_ring_paddr;
};
struct kr_softc {
struct ifnet *kr_ifp; /* interface info */
bus_space_handle_t kr_bhandle; /* bus space handle */
bus_space_tag_t kr_btag; /* bus space tag */
device_t kr_dev;
struct resource *kr_res;
int kr_rid;
struct resource *kr_rx_irq;
void *kr_rx_intrhand;
struct resource *kr_tx_irq;
void *kr_tx_intrhand;
struct resource *kr_rx_und_irq;
void *kr_rx_und_intrhand;
struct resource *kr_tx_ovr_irq;
void *kr_tx_ovr_intrhand;
device_t kr_miibus;
bus_dma_tag_t kr_parent_tag;
bus_dma_tag_t kr_tag;
struct mtx kr_mtx;
struct callout kr_stat_callout;
struct task kr_link_task;
struct kr_chain_data kr_cdata;
struct kr_ring_data kr_rdata;
int kr_link_status;
int kr_detach;
};
#define KR_LOCK(_sc) mtx_lock(&(_sc)->kr_mtx)
#define KR_UNLOCK(_sc) mtx_unlock(&(_sc)->kr_mtx)
#define KR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->kr_mtx, MA_OWNED)
/*
* register space access macros
*/
#define CSR_WRITE_4(sc, reg, val) \
bus_space_write_4(sc->kr_btag, sc->kr_bhandle, reg, val)
#define CSR_READ_4(sc, reg) \
bus_space_read_4(sc->kr_btag, sc->kr_bhandle, reg)
#endif /* __IF_KRREG_H__ */

484
sys/mips/idt/obio.c
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@ -1,484 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2007, Oleksandr Tymoshenko <gonzo@freebsd.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/interrupt.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/malloc.h>
#include <machine/bus.h>
#include <mips/idt/idtreg.h>
#include <mips/idt/obiovar.h>
#define ICU_REG_READ(o) \
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_ICU + (o)))
#define ICU_REG_WRITE(o,v) (ICU_REG_READ(o)) = (v)
#define GPIO_REG_READ(o) \
*((volatile uint32_t *)MIPS_PHYS_TO_KSEG1(IDT_BASE_GPIO + (o)))
#define GPIO_REG_WRITE(o,v) (GPIO_REG_READ(o)) = (v)
static int obio_activate_resource(device_t, device_t, int, int,
struct resource *);
static device_t obio_add_child(device_t, u_int, const char *, int);
static struct resource *
obio_alloc_resource(device_t, device_t, int, int *, rman_res_t,
rman_res_t, rman_res_t, u_int);
static int obio_attach(device_t);
static int obio_deactivate_resource(device_t, device_t, int, int,
struct resource *);
static struct resource_list *
obio_get_resource_list(device_t, device_t);
static void obio_hinted_child(device_t, const char *, int);
static int obio_intr(void *);
static int obio_probe(device_t);
static int obio_release_resource(device_t, device_t, int, int,
struct resource *);
static int obio_setup_intr(device_t, device_t, struct resource *, int,
driver_filter_t *, driver_intr_t *, void *, void **);
static int obio_teardown_intr(device_t, device_t, struct resource *,
void *);
static void
obio_mask_irq(void *arg)
{
unsigned int irq = (unsigned int)arg;
int ip_bit, mask, mask_register;
/* mask IRQ */
mask_register = ICU_IRQ_MASK_REG(irq);
ip_bit = ICU_IP_BIT(irq);
mask = ICU_REG_READ(mask_register);
ICU_REG_WRITE(mask_register, mask | ip_bit);
}
static void
obio_unmask_irq(void *arg)
{
unsigned int irq = (unsigned int)arg;
int ip_bit, mask, mask_register;
/* unmask IRQ */
mask_register = ICU_IRQ_MASK_REG(irq);
ip_bit = ICU_IP_BIT(irq);
mask = ICU_REG_READ(mask_register);
ICU_REG_WRITE(mask_register, mask & ~ip_bit);
}
static int
obio_probe(device_t dev)
{
return (BUS_PROBE_NOWILDCARD);
}
static int
obio_attach(device_t dev)
{
struct obio_softc *sc = device_get_softc(dev);
int rid, irq;
sc->oba_mem_rman.rm_type = RMAN_ARRAY;
sc->oba_mem_rman.rm_descr = "OBIO memeory";
if (rman_init(&sc->oba_mem_rman) != 0 ||
rman_manage_region(&sc->oba_mem_rman, OBIO_MEM_START,
OBIO_MEM_START + OBIO_MEM_SIZE) != 0)
panic("obio_attach: failed to set up I/O rman");
sc->oba_irq_rman.rm_type = RMAN_ARRAY;
sc->oba_irq_rman.rm_descr = "OBIO IRQ";
if (rman_init(&sc->oba_irq_rman) != 0 ||
rman_manage_region(&sc->oba_irq_rman, IRQ_BASE, IRQ_END) != 0)
panic("obio_attach: failed to set up IRQ rman");
/* Hook up our interrupt handlers. We should handle IRQ0..IRQ4*/
for(irq = 0; irq < 5; irq++) {
if ((sc->sc_irq[irq] = bus_alloc_resource(dev, SYS_RES_IRQ,
&rid, irq, irq, 1, RF_SHAREABLE | RF_ACTIVE)) == NULL) {
device_printf(dev, "unable to allocate IRQ resource\n");
return (ENXIO);
}
if ((bus_setup_intr(dev, sc->sc_irq[irq], INTR_TYPE_MISC,
obio_intr, NULL, sc, &sc->sc_ih[irq]))) {
device_printf(dev,
"WARNING: unable to register interrupt handler\n");
return (ENXIO);
}
}
bus_generic_probe(dev);
bus_enumerate_hinted_children(dev);
bus_generic_attach(dev);
return (0);
}
static struct resource *
obio_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct obio_softc *sc = device_get_softc(bus);
struct obio_ivar *ivar = device_get_ivars(child);
struct resource *rv;
struct resource_list_entry *rle;
struct rman *rm;
int isdefault, needactivate, passthrough;
isdefault = (RMAN_IS_DEFAULT_RANGE(start, end));
needactivate = flags & RF_ACTIVE;
passthrough = (device_get_parent(child) != bus);
rle = NULL;
if (passthrough)
return (BUS_ALLOC_RESOURCE(device_get_parent(bus), child, type,
rid, start, end, count, flags));
/*
* If this is an allocation of the "default" range for a given RID,
* and we know what the resources for this device are (ie. they aren't
* maintained by a child bus), then work out the start/end values.
*/
if (isdefault) {
rle = resource_list_find(&ivar->resources, type, *rid);
if (rle == NULL)
return (NULL);
if (rle->res != NULL) {
panic("%s: resource entry is busy", __func__);
}
start = rle->start;
end = rle->end;
count = rle->count;
}
switch (type) {
case SYS_RES_IRQ:
rm = &sc->oba_irq_rman;
break;
case SYS_RES_MEMORY:
rm = &sc->oba_mem_rman;
break;
default:
printf("%s: unknown resource type %d\n", __func__, type);
return (0);
}
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL) {
printf("%s: could not reserve resource\n", __func__);
return (0);
}
rman_set_rid(rv, *rid);
if (needactivate) {
if (bus_activate_resource(child, type, *rid, rv)) {
printf("%s: could not activate resource\n", __func__);
rman_release_resource(rv);
return (0);
}
}
return (rv);
}
static int
obio_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
/* XXX: should we mask/unmask IRQ here? */
return (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
}
static int
obio_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
/* XXX: should we mask/unmask IRQ here? */
return (BUS_DEACTIVATE_RESOURCE(device_get_parent(bus), child,
type, rid, r));
}
static int
obio_release_resource(device_t dev, device_t child, int type,
int rid, struct resource *r)
{
struct resource_list *rl;
struct resource_list_entry *rle;
rl = obio_get_resource_list(dev, child);
if (rl == NULL)
return (EINVAL);
rle = resource_list_find(rl, type, rid);
if (rle == NULL)
return (EINVAL);
rman_release_resource(r);
rle->res = NULL;
return (0);
}
static int
obio_setup_intr(device_t dev, device_t child, struct resource *ires,
int flags, driver_filter_t *filt, driver_intr_t *handler,
void *arg, void **cookiep)
{
struct obio_softc *sc = device_get_softc(dev);
struct intr_event *event;
int irq, ip_bit, error, mask, mask_register;
irq = rman_get_start(ires);
if (irq >= NIRQS)
panic("%s: bad irq %d", __func__, irq);
event = sc->sc_eventstab[irq];
if (event == NULL) {
error = intr_event_create(&event, (void *)irq, 0, irq,
obio_mask_irq, obio_unmask_irq,
NULL, NULL,
"obio intr%d:", irq);
sc->sc_eventstab[irq] = event;
}
intr_event_add_handler(event, device_get_nameunit(child), filt,
handler, arg, intr_priority(flags), flags, cookiep);
/* unmask IRQ */
mask_register = ICU_IRQ_MASK_REG(irq);
ip_bit = ICU_IP_BIT(irq);
mask = ICU_REG_READ(mask_register);
ICU_REG_WRITE(mask_register, mask & ~ip_bit);
return (0);
}
static int
obio_teardown_intr(device_t dev, device_t child, struct resource *ires,
void *cookie)
{
struct obio_softc *sc = device_get_softc(dev);
int irq, result;
uint32_t mask_register, mask, ip_bit;
irq = rman_get_start(ires);
if (irq >= NIRQS)
panic("%s: bad irq %d", __func__, irq);
if (sc->sc_eventstab[irq] == NULL)
panic("Trying to teardown unoccupied IRQ");
/* mask IRQ */
mask_register = ICU_IRQ_MASK_REG(irq);
ip_bit = ICU_IP_BIT(irq);
mask = ICU_REG_READ(mask_register);
ICU_REG_WRITE(mask_register, mask | ip_bit);
result = intr_event_remove_handler(cookie);
if (!result)
sc->sc_eventstab[irq] = NULL;
return (result);
}
static int
obio_intr(void *arg)
{
struct obio_softc *sc = arg;
struct intr_event *event;
uint32_t irqstat, ipend, imask, xpend;
int irq, thread, group, i;
irqstat = 0;
irq = 0;
for (group = 2; group <= 6; group++) {
ipend = ICU_REG_READ(ICU_GROUP_IPEND_REG(group));
imask = ICU_REG_READ(ICU_GROUP_MASK_REG(group));
xpend = ipend;
ipend &= ~imask;
while ((i = fls(xpend)) != 0) {
xpend &= ~(1 << (i - 1));
irq = IP_IRQ(group, i - 1);
}
while ((i = fls(ipend)) != 0) {
ipend &= ~(1 << (i - 1));
irq = IP_IRQ(group, i - 1);
event = sc->sc_eventstab[irq];
thread = 0;
if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
/* TODO: Log stray IRQs */
continue;
}
/* TODO: frame instead of NULL? */
intr_event_handle(event, NULL);
/* XXX: Log stray IRQs */
}
}
#if 0
ipend = ICU_REG_READ(ICU_IPEND2);
printf("ipend2 = %08x!\n", ipend);
ipend = ICU_REG_READ(ICU_IPEND3);
printf("ipend3 = %08x!\n", ipend);
ipend = ICU_REG_READ(ICU_IPEND4);
printf("ipend4 = %08x!\n", ipend);
ipend = ICU_REG_READ(ICU_IPEND5);
printf("ipend5 = %08x!\n", ipend);
ipend = ICU_REG_READ(ICU_IPEND6);
printf("ipend6 = %08x!\n", ipend);
#endif
while (irqstat != 0) {
if ((irqstat & 1) == 1) {
}
irq++;
irqstat >>= 1;
}
return (FILTER_HANDLED);
}
static void
obio_hinted_child(device_t bus, const char *dname, int dunit)
{
device_t child;
long maddr;
int msize;
int irq;
int result;
child = BUS_ADD_CHILD(bus, 0, dname, dunit);
/*
* Set hard-wired resources for hinted child using
* specific RIDs.
*/
resource_long_value(dname, dunit, "maddr", &maddr);
resource_int_value(dname, dunit, "msize", &msize);
result = bus_set_resource(child, SYS_RES_MEMORY, 0,
maddr, msize);
if (result != 0)
device_printf(bus, "warning: bus_set_resource() failed\n");
if (resource_int_value(dname, dunit, "irq", &irq) == 0) {
result = bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1);
if (result != 0)
device_printf(bus,
"warning: bus_set_resource() failed\n");
}
}
static device_t
obio_add_child(device_t bus, u_int order, const char *name, int unit)
{
device_t child;
struct obio_ivar *ivar;
ivar = malloc(sizeof(struct obio_ivar), M_DEVBUF, M_WAITOK | M_ZERO);
resource_list_init(&ivar->resources);
child = device_add_child_ordered(bus, order, name, unit);
if (child == NULL) {
printf("Can't add child %s%d ordered\n", name, unit);
return (0);
}
device_set_ivars(child, ivar);
return (child);
}
/*
* Helper routine for bus_generic_rl_get_resource/bus_generic_rl_set_resource
* Provides pointer to resource_list for these routines
*/
static struct resource_list *
obio_get_resource_list(device_t dev, device_t child)
{
struct obio_ivar *ivar;
ivar = device_get_ivars(child);
return (&(ivar->resources));
}
static device_method_t obio_methods[] = {
DEVMETHOD(bus_activate_resource, obio_activate_resource),
DEVMETHOD(bus_add_child, obio_add_child),
DEVMETHOD(bus_alloc_resource, obio_alloc_resource),
DEVMETHOD(bus_deactivate_resource, obio_deactivate_resource),
DEVMETHOD(bus_get_resource_list, obio_get_resource_list),
DEVMETHOD(bus_hinted_child, obio_hinted_child),
DEVMETHOD(bus_release_resource, obio_release_resource),
DEVMETHOD(bus_setup_intr, obio_setup_intr),
DEVMETHOD(bus_teardown_intr, obio_teardown_intr),
DEVMETHOD(device_attach, obio_attach),
DEVMETHOD(device_probe, obio_probe),
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
{0, 0},
};
static driver_t obio_driver = {
"obio",
obio_methods,
sizeof(struct obio_softc),
};
static devclass_t obio_devclass;
DRIVER_MODULE(obio, nexus, obio_driver, obio_devclass, 0, 0);

69
sys/mips/idt/obiovar.h
View File

@ -1,69 +0,0 @@
/* $NetBSD: obiovar.h,v 1.4 2003/06/16 17:40:53 thorpej Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2002, 2003 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* $FreeBSD$
*
*/
#ifndef _ADM5120_OBIOVAR_H_
#define _ADM5120_OBIOVAR_H_
#include <sys/rman.h>
/* Number of controller's IRQs */
#define NIRQS 32*5
/* Number of CPU IRQ lines */
#define MIPS_IRQS 5
#define OBIO_MEM_START 0x18000000L
#define OBIO_MEM_SIZE 0x200000
struct obio_softc {
struct rman oba_mem_rman;
struct rman oba_irq_rman;
struct intr_event *sc_eventstab[NIRQS]; /* IRQ events structs */
struct resource *sc_irq[MIPS_IRQS]; /* IRQ resource */
void *sc_ih[MIPS_IRQS]; /* interrupt cookie */
};
struct obio_ivar {
struct resource_list resources;
};
#endif /* _ADM5120_OBIOVAR_H_ */

6
sys/mips/idt/std.idt
View File

@ -1,6 +0,0 @@
# $FreeBSD$
# Standard include file for IDT
files "../idt/files.idt"
machine mips mipsel

102
sys/mips/idt/uart_bus_rc32434.c
View File

@ -1,102 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2007 Bruce M. Simpson.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* $Id$
*/
/*
* Skeleton of this file was based on respective code for ARM
* code written by Olivier Houchard.
*/
/*
* XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
* experimental and was written for MIPS32 port.
*/
#include "opt_uart.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <mips/idt/idtreg.h>
#include <dev/pci/pcivar.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
#include <dev/ic/ns16550.h>
#include "uart_if.h"
static int uart_rc32434_probe(device_t dev);
extern struct uart_class uart_rc32434_uart_class;
static device_method_t uart_rc32434_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, uart_rc32434_probe),
DEVMETHOD(device_attach, uart_bus_attach),
DEVMETHOD(device_detach, uart_bus_detach),
{ 0, 0 }
};
static driver_t uart_rc32434_driver = {
uart_driver_name,
uart_rc32434_methods,
sizeof(struct uart_softc),
};
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
static int
uart_rc32434_probe(device_t dev)
{
struct uart_softc *sc;
sc = device_get_softc(dev);
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
sc->sc_class = &uart_ns8250_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
sc->sc_sysdev->bas.regshft = 2;
sc->sc_sysdev->bas.bst = mips_bus_space_generic;
sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0);
sc->sc_bas.regshft = 2;
sc->sc_bas.bst = mips_bus_space_generic;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(IDT_BASE_UART0);
return (uart_bus_probe(dev, 2, 0, 330000000UL/2, 0, 0));
}
DRIVER_MODULE(uart, obio, uart_rc32434_driver, uart_devclass, 0, 0);

87
sys/mips/idt/uart_cpu_rc32434.c
View File

@ -1,87 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id$
*/
/*
* Skeleton of this file was based on respective code for ARM
* code written by Olivier Houchard.
*/
/*
* XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
* experimental and was written for MIPS32 port.
*/
#include "opt_uart.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
extern struct uart_class uart_rc32434_uart_class;
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
uint32_t maddr;
if (resource_int_value("uart", 0, "maddr", &maddr) != 0 ||
maddr == 0)
return (ENXIO);
/* Got it. Fill in the instance and return it. */
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = mips_bus_space_generic;
di->bas.regshft = 2;
di->bas.rclk = 330000000UL/2; /* IPbus clock */
di->baudrate = 115200;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = 0;
uart_bus_space_mem = mips_bus_space_generic;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(maddr);
return (0);
}