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Code Issues Releases Activity

Expose per-lane counters before correction mechanism in mlx5en(4).

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MFC after:	3 days
Sponsored by:	Mellanox Technologies
This commit is contained in:
Hans Petter Selasky 2019-05-08 11:03:29 +00:00
parent 5f9484f3f1
commit c62f4d8de8
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=347310
2 changed files with 33 additions and 0 deletions
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21
sys/dev/mlx5/mlx5_en/en.h
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@ -281,6 +281,24 @@ struct mlx5e_vport_stats {
m(+1, u64, tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \
m(+1, u64, tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes")
#define MLX5E_PPORT_STATISTICAL_DEBUG(m) \
m(+1, u64, phy_time_since_last_clear, "phy_time_since_last_clear", \
"Time since last clear in milliseconds") \
m(+1, u64, phy_received_bits, "phy_received_bits", \
"Total amount of traffic received in bits before error correction") \
m(+1, u64, phy_symbol_errors, "phy_symbol_errors", \
"Total number of symbol errors before error correction") \
m(+1, u64, phy_corrected_bits, "phy_corrected_bits", \
"Total number of corrected bits ") \
m(+1, u64, phy_corrected_bits_lane0, "phy_corrected_bits_lane0", \
"Total number of corrected bits for lane 0") \
m(+1, u64, phy_corrected_bits_lane1, "phy_corrected_bits_lane1", \
"Total number of corrected bits for lane 1") \
m(+1, u64, phy_corrected_bits_lane2, "phy_corrected_bits_lane2", \
"Total number of corrected bits for lane 2") \
m(+1, u64, phy_corrected_bits_lane3, "phy_corrected_bits_lane3", \
"Total number of corrected bits for lane 3")
#define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
m(+1, u64, time_since_last_clear, "time_since_last_clear", \
"Time since the last counters clear event (msec)") \
@ -523,6 +541,7 @@ struct mlx5e_vport_stats {
MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \
MLX5E_PPORT_STATISTICAL_DEBUG(m) \
MLX5E_PCIE_PERFORMANCE_COUNTERS_64(m) \
MLX5E_PCIE_PERFORMANCE_COUNTERS_32(m) \
MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(m) \
@ -545,6 +564,8 @@ struct mlx5e_vport_stats {
(0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
#define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \
(0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT))
#define MLX5E_PPORT_STATISTICAL_DEBUG_NUM \
(0 MLX5E_PPORT_STATISTICAL_DEBUG(MLX5E_STATS_COUNT))
#define MLX5E_PORT_STATS_DEBUG_NUM \
(0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))

12
sys/dev/mlx5/mlx5_en/mlx5_en_main.c
View File

@ -769,6 +769,18 @@ mlx5e_update_pport_counters(struct mlx5e_priv *priv)
for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
s_debug->arg[y] = be64toh(ptr[x]);
/* read Extended Statistical Group */
if (MLX5_CAP_GEN(mdev, pcam_reg) &&
MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
/* read Extended Statistical counter group using predefined counter layout */
MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
s_debug->arg[y] = be64toh(ptr[x]);
}
/* read PCIE counters */
mlx5e_update_pcie_counters(priv);