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Add the machine-specific definitions for configuring the new physical

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memory allocator.

Approved by:	re
This commit is contained in:
Alan Cox 2007-06-03 23:33:11 +00:00
parent 5b4a3e940f
commit c63f556284
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=170254
1 changed files with 38 additions and 0 deletions
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38
sys/sun4v/include/vmparam.h
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@ -82,6 +82,44 @@
*/
#define VM_PHYSSEG_DENSE
/*
* The number of PHYSSEG entries must be one greater than the number
* of phys_avail entries because the phys_avail entry that spans the
* largest physical address that is accessible by ISA DMA is split
* into two PHYSSEG entries.
*/
#define VM_PHYSSEG_MAX 64
/*
* Create two free page pools: VM_FREEPOOL_DEFAULT is the default pool
* from which physical pages are allocated and VM_FREEPOOL_DIRECT is
* the pool from which physical pages for small UMA objects are
* allocated.
*/
#define VM_NFREEPOOL 2
#define VM_FREEPOOL_DEFAULT 0
#define VM_FREEPOOL_DIRECT 1
/*
* Create two free page lists: VM_FREELIST_DEFAULT is for physical
* pages that are above the largest physical address that is
* accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages
* that are below that address.
*/
#define VM_NFREELIST 2
#define VM_FREELIST_DEFAULT 0
#define VM_FREELIST_ISADMA 1
/*
* An allocation size of 16MB is supported in order to optimize the
* use of the direct map by UMA. Specifically, a cache line contains
* at most four TTEs, collectively mapping 16MB of physical memory.
* By reducing the number of distinct 16MB "pages" that are used by UMA,
* the physical memory allocator reduces the likelihood of both 4MB
* page TLB misses and cache misses caused by 4MB page TLB misses.
*/
#define VM_NFREEORDER 12
/*
* Address space layout.
*