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Code Issues Releases Activity

Add missing isa_dmatc() function.

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This may or may not be correct,  Only the pcii driver would notice and
it doesn't support PC98 yet.
This commit is contained in:
Poul-Henning Kamp 2005-02-07 08:19:53 +00:00
parent 37e90a8cc9
commit c81b5b21d3
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=141441
2 changed files with 24 additions and 14 deletions
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19
sys/pc98/cbus/cbus_dma.c
View File

@ -73,22 +73,17 @@
/*
** Register definitions for DMA controller 1 (channels 0..3):
*/
#ifdef PC98
#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */
#define DMA1_STATUS (IO_DMA + 0x10) /* status register */
#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */
#define DMA1_MODE (IO_DMA + 0x16) /* mode register */
#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */
#else
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
#endif
/*
** Register definitions for DMA controller 2 (channels 4..7):
*/
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
@ -559,6 +554,16 @@ isa_dmastatus(int chan)
return(cnt);
}
/*
* Reached terminal count yet ?
*/
int
isa_dmatc(int chan)
{
return(inb(DMA1_STATUS) & (1 << chan));
}
/*
* Stop a DMA transfer currently in progress.
*/

19
sys/pc98/pc98/isa_dma.c
View File

@ -73,22 +73,17 @@
/*
** Register definitions for DMA controller 1 (channels 0..3):
*/
#ifdef PC98
#define DMA1_CHN(c) (IO_DMA + (4*(c))) /* addr reg for channel c */
#define DMA1_STATUS (IO_DMA + 0x10) /* status register */
#define DMA1_SMSK (IO_DMA + 0x14) /* single mask register */
#define DMA1_MODE (IO_DMA + 0x16) /* mode register */
#define DMA1_FFC (IO_DMA + 0x18) /* clear first/last FF */
#else
#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */
#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */
#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */
#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */
#endif
/*
** Register definitions for DMA controller 2 (channels 4..7):
*/
#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */
#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */
#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */
#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */
#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */
@ -559,6 +554,16 @@ isa_dmastatus(int chan)
return(cnt);
}
/*
* Reached terminal count yet ?
*/
int
isa_dmatc(int chan)
{
return(inb(DMA1_STATUS) & (1 << chan));
}
/*
* Stop a DMA transfer currently in progress.
*/