mirror of
https://git.FreeBSD.org/src.git
synced 2024-11-28 08:02:54 +00:00
- Check on target wordsize instead of compile time define if we build on
64-bit PowerPC or 32-bit PowerPC. - Make gdb work on powerpc64, the code for this is obtained from ppc-linux-tdep.c. - Remove non-elf core read functionality. Implement core read functionality similar like other FreeBSD targets. - Set long double limitations.
This commit is contained in:
Andreas Tobler
parent
3501942bbe
commit
c81c8b1a46
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=223082
@ -27,7 +27,9 @@
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#include "target.h"
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#include "breakpoint.h"
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#include "value.h"
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#include "gdb_string.h"
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#include "osabi.h"
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#include "regset.h"
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#include "ppc-tdep.h"
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#include "ppcfbsd-tdep.h"
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@ -80,6 +82,17 @@ ppcfbsd_supply_reg (char *regs, int regno)
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regcache_raw_supply (current_regcache, PC_REGNUM,
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regs + REG_PC_OFFSET);
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}
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static void
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ppcfbsd_supply_gregset (const struct regset *regset,
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struct regcache *regcache,
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int regnum, void *gregs, size_t size)
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{
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ppcfbsd_supply_reg (gregs, -1);
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}
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static struct regset ppcfbsd_gregset = {
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NULL, (void*)ppcfbsd_supply_gregset
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};
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void
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ppcfbsd_fill_reg (char *regs, int regno)
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@ -144,6 +157,20 @@ ppcfbsd_supply_fpreg (char *fpregs, int regno)
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fpregs + FPREG_FPSCR_OFFSET);
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}
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static void
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ppcfbsd_supply_fpregset (const struct regset *regset,
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struct regcache * regcache,
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int regnum, void *fpset, size_t size)
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{
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ppcfbsd_supply_fpreg (fpset, -1);
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}
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static struct regset ppcfbsd_fpregset =
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{
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NULL, (void*)ppcfbsd_supply_fpregset
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};
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void
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ppcfbsd_fill_fpreg (char *fpregs, int regno)
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{
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@ -174,69 +201,285 @@ ppcfbsd_fill_fpreg (char *fpregs, int regno)
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fpregs + FPREG_FPSCR_OFFSET);
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}
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static void
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fetch_core_registers (char *core_reg_sect, unsigned core_reg_size, int which,
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CORE_ADDR ignore)
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/* Return the appropriate register set for the core section identified
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by SECT_NAME and SECT_SIZE. */
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const struct regset *
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ppcfbsd_regset_from_core_section (struct gdbarch *gdbarch,
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const char *sect_name, size_t sect_size)
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{
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char *regs, *fpregs;
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struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
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/* We get everything from one section. */
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if (which != 0)
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return;
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if (strcmp (sect_name, ".reg") == 0 && sect_size >= SIZEOF_STRUCT_REG)
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return &ppcfbsd_gregset;
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regs = core_reg_sect;
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fpregs = core_reg_sect + SIZEOF_STRUCT_REG;
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if (strcmp (sect_name, ".reg2") == 0 && sect_size >= SIZEOF_STRUCT_FPREG)
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return &ppcfbsd_fpregset;
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/* Integer registers. */
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ppcfbsd_supply_reg (regs, -1);
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/* Floating point registers. */
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ppcfbsd_supply_fpreg (fpregs, -1);
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return NULL;
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}
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static void
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fetch_elfcore_registers (char *core_reg_sect, unsigned core_reg_size, int which,
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CORE_ADDR ignore)
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/* Macros for matching instructions. Note that, since all the
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operands are masked off before they're or-ed into the instruction,
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you can use -1 to make masks. */
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#define insn_d(opcd, rts, ra, d) \
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((((opcd) & 0x3f) << 26) \
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| (((rts) & 0x1f) << 21) \
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| (((ra) & 0x1f) << 16) \
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| ((d) & 0xffff))
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#define insn_ds(opcd, rts, ra, d, xo) \
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((((opcd) & 0x3f) << 26) \
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| (((rts) & 0x1f) << 21) \
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| (((ra) & 0x1f) << 16) \
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| ((d) & 0xfffc) \
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| ((xo) & 0x3))
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#define insn_xfx(opcd, rts, spr, xo) \
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((((opcd) & 0x3f) << 26) \
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| (((rts) & 0x1f) << 21) \
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| (((spr) & 0x1f) << 16) \
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| (((spr) & 0x3e0) << 6) \
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| (((xo) & 0x3ff) << 1))
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/* Read a PPC instruction from memory. PPC instructions are always
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big-endian, no matter what endianness the program is running in, so
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we can't use read_memory_integer or one of its friends here. */
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static unsigned int
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read_insn (CORE_ADDR pc)
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{
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switch (which)
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unsigned char buf[4];
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read_memory (pc, buf, 4);
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return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
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}
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/* An instruction to match. */
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struct insn_pattern
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{
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unsigned int mask; /* mask the insn with this... */
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unsigned int data; /* ...and see if it matches this. */
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int optional; /* If non-zero, this insn may be absent. */
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};
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/* Return non-zero if the instructions at PC match the series
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described in PATTERN, or zero otherwise. PATTERN is an array of
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'struct insn_pattern' objects, terminated by an entry whose mask is
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zero.
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When the match is successful, fill INSN[i] with what PATTERN[i]
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matched. If PATTERN[i] is optional, and the instruction wasn't
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present, set INSN[i] to 0 (which is not a valid PPC instruction).
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INSN should have as many elements as PATTERN. Note that, if
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PATTERN contains optional instructions which aren't present in
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memory, then INSN will have holes, so INSN[i] isn't necessarily the
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i'th instruction in memory. */
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static int
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insns_match_pattern (CORE_ADDR pc,
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struct insn_pattern *pattern,
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unsigned int *insn)
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{
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int i;
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for (i = 0; pattern[i].mask; i++)
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{
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case 0: /* Integer registers. */
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if (core_reg_size != SIZEOF_STRUCT_REG)
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warning (_("Wrong size register set in core file."));
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insn[i] = read_insn (pc);
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if ((insn[i] & pattern[i].mask) == pattern[i].data)
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pc += 4;
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else if (pattern[i].optional)
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insn[i] = 0;
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else
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ppcfbsd_supply_reg (core_reg_sect, -1);
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break;
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case 2: /* Floating point registers. */
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if (core_reg_size != SIZEOF_STRUCT_FPREG)
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warning (_("Wrong size FP register set in core file."));
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else
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ppcfbsd_supply_fpreg (core_reg_sect, -1);
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break;
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default:
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/* Don't know what kind of register request this is; just ignore it. */
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break;
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return 0;
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}
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return 1;
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}
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static struct core_fns ppcfbsd_core_fns =
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{
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bfd_target_unknown_flavour, /* core_flavour */
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default_check_format, /* check_format */
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default_core_sniffer, /* core_sniffer */
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fetch_core_registers, /* core_read_registers */
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NULL /* next */
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};
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static struct core_fns ppcfbsd_elfcore_fns =
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/* Return the 'd' field of the d-form instruction INSN, properly
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sign-extended. */
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static CORE_ADDR
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insn_d_field (unsigned int insn)
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{
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bfd_target_elf_flavour, /* core_flavour */
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default_check_format, /* check_format */
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default_core_sniffer, /* core_sniffer */
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fetch_elfcore_registers, /* core_read_registers */
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NULL /* next */
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};
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return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000);
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}
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/* Return the 'ds' field of the ds-form instruction INSN, with the two
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zero bits concatenated at the right, and properly
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sign-extended. */
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static CORE_ADDR
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insn_ds_field (unsigned int insn)
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{
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return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000);
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}
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/* If DESC is the address of a 64-bit PowerPC FreeBSD function
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descriptor, return the descriptor's entry point. */
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static CORE_ADDR
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ppc64_desc_entry_point (CORE_ADDR desc)
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{
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/* The first word of the descriptor is the entry point. */
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return (CORE_ADDR) read_memory_unsigned_integer (desc, 8);
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}
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/* Pattern for the standard linkage function. These are built by
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build_plt_stub in elf64-ppc.c, whose GLINK argument is always
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zero. */
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static struct insn_pattern ppc64_standard_linkage[] =
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{
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/* addis r12, r2, <any> */
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{ insn_d (-1, -1, -1, 0), insn_d (15, 12, 2, 0), 0 },
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/* std r2, 40(r1) */
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{ -1, insn_ds (62, 2, 1, 40, 0), 0 },
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/* ld r11, <any>(r12) */
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{ insn_ds (-1, -1, -1, 0, -1), insn_ds (58, 11, 12, 0, 0), 0 },
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/* addis r12, r12, 1 <optional> */
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{ insn_d (-1, -1, -1, -1), insn_d (15, 12, 2, 1), 1 },
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/* ld r2, <any>(r12) */
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{ insn_ds (-1, -1, -1, 0, -1), insn_ds (58, 2, 12, 0, 0), 0 },
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/* addis r12, r12, 1 <optional> */
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{ insn_d (-1, -1, -1, -1), insn_d (15, 12, 2, 1), 1 },
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/* mtctr r11 */
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{ insn_xfx (-1, -1, -1, -1), insn_xfx (31, 11, 9, 467),
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0 },
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/* ld r11, <any>(r12) */
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{ insn_ds (-1, -1, -1, 0, -1), insn_ds (58, 11, 12, 0, 0), 0 },
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/* bctr */
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{ -1, 0x4e800420, 0 },
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{ 0, 0, 0 }
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};
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#define PPC64_STANDARD_LINKAGE_LEN \
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(sizeof (ppc64_standard_linkage) / sizeof (ppc64_standard_linkage[0]))
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/* When the dynamic linker is doing lazy symbol resolution, the first
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call to a function in another object will go like this:
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- The user's function calls the linkage function:
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100007c4: 4b ff fc d5 bl 10000498
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100007c8: e8 41 00 28 ld r2,40(r1)
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- The linkage function loads the entry point (and other stuff) from
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the function descriptor in the PLT, and jumps to it:
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10000498: 3d 82 00 00 addis r12,r2,0
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1000049c: f8 41 00 28 std r2,40(r1)
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100004a0: e9 6c 80 98 ld r11,-32616(r12)
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100004a4: e8 4c 80 a0 ld r2,-32608(r12)
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100004a8: 7d 69 03 a6 mtctr r11
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100004ac: e9 6c 80 a8 ld r11,-32600(r12)
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100004b0: 4e 80 04 20 bctr
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- But since this is the first time that PLT entry has been used, it
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sends control to its glink entry. That loads the number of the
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PLT entry and jumps to the common glink0 code:
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10000c98: 38 00 00 00 li r0,0
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10000c9c: 4b ff ff dc b 10000c78
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- The common glink0 code then transfers control to the dynamic
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linker's fixup code:
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10000c78: e8 41 00 28 ld r2,40(r1)
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10000c7c: 3d 82 00 00 addis r12,r2,0
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10000c80: e9 6c 80 80 ld r11,-32640(r12)
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10000c84: e8 4c 80 88 ld r2,-32632(r12)
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10000c88: 7d 69 03 a6 mtctr r11
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10000c8c: e9 6c 80 90 ld r11,-32624(r12)
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10000c90: 4e 80 04 20 bctr
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Eventually, this code will figure out how to skip all of this,
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including the dynamic linker. At the moment, we just get through
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the linkage function. */
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/* If the current thread is about to execute a series of instructions
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at PC matching the ppc64_standard_linkage pattern, and INSN is the result
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from that pattern match, return the code address to which the
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standard linkage function will send them. (This doesn't deal with
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dynamic linker lazy symbol resolution stubs.) */
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static CORE_ADDR
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ppc64_standard_linkage_target (CORE_ADDR pc, unsigned int *insn)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
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/* The address of the function descriptor this linkage function
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references. */
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CORE_ADDR desc
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= ((CORE_ADDR) read_register (tdep->ppc_gp0_regnum + 2)
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+ (insn_d_field (insn[0]) << 16)
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+ insn_ds_field (insn[2]));
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/* The first word of the descriptor is the entry point. Return that. */
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return ppc64_desc_entry_point (desc);
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}
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|
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/* Given that we've begun executing a call trampoline at PC, return
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the entry point of the function the trampoline will go to. */
|
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static CORE_ADDR
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ppc64_skip_trampoline_code (CORE_ADDR pc)
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{
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unsigned int ppc64_standard_linkage_insn[PPC64_STANDARD_LINKAGE_LEN];
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if (insns_match_pattern (pc, ppc64_standard_linkage,
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ppc64_standard_linkage_insn))
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return ppc64_standard_linkage_target (pc, ppc64_standard_linkage_insn);
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else
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return 0;
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}
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|
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|
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/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG) on PPC64
|
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GNU/Linux and FreeBSD.
|
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|
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Usually a function pointer's representation is simply the address
|
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of the function. On GNU/Linux on the 64-bit PowerPC however, a
|
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function pointer is represented by a pointer to a TOC entry. This
|
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TOC entry contains three words, the first word is the address of
|
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the function, the second word is the TOC pointer (r2), and the
|
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third word is the static chain value. Throughout GDB it is
|
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currently assumed that a function pointer contains the address of
|
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the function, which is not easy to fix. In addition, the
|
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conversion of a function address to a function pointer would
|
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require allocation of a TOC entry in the inferior's memory space,
|
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with all its drawbacks. To be able to call C++ virtual methods in
|
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the inferior (which are called via function pointers),
|
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find_function_addr uses this function to get the function address
|
||||
from a function pointer. */
|
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|
||||
/* If ADDR points at what is clearly a function descriptor, transform
|
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it into the address of the corresponding function. Be
|
||||
conservative, otherwize GDB will do the transformation on any
|
||||
random addresses such as occures when there is no symbol table. */
|
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|
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static CORE_ADDR
|
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ppc64_fbsd_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
|
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CORE_ADDR addr,
|
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struct target_ops *targ)
|
||||
{
|
||||
struct section_table *s = target_section_by_addr (targ, addr);
|
||||
|
||||
/* Check if ADDR points to a function descriptor. */
|
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if (s && strcmp (s->the_bfd_section->name, ".opd") == 0)
|
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return get_target_memory_unsigned (targ, addr, 8);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static int
|
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ppcfbsd_pc_in_sigtramp (CORE_ADDR pc, char *func_name)
|
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@ -270,27 +513,42 @@ static void
|
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ppcfbsd_init_abi (struct gdbarch_info info,
|
||||
struct gdbarch *gdbarch)
|
||||
{
|
||||
struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
|
||||
|
||||
/* FreeBSD doesn't support the 128-bit `long double' from the psABI. */
|
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set_gdbarch_long_double_bit (gdbarch, 64);
|
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|
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set_gdbarch_pc_in_sigtramp (gdbarch, ppcfbsd_pc_in_sigtramp);
|
||||
/* For NetBSD, this is an on again, off again thing. Some systems
|
||||
do use the broken struct convention, and some don't. */
|
||||
set_gdbarch_return_value (gdbarch, ppcfbsd_return_value);
|
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#ifdef __powerpc64__
|
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
|
||||
svr4_lp64_fetch_link_map_offsets);
|
||||
#else
|
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
|
||||
svr4_ilp32_fetch_link_map_offsets);
|
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#endif
|
||||
|
||||
if (tdep->wordsize == 4)
|
||||
{
|
||||
set_gdbarch_return_value (gdbarch, ppcfbsd_return_value);
|
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
|
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svr4_ilp32_fetch_link_map_offsets);
|
||||
}
|
||||
|
||||
if (tdep->wordsize == 8)
|
||||
{
|
||||
set_gdbarch_convert_from_func_ptr_addr
|
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(gdbarch, ppc64_fbsd_convert_from_func_ptr_addr);
|
||||
|
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set_gdbarch_skip_trampoline_code (gdbarch, ppc64_skip_trampoline_code);
|
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|
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
|
||||
svr4_lp64_fetch_link_map_offsets);
|
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}
|
||||
|
||||
set_gdbarch_regset_from_core_section (gdbarch,
|
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ppcfbsd_regset_from_core_section);
|
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}
|
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|
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void
|
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_initialize_ppcfbsd_tdep (void)
|
||||
{
|
||||
gdbarch_register_osabi (bfd_arch_powerpc, bfd_mach_ppc,
|
||||
GDB_OSABI_FREEBSD_ELF, ppcfbsd_init_abi);
|
||||
gdbarch_register_osabi (bfd_arch_powerpc, bfd_mach_ppc64,
|
||||
GDB_OSABI_FREEBSD_ELF, ppcfbsd_init_abi);
|
||||
gdbarch_register_osabi (bfd_arch_rs6000, 0, GDB_OSABI_FREEBSD_ELF,
|
||||
ppcfbsd_init_abi);
|
||||
gdbarch_register_osabi (bfd_arch_powerpc, 0, GDB_OSABI_FREEBSD_ELF,
|
||||
ppcfbsd_init_abi);
|
||||
|
||||
add_core_fns (&ppcfbsd_core_fns);
|
||||
add_core_fns (&ppcfbsd_elfcore_fns);
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user