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- Add a function ioapic_program_intpin() that completely programs an I/O
APIC interrupt pin based on the settings in the corresponding interrupt source structure. - Use ioapic_program_intpin() in place of manual frobbing of the intpin configuration in ioapic_program_destination() and ioapic_register(). - Use ioapic_program_intpin() to implement suspend/resume support for I/O APICs.
This commit is contained in:
John Baldwin
parent
c7cfc3b129
commit
c9702514c0
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=129964
@ -125,6 +125,7 @@ static int ioapic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
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static void ioapic_suspend(struct intsrc *isrc);
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static void ioapic_resume(struct intsrc *isrc);
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static void ioapic_program_destination(struct ioapic_intsrc *intpin);
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static void ioapic_program_intpin(struct ioapic_intsrc *intpin);
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static void ioapic_setup_mixed_mode(struct ioapic_intsrc *intpin);
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static STAILQ_HEAD(,ioapic) ioapic_list = STAILQ_HEAD_INITIALIZER(ioapic_list);
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@ -134,7 +135,7 @@ struct pic ioapic_template = { ioapic_enable_source, ioapic_disable_source,
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ioapic_suspend, ioapic_resume,
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ioapic_config_intr };
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static int current_cluster, logical_clusters, next_ioapic_base;
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static int bsp_id, current_cluster, logical_clusters, next_ioapic_base;
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static u_int mixed_mode_enabled, next_id, program_logical_dest;
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#ifdef NO_MIXED_MODE
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static int mixed_mode_active = 0;
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@ -206,6 +207,82 @@ ioapic_eoi_source(struct intsrc *isrc)
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lapic_eoi();
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}
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/*
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* Completely program an intpin based on the data in its interrupt source
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* structure.
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*/
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static void
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ioapic_program_intpin(struct ioapic_intsrc *intpin)
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{
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struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
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uint32_t low, high, value;
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/*
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* For pins routed via mixed mode or disabled, just ensure that
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* they are masked.
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*/
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if (intpin->io_dest == DEST_EXTINT ||
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intpin->io_vector == VECTOR_DISABLED) {
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low = ioapic_read(io->io_addr,
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IOAPIC_REDTBL_LO(intpin->io_intpin));
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if ((low & IOART_INTMASK) == IOART_INTMCLR)
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ioapic_write(io->io_addr,
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IOAPIC_REDTBL_LO(intpin->io_intpin),
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low | IOART_INTMSET);
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return;
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}
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/* Set the destination. */
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if (intpin->io_dest == DEST_NONE) {
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low = IOART_DESTPHY;
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high = bsp_id << APIC_ID_SHIFT;
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} else {
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low = IOART_DESTLOG;
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high = (intpin->io_dest << APIC_ID_CLUSTER_SHIFT |
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APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT;
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}
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/* Program the rest of the low word. */
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if (intpin->io_edgetrigger)
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low |= IOART_TRGREDG;
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else
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low |= IOART_TRGRLVL;
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if (intpin->io_activehi)
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low |= IOART_INTAHI;
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else
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low |= IOART_INTALO;
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if (intpin->io_masked)
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low |= IOART_INTMSET;
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switch (intpin->io_vector) {
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case VECTOR_EXTINT:
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KASSERT(intpin->io_edgetrigger,
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("EXTINT not edge triggered"));
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low |= IOART_DELEXINT;
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break;
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case VECTOR_NMI:
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KASSERT(intpin->io_edgetrigger,
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("NMI not edge triggered"));
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low |= IOART_DELNMI;
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break;
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case VECTOR_SMI:
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KASSERT(intpin->io_edgetrigger,
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("SMI not edge triggered"));
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low |= IOART_DELSMI;
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break;
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default:
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low |= IOART_DELLOPRI | apic_irq_to_idt(intpin->io_vector);
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}
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/* Write the values to the APIC. */
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mtx_lock_spin(&icu_lock);
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ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), low);
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value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
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value &= ~IOART_DEST;
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value |= high;
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ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
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mtx_unlock_spin(&icu_lock);
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}
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/*
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* Program an individual intpin's logical destination.
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*/
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@ -213,7 +290,6 @@ static void
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ioapic_program_destination(struct ioapic_intsrc *intpin)
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{
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struct ioapic *io = (struct ioapic *)intpin->io_intsrc.is_pic;
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uint32_t value;
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KASSERT(intpin->io_dest != DEST_NONE,
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("intpin not assigned to a cluster"));
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@ -228,17 +304,7 @@ ioapic_program_destination(struct ioapic_intsrc *intpin)
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printf("IRQ %u", intpin->io_vector);
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printf(") to cluster %u\n", intpin->io_dest);
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}
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mtx_lock_spin(&icu_lock);
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value = ioapic_read(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin));
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value &= ~IOART_DESTMOD;
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value |= IOART_DESTLOG;
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ioapic_write(io->io_addr, IOAPIC_REDTBL_LO(intpin->io_intpin), value);
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value = ioapic_read(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin));
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value &= ~IOART_DEST;
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value |= (intpin->io_dest << APIC_ID_CLUSTER_SHIFT |
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APIC_ID_CLUSTER_ID) << APIC_ID_SHIFT;
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ioapic_write(io->io_addr, IOAPIC_REDTBL_HI(intpin->io_intpin), value);
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mtx_unlock_spin(&icu_lock);
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ioapic_program_intpin(intpin);
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}
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static void
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@ -338,7 +404,7 @@ static void
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ioapic_resume(struct intsrc *isrc)
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{
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TODO;
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ioapic_program_intpin((struct ioapic_intsrc *)isrc);
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}
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/*
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@ -630,6 +696,7 @@ ioapic_register(void *cookie)
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printf("ioapic%u <Version %u.%u> irqs %u-%u on motherboard\n",
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io->io_id, flags >> 4, flags & 0xf, io->io_intbase,
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io->io_intbase + io->io_numintr - 1);
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bsp_id = PCPU_GET(apic_id);
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for (i = 0, pin = io->io_pins; i < io->io_numintr; i++, pin++) {
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/*
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* Finish initializing the pins by programming the vectors
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@ -637,63 +704,18 @@ ioapic_register(void *cookie)
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*/
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if (pin->io_vector == VECTOR_DISABLED)
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continue;
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flags = IOART_DESTPHY;
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if (pin->io_edgetrigger)
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flags |= IOART_TRGREDG;
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else
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flags |= IOART_TRGRLVL;
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if (pin->io_activehi)
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flags |= IOART_INTAHI;
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else
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flags |= IOART_INTALO;
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if (pin->io_masked)
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flags |= IOART_INTMSET;
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switch (pin->io_vector) {
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case VECTOR_EXTINT:
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KASSERT(pin->io_edgetrigger,
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("EXTINT not edge triggered"));
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flags |= IOART_DELEXINT;
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break;
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case VECTOR_NMI:
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KASSERT(pin->io_edgetrigger,
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("NMI not edge triggered"));
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flags |= IOART_DELNMI;
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break;
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case VECTOR_SMI:
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KASSERT(pin->io_edgetrigger,
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("SMI not edge triggered"));
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flags |= IOART_DELSMI;
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break;
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default:
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flags |= IOART_DELLOPRI |
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apic_irq_to_idt(pin->io_vector);
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}
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mtx_lock_spin(&icu_lock);
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ioapic_write(apic, IOAPIC_REDTBL_LO(i), flags);
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ioapic_program_intpin(pin);
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if (pin->io_vector >= NUM_IO_INTS)
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continue;
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/*
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* Route interrupts to the BSP by default using physical
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* addressing. Vectored interrupts get readdressed using
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* logical IDs to CPU clusters when they are enabled.
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* Route IRQ0 via the 8259A using mixed mode if mixed mode
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* is available and turned on.
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*/
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flags = ioapic_read(apic, IOAPIC_REDTBL_HI(i));
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flags &= ~IOART_DEST;
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flags |= PCPU_GET(apic_id) << APIC_ID_SHIFT;
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ioapic_write(apic, IOAPIC_REDTBL_HI(i), flags);
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mtx_unlock_spin(&icu_lock);
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if (pin->io_vector < NUM_IO_INTS) {
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/*
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* Route IRQ0 via the 8259A using mixed mode if
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* mixed mode is available and turned on.
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*/
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if (pin->io_vector == 0 && mixed_mode_active &&
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mixed_mode_enabled)
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ioapic_setup_mixed_mode(pin);
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else
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intr_register_source(&pin->io_intsrc);
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}
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if (pin->io_vector == 0 && mixed_mode_active &&
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mixed_mode_enabled)
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ioapic_setup_mixed_mode(pin);
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else
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intr_register_source(&pin->io_intsrc);
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}
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}
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