mirror of
https://git.FreeBSD.org/src.git
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Driver for OpenPIC compatible interrupt controllers.
It's fairly PowerMac specific at the moment, but that should be fixable.
This commit is contained in:
Benno Rice
parent
bd275d1aed
commit
ca01920852
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=99654
@ -28,6 +28,7 @@ powerpc/powerpc/machdep.c standard
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powerpc/powerpc/nexus.c standard
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powerpc/powerpc/ofwmagic.s standard
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powerpc/powerpc/ofw_machdep.c standard
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powerpc/powerpc/openpic.c standard
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powerpc/powerpc/pic_if.m standard
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powerpc/powerpc/pmap.c standard
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powerpc/powerpc/sigcode.S standard
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@ -23,33 +23,49 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: openpicreg.h,v 1.2 2001/02/05 19:22:23 briggs Exp $
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* from NetBSD: openpicreg.h,v 1.3 2001/08/30 03:08:52 briggs Exp
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* $FreeBSD$
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*/
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/*
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* Size of OpenPIC register space
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*/
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#define OPENPIC_SIZE 0x40000
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/*
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* GLOBAL/TIMER register (IDU base + 0x1000)
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*/
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/* feature reporting reg 0 */
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#define OPENPIC_FEATURE 0x1000
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#define OPENPIC_FEATURE 0x1000
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#define OPENPIC_FEATURE_VERSION_MASK 0x000000ff
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#define OPENPIC_FEATURE_LAST_CPU_MASK 0x00001f00
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#define OPENPIC_FEATURE_LAST_CPU_SHIFT 8
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#define OPENPIC_FEATURE_LAST_IRQ_MASK 0x07ff0000
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#define OPENPIC_FEATURE_LAST_IRQ_SHIFT 16
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/* global config reg 0 */
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#define OPENPIC_CONFIG 0x1020
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#define OPENPIC_CONFIG_RESET 0x80000000
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#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000
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#define OPENPIC_CONFIG 0x1020
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#define OPENPIC_CONFIG_RESET 0x80000000
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#define OPENPIC_CONFIG_8259_PASSTHRU_DISABLE 0x20000000
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/* interrupt configuration mode (direct or serial) */
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#define OPENPIC_ICR 0x1030
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#define OPENPIC_ICR_SERIAL_MODE (1 << 27)
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#define OPENPIC_ICR_SERIAL_RATIO_MASK (0x7 << 28)
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#define OPENPIC_ICR_SERIAL_RATIO_SHIFT 28
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/* vendor ID */
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#define OPENPIC_VENDOR_ID 0x1080
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#define OPENPIC_VENDOR_ID 0x1080
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/* processor initialization reg */
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#define OPENPIC_PROC_INIT 0x1090
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#define OPENPIC_PROC_INIT 0x1090
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/* IPI vector/priority reg */
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#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10)
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#define OPENPIC_IPI_VECTOR(ipi) (0x10a0 + (ipi) * 0x10)
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/* spurious intr. vector */
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#define OPENPIC_SPURIOUS_VECTOR 0x10e0
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#define OPENPIC_SPURIOUS_VECTOR 0x10e0
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/*
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@ -57,22 +73,22 @@
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*/
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/* interrupt vector/priority reg */
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#ifndef OPENPIC_SRC_VECTOR
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#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20)
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#ifndef OPENPIC_SRC_VECTOR
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#define OPENPIC_SRC_VECTOR(irq) (0x10000 + (irq) * 0x20)
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#endif
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#define OPENPIC_SENSE_LEVEL 0x00400000
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#define OPENPIC_SENSE_EDGE 0x00000000
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#define OPENPIC_POLARITY_POSITIVE 0x00800000
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#define OPENPIC_POLARITY_NEGATIVE 0x00000000
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#define OPENPIC_IMASK 0x80000000
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#define OPENPIC_ACTIVITY 0x40000000
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#define OPENPIC_PRIORITY_MASK 0x000f0000
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#define OPENPIC_PRIORITY_SHIFT 16
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#define OPENPIC_VECTOR_MASK 0x000000ff
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#define OPENPIC_SENSE_LEVEL 0x00400000
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#define OPENPIC_SENSE_EDGE 0x00000000
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#define OPENPIC_POLARITY_POSITIVE 0x00800000
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#define OPENPIC_POLARITY_NEGATIVE 0x00000000
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#define OPENPIC_IMASK 0x80000000
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#define OPENPIC_ACTIVITY 0x40000000
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#define OPENPIC_PRIORITY_MASK 0x000f0000
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#define OPENPIC_PRIORITY_SHIFT 16
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#define OPENPIC_VECTOR_MASK 0x000000ff
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/* interrupt destination cpu */
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#ifndef OPENPIC_IDEST
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#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20)
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#ifndef OPENPIC_IDEST
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#define OPENPIC_IDEST(irq) (0x10010 + (irq) * 0x20)
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#endif
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/*
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@ -80,14 +96,14 @@
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*/
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/* IPI command reg */
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#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi))
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#define OPENPIC_IPI(cpu, ipi) (0x20040 + (cpu) * 0x1000 + (ipi))
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/* current task priority reg */
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#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000)
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#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f
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#define OPENPIC_CPU_PRIORITY(cpu) (0x20080 + (cpu) * 0x1000)
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#define OPENPIC_CPU_PRIORITY_MASK 0x0000000f
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/* interrupt acknowledge reg */
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#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000)
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#define OPENPIC_IACK(cpu) (0x200a0 + (cpu) * 0x1000)
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/* end of interrupt reg */
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#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000)
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#define OPENPIC_EOI(cpu) (0x200b0 + (cpu) * 0x1000)
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39
sys/powerpc/include/openpicvar.h
Normal file
39
sys/powerpc/include/openpicvar.h
Normal file
@ -0,0 +1,39 @@
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/*
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* Copyright (C) 2002 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_OPENPICVAR_H_
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#define _POWERPC_OPENPICVAR_H_
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struct openpic_softc {
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vm_offset_t sc_base;
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char *sc_version;
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u_int sc_ncpu;
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u_int sc_nirq;
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struct rman sc_rman;
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};
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#endif /* _POWERPC_OPENPICVAR_H_ */
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465
sys/powerpc/powerpc/openpic.c
Normal file
465
sys/powerpc/powerpc/openpic.c
Normal file
@ -0,0 +1,465 @@
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/*
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* Copyright (C) 2002 Benno Rice.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofw_pci2.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/nexusvar.h>
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#include <machine/pio.h>
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#include <machine/resource.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <sys/rman.h>
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#include <machine/openpicreg.h>
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#include <machine/openpicvar.h>
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#include "pic_if.h"
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/*
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* Device interface.
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*/
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static int openpic_probe(device_t);
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static int openpic_attach(device_t);
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/*
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* PIC interface.
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*/
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static struct resource *openpic_allocate_intr(device_t, device_t, int *,
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u_long, u_int);
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static int openpic_setup_intr(device_t, device_t,
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struct resource *, int, driver_intr_t, void *,
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void **);
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static int openpic_teardown_intr(device_t, device_t,
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struct resource *, void *);
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static int openpic_release_intr(device_t dev, device_t, int,
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struct resource *res);
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/*
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* Local routines
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*/
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static u_int openpic_read(struct openpic_softc *, int);
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static void openpic_write(struct openpic_softc *, int, u_int);
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static int openpic_read_irq(struct openpic_softc *, int);
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static void openpic_eoi(struct openpic_softc *, int);
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static void openpic_enable_irq(struct openpic_softc *, int, int);
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static void openpic_disable_irq(struct openpic_softc *, int);
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static void openpic_set_priority(struct openpic_softc *, int, int);
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static void openpic_intr(void);
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static void irq_enable(int);
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static void irq_disable(int);
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/*
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* Driver methods.
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*/
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static device_method_t openpic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, openpic_probe),
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DEVMETHOD(device_attach, openpic_attach),
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/* PIC interface */
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DEVMETHOD(pic_allocate_intr, openpic_allocate_intr),
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DEVMETHOD(pic_setup_intr, openpic_setup_intr),
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DEVMETHOD(pic_teardown_intr, openpic_teardown_intr),
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DEVMETHOD(pic_release_intr, openpic_release_intr),
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{ 0, 0 }
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};
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static driver_t openpic_driver = {
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"openpic",
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openpic_methods,
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sizeof(struct openpic_softc)
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};
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static devclass_t openpic_devclass;
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DRIVER_MODULE(openpic, nexus, openpic_driver, openpic_devclass, 0, 0);
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static struct openpic_softc *softc; /* XXX This limits us to one openpic */
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/*
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* Device interface
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*/
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static int
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openpic_probe(device_t dev)
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{
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struct openpic_softc *sc;
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phandle_t node, parent;
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char *type;
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u_int32_t reg[5], val;
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vm_offset_t macio_base;
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sc = device_get_softc(dev);
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node = nexus_get_node(dev);
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type = nexus_get_device_type(dev);
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if (type == NULL)
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return (ENXIO);
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if (strcmp(type, "open-pic") != 0)
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return (ENXIO);
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parent = OF_parent(node);
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if (OF_getprop(parent, "assigned-addresses", reg, sizeof(reg)) < 20)
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return (ENXIO);
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macio_base = (vm_offset_t)reg[2];
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if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
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return (ENXIO);
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sc->sc_base = (vm_offset_t)pmap_mapdev(macio_base + reg[0],
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OPENPIC_SIZE);
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val = openpic_read(sc, OPENPIC_FEATURE);
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switch (val & OPENPIC_FEATURE_VERSION_MASK) {
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case 1:
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sc->sc_version = "1.0";
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break;
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case 2:
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sc->sc_version = "1.2";
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break;
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case 3:
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sc->sc_version = "1.3";
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break;
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default:
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sc->sc_version = "unknown";
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break;
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}
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sc->sc_ncpu = ((val & OPENPIC_FEATURE_LAST_CPU_MASK) >>
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OPENPIC_FEATURE_LAST_CPU_SHIFT) + 1;
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sc->sc_nirq = ((val & OPENPIC_FEATURE_LAST_IRQ_MASK) >>
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OPENPIC_FEATURE_LAST_IRQ_SHIFT) + 1;
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device_set_desc(dev, "OpenPIC interrupt controller");
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return (0);
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}
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static int
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openpic_attach(device_t dev)
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{
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struct openpic_softc *sc;
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u_int32_t irq, x;
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sc = device_get_softc(dev);
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softc = sc;
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device_printf(dev,
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"Version %s, supports up to %d CPUs and up to %d irqs\n",
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sc->sc_version, sc->sc_ncpu, sc->sc_nirq);
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sc->sc_rman.rm_type = RMAN_ARRAY;
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sc->sc_rman.rm_descr = device_get_nameunit(dev);
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if (rman_init(&sc->sc_rman) != 0 ||
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rman_manage_region(&sc->sc_rman, 0, sc->sc_nirq - 1) != 0) {
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device_printf(dev, "could not set up resource management");
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return (ENXIO);
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}
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/* disable all interrupts */
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for (irq = 0; irq < 256; irq++)
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openpic_write(sc, OPENPIC_SRC_VECTOR(irq), OPENPIC_IMASK);
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openpic_set_priority(sc, 0, 15);
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/* we don't need 8259 passthrough mode */
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x = openpic_read(sc, OPENPIC_CONFIG);
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x |= OPENPIC_CONFIG_8259_PASSTHRU_DISABLE;
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openpic_write(sc, OPENPIC_CONFIG, x);
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/* send all interrupts to cpu 0 */
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for (irq = 0; irq < sc->sc_nirq; irq++)
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openpic_write(sc, OPENPIC_IDEST(irq), 1 << 0);
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for (irq = 0; irq < sc->sc_nirq; irq++) {
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x = irq;
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x |= OPENPIC_IMASK;
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x |= OPENPIC_POLARITY_POSITIVE;
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x |= OPENPIC_SENSE_LEVEL;
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x |= 8 << OPENPIC_PRIORITY_SHIFT;
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openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
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}
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/* XXX IPI */
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/* XXX set spurious intr vector */
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openpic_set_priority(sc, 0, 0);
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/* clear all pending interrupts */
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for (irq = 0; irq < 256; irq++) {
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openpic_read_irq(sc, 0);
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openpic_eoi(sc, 0);
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}
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for (irq = 0; irq < sc->sc_nirq; irq++)
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openpic_disable_irq(sc, irq);
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intr_init(openpic_intr, sc->sc_nirq, irq_enable, irq_disable);
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return (0);
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}
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/*
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* PIC interface
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*/
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static struct resource *
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openpic_allocate_intr(device_t dev, device_t child, int *rid, u_long intr,
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u_int flags)
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{
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struct openpic_softc *sc;
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struct resource *rv;
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int needactivate;
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sc = device_get_softc(dev);
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needactivate = flags & RF_ACTIVE;
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flags &= ~RF_ACTIVE;
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rv = rman_reserve_resource(&sc->sc_rman, intr, intr, 1, flags, child);
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if (rv == NULL) {
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device_printf(dev, "interrupt reservation failed for %s\n",
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device_get_nameunit(child));
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return (NULL);
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}
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if (needactivate) {
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if (bus_activate_resource(child, SYS_RES_IRQ, *rid, rv) != 0) {
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device_printf(dev,
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"resource activation failed for %s\n",
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device_get_nameunit(child));
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||||
rman_release_resource(rv);
|
||||
return (NULL);
|
||||
}
|
||||
}
|
||||
|
||||
return (rv);
|
||||
}
|
||||
|
||||
static int
|
||||
openpic_setup_intr(device_t dev, device_t child, struct resource *res,
|
||||
int flags, driver_intr_t *intr, void *arg, void **cookiep)
|
||||
{
|
||||
struct openpic_softc *sc;
|
||||
int error;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
if (res == NULL) {
|
||||
device_printf(dev, "null interrupt resource from %s\n",
|
||||
device_get_nameunit(child));
|
||||
return (EINVAL);
|
||||
}
|
||||
|
||||
if ((res->r_flags & RF_SHAREABLE) == 0)
|
||||
flags |= INTR_EXCL;
|
||||
|
||||
/*
|
||||
* We depend here on rman_activate_resource() being idempotent.
|
||||
*/
|
||||
error = rman_activate_resource(res);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
error = inthand_add(device_get_nameunit(child), res->r_start, intr,
|
||||
arg, flags, cookiep);
|
||||
openpic_enable_irq(sc, res->r_start, IST_LEVEL);
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
openpic_teardown_intr(device_t dev, device_t child, struct resource *res,
|
||||
void *ih)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = rman_deactivate_resource(res);
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
error = inthand_remove(res->r_start, ih);
|
||||
|
||||
return (error);
|
||||
}
|
||||
|
||||
static int
|
||||
openpic_release_intr(device_t dev, device_t child, int rid,
|
||||
struct resource *res)
|
||||
{
|
||||
int error;
|
||||
|
||||
if (rman_get_flags(res) & RF_ACTIVE) {
|
||||
error = bus_deactivate_resource(child, SYS_RES_IRQ, rid, res);
|
||||
if (error)
|
||||
return (error);
|
||||
}
|
||||
|
||||
return (rman_release_resource(res));
|
||||
}
|
||||
|
||||
/*
|
||||
* Local routines
|
||||
*/
|
||||
|
||||
static u_int
|
||||
openpic_read(struct openpic_softc *sc, int reg)
|
||||
{
|
||||
volatile unsigned char *addr;
|
||||
|
||||
addr = (unsigned char *)sc->sc_base + reg;
|
||||
#if 0
|
||||
printf("openpic: reading from %p (0x%08x + 0x%08x)\n", addr,
|
||||
sc->sc_base, reg);
|
||||
#endif
|
||||
|
||||
return in32rb(addr);
|
||||
}
|
||||
|
||||
static void
|
||||
openpic_write(struct openpic_softc *sc, int reg, u_int val)
|
||||
{
|
||||
volatile unsigned char *addr;
|
||||
|
||||
addr = (unsigned char *)sc->sc_base + reg;
|
||||
#if 0
|
||||
printf("openpic: writing to %p (0x%08x + 0x%08x)\n", addr, sc->sc_base,
|
||||
reg);
|
||||
#endif
|
||||
|
||||
out32rb(addr, val);
|
||||
}
|
||||
|
||||
static int
|
||||
openpic_read_irq(struct openpic_softc *sc, int cpu)
|
||||
{
|
||||
return openpic_read(sc, OPENPIC_IACK(cpu)) & OPENPIC_VECTOR_MASK;
|
||||
}
|
||||
|
||||
static void
|
||||
openpic_eoi(struct openpic_softc *sc, int cpu)
|
||||
{
|
||||
openpic_write(sc, OPENPIC_EOI(cpu), 0);
|
||||
openpic_read(sc, OPENPIC_EOI(cpu));
|
||||
}
|
||||
|
||||
static void
|
||||
openpic_enable_irq(struct openpic_softc *sc, int irq, int type)
|
||||
{
|
||||
u_int x;
|
||||
|
||||
x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
|
||||
x &= ~(OPENPIC_IMASK | OPENPIC_SENSE_LEVEL | OPENPIC_SENSE_EDGE);
|
||||
if (type == IST_LEVEL)
|
||||
x |= OPENPIC_SENSE_LEVEL;
|
||||
else
|
||||
x |= OPENPIC_SENSE_EDGE;
|
||||
openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
|
||||
}
|
||||
|
||||
static void
|
||||
openpic_disable_irq(struct openpic_softc *sc, int irq)
|
||||
{
|
||||
u_int x;
|
||||
|
||||
x = openpic_read(sc, OPENPIC_SRC_VECTOR(irq));
|
||||
x |= OPENPIC_IMASK;
|
||||
openpic_write(sc, OPENPIC_SRC_VECTOR(irq), x);
|
||||
}
|
||||
|
||||
static void
|
||||
openpic_set_priority(struct openpic_softc *sc, int cpu, int pri)
|
||||
{
|
||||
u_int x;
|
||||
|
||||
x = openpic_read(sc, OPENPIC_CPU_PRIORITY(cpu));
|
||||
x &= ~OPENPIC_CPU_PRIORITY_MASK;
|
||||
x |= pri;
|
||||
openpic_write(sc, OPENPIC_CPU_PRIORITY(cpu), x);
|
||||
}
|
||||
|
||||
static void
|
||||
openpic_intr(void)
|
||||
{
|
||||
int irq;
|
||||
u_int32_t msr;
|
||||
|
||||
msr = mfmsr();
|
||||
|
||||
irq = openpic_read_irq(softc, 0);
|
||||
if (irq == 255) {
|
||||
return;
|
||||
}
|
||||
|
||||
start:
|
||||
openpic_disable_irq(softc, irq);
|
||||
mtmsr(msr | PSL_EE);
|
||||
|
||||
/* do the interrupt thang */
|
||||
intr_handle(irq);
|
||||
|
||||
mtmsr(msr);
|
||||
|
||||
openpic_eoi(softc, 0);
|
||||
|
||||
irq = openpic_read_irq(softc, 0);
|
||||
if (irq != 255)
|
||||
goto start;
|
||||
}
|
||||
|
||||
static void
|
||||
irq_enable(int irq)
|
||||
{
|
||||
|
||||
openpic_enable_irq(softc, irq, IST_LEVEL);
|
||||
}
|
||||
|
||||
static void
|
||||
irq_disable(int irq)
|
||||
{
|
||||
|
||||
openpic_disable_irq(softc, irq);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user