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Use convenience macro for minimum and maximum value capping when
re-arming the watchdog timeout. Sponsored by: Sandvine Incorporated Submitted by: Mark Johnston <mjohnston at sandvine dot com> Reviewed by: des MFC after: 10 days
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=216298
@ -288,30 +288,23 @@ static __inline void
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ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
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{
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/*
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* If the datasheets are to be believed, the minimum value
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* actually varies from chipset to chipset - 4 for ICH5 and 2 for
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* all other chipsets. I suspect this is a bug in the ICH5
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* datasheet and that the minimum is uniformly 2, but I'd rather
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* err on the side of caution.
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*/
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if (timeout < 4)
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timeout = 4;
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if (timeout < TCO_RLD_TMR_MIN)
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timeout = TCO_RLD_TMR_MIN;
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if (sc->ich_version <= 5) {
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uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
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tmr_val8 &= 0xc0;
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if (timeout > 0x3f)
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timeout = 0x3f;
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tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
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if (timeout > TCO_RLD1_TMR_MAX)
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timeout = TCO_RLD1_TMR_MAX;
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tmr_val8 |= timeout;
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ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
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} else {
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uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
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tmr_val16 &= 0xfc00;
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if (timeout > 0x03ff)
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timeout = 0x03ff;
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tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff);
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if (timeout > TCO_RLD2_TMR_MAX)
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timeout = TCO_RLD2_TMR_MAX;
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tmr_val16 |= timeout;
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ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
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}
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@ -199,6 +199,17 @@ struct ichwd_softc {
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#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */
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#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */
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/*
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* Masks for the TCO timer value field in TCO_RLD.
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* If the datasheets are to be believed, the minimum value actually varies
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* from chipset to chipset - 4 for ICH5 and 2 for all other chipsets.
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* I suspect this is a bug in the ICH5 datasheet and that the minimum is
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* uniformly 2, but I'd rather err on the side of caution.
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*/
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#define TCO_RLD_TMR_MIN 0x0004
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#define TCO_RLD1_TMR_MAX 0x003f
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#define TCO_RLD2_TMR_MAX 0x03ff
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/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */
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#define ICHWD_TICK 600000000
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