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https://git.FreeBSD.org/src.git
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Add support for selectively enabling LLVM targets
This makes it possible, through src.conf(5) settings, to select which LLVM targets you want to build during buildworld. The current list is: * (WITH|WITHOUT)_LLVM_TARGET_AARCH64 * (WITH|WITHOUT)_LLVM_TARGET_ARM * (WITH|WITHOUT)_LLVM_TARGET_MIPS * (WITH|WITHOUT)_LLVM_TARGET_POWERPC * (WITH|WITHOUT)_LLVM_TARGET_SPARC * (WITH|WITHOUT)_LLVM_TARGET_X86 To not influence anything right now, all of these are on by default, in situations where clang is enabled. Selectively turning a few targets off manually should work. Turning on only one target should work too, even if that target does not correspond to the build architecture. (In that case, LLVM_NATIVE_ARCH will not be defined, and you can only use the resulting clang executable for cross-compiling.) I performed a few measurements on one of the FreeBSD.org reference machines, building clang from scratch, with all targets enabled, and with only the x86 target enabled. The latter was ~12% faster in real time (on a 32-core box), and ~14% faster in user time. For a full buildworld the difference will probably be less pronounced, though. Reviewed by: bdrewery MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D11077
This commit is contained in:
Dimitry Andric
parent
7e8db78116
commit
cbafd2630b
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=335558
@ -4,11 +4,23 @@
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# error Please define the macro LLVM_ASM_PARSER(TargetName)
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#endif
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#ifdef LLVM_TARGET_ENABLE_AARCH64
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LLVM_ASM_PARSER(AArch64)
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#endif
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#ifdef LLVM_TARGET_ENABLE_ARM
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LLVM_ASM_PARSER(ARM)
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#endif
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#ifdef LLVM_TARGET_ENABLE_MIPS
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LLVM_ASM_PARSER(Mips)
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#endif
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#ifdef LLVM_TARGET_ENABLE_POWERPC
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LLVM_ASM_PARSER(PowerPC)
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#endif
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#ifdef LLVM_TARGET_ENABLE_SPARC
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LLVM_ASM_PARSER(Sparc)
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#endif
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#ifdef LLVM_TARGET_ENABLE_X86
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LLVM_ASM_PARSER(X86)
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#endif
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#undef LLVM_ASM_PARSER
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@ -4,11 +4,23 @@
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# error Please define the macro LLVM_ASM_PRINTER(TargetName)
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#endif
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#ifdef LLVM_TARGET_ENABLE_AARCH64
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LLVM_ASM_PRINTER(AArch64)
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#endif
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#ifdef LLVM_TARGET_ENABLE_ARM
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LLVM_ASM_PRINTER(ARM)
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#endif
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#ifdef LLVM_TARGET_ENABLE_MIPS
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LLVM_ASM_PRINTER(Mips)
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#endif
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#ifdef LLVM_TARGET_ENABLE_POWERPC
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LLVM_ASM_PRINTER(PowerPC)
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#endif
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#ifdef LLVM_TARGET_ENABLE_SPARC
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LLVM_ASM_PRINTER(Sparc)
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#endif
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#ifdef LLVM_TARGET_ENABLE_X86
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LLVM_ASM_PRINTER(X86)
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#endif
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#undef LLVM_ASM_PRINTER
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@ -4,11 +4,23 @@
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# error Please define the macro LLVM_DISASSEMBLER(TargetName)
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#endif
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#ifdef LLVM_TARGET_ENABLE_AARCH64
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LLVM_DISASSEMBLER(AArch64)
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#endif
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#ifdef LLVM_TARGET_ENABLE_ARM
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LLVM_DISASSEMBLER(ARM)
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#endif
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#ifdef LLVM_TARGET_ENABLE_MIPS
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LLVM_DISASSEMBLER(Mips)
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#endif
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#ifdef LLVM_TARGET_ENABLE_POWERPC
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LLVM_DISASSEMBLER(PowerPC)
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#endif
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#ifdef LLVM_TARGET_ENABLE_SPARC
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LLVM_DISASSEMBLER(Sparc)
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#endif
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#ifdef LLVM_TARGET_ENABLE_X86
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LLVM_DISASSEMBLER(X86)
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#endif
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#undef LLVM_DISASSEMBLER
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@ -4,11 +4,23 @@
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# error Please define the macro LLVM_TARGET(TargetName)
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#endif
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#ifdef LLVM_TARGET_ENABLE_AARCH64
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LLVM_TARGET(AArch64)
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#endif
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#ifdef LLVM_TARGET_ENABLE_ARM
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LLVM_TARGET(ARM)
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#endif
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#ifdef LLVM_TARGET_ENABLE_MIPS
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LLVM_TARGET(Mips)
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#endif
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#ifdef LLVM_TARGET_ENABLE_POWERPC
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LLVM_TARGET(PowerPC)
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#endif
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#ifdef LLVM_TARGET_ENABLE_SPARC
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LLVM_TARGET(Sparc)
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#endif
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#ifdef LLVM_TARGET_ENABLE_X86
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LLVM_TARGET(X86)
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#endif
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#undef LLVM_TARGET
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@ -34,25 +34,25 @@
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/* #undef LLVM_HOST_TRIPLE */
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/* LLVM architecture name for the native architecture, if available */
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#define LLVM_NATIVE_ARCH X86
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/* #undef LLVM_NATIVE_ARCH */
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/* LLVM name for the native AsmParser init function, if available */
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#define LLVM_NATIVE_ASMPARSER LLVMInitializeX86AsmParser
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/* #undef LLVM_NATIVE_ASMPARSER */
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/* LLVM name for the native AsmPrinter init function, if available */
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#define LLVM_NATIVE_ASMPRINTER LLVMInitializeX86AsmPrinter
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/* #undef LLVM_NATIVE_ASMPRINTER */
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/* LLVM name for the native Disassembler init function, if available */
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#define LLVM_NATIVE_DISASSEMBLER LLVMInitializeX86Disassembler
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/* #undef LLVM_NATIVE_DISASSEMBLER */
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/* LLVM name for the native Target init function, if available */
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#define LLVM_NATIVE_TARGET LLVMInitializeX86Target
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/* #undef LLVM_NATIVE_TARGET */
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/* LLVM name for the native TargetInfo init function, if available */
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#define LLVM_NATIVE_TARGETINFO LLVMInitializeX86TargetInfo
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/* #undef LLVM_NATIVE_TARGETINFO */
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/* LLVM name for the native target MC init function, if available */
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#define LLVM_NATIVE_TARGETMC LLVMInitializeX86TargetMC
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/* #undef LLVM_NATIVE_TARGETMC */
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/* Define if this is Unixish platform */
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#define LLVM_ON_UNIX 1
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@ -7,8 +7,19 @@ LIB= llvm
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INTERNALLIB=
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CFLAGS+= -I${.OBJDIR}
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.if ${MK_LLVM_TARGET_AARCH64} == "no" && ${MK_LLVM_TARGET_ARM} == "no" && \
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${MK_LLVM_TARGET_MIPS} == "no" && ${MK_LLVM_TARGET_POWERPC} == "no" && \
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${MK_LLVM_TARGET_SPARC} == "no" && ${MK_LLVM_TARGET_X86} == "no"
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.error Please enable at least one of: MK_LLVM_TARGET_AARCH64,\
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MK_LLVM_TARGET_ARM, MK_LLVM_TARGET_MIPS, MK_LLVM_TARGET_POWERPC,\
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MK_LLVM_TARGET_SPARC, or MK_LLVM_TARGET_X86
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.endif
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.for arch in AArch64 ARM Mips PowerPC Sparc X86
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. if ${MK_LLVM_TARGET_${arch:tu}} != "no"
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CFLAGS+= -I${LLVM_SRCS}/lib/Target/${arch}
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. endif
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.endfor
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SRCDIR= lib
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@ -784,6 +795,7 @@ SRCS_MIN+= TableGen/StringMatcher.cpp
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SRCS_MIN+= TableGen/TGLexer.cpp
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SRCS_MIN+= TableGen/TGParser.cpp
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SRCS_MIN+= TableGen/TableGenBackend.cpp
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.if ${MK_LLVM_TARGET_AARCH64} != "no"
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SRCS_MIN+= Target/AArch64/AArch64A53Fix835769.cpp
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SRCS_MIN+= Target/AArch64/AArch64A57FPLoadBalancing.cpp
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SRCS_MIN+= Target/AArch64/AArch64AdvSIMDScalarPass.cpp
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@ -836,6 +848,8 @@ SRCS_MIN+= Target/AArch64/MCTargetDesc/AArch64WinCOFFObjectWriter.cpp
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SRCS_MIN+= Target/AArch64/MCTargetDesc/AArch64WinCOFFStreamer.cpp
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SRCS_MIN+= Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
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SRCS_MIN+= Target/AArch64/Utils/AArch64BaseInfo.cpp
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.endif # MK_LLVM_TARGET_AARCH64
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.if ${MK_LLVM_TARGET_ARM} != "no"
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SRCS_MIN+= Target/ARM/A15SDOptimizer.cpp
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SRCS_MIN+= Target/ARM/ARMAsmPrinter.cpp
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SRCS_MIN+= Target/ARM/ARMBaseInstrInfo.cpp
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@ -890,6 +904,8 @@ SRCS_MIN+= Target/ARM/Thumb2InstrInfo.cpp
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SRCS_MIN+= Target/ARM/Thumb2SizeReduction.cpp
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SRCS_MIN+= Target/ARM/ThumbRegisterInfo.cpp
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SRCS_MIN+= Target/ARM/Utils/ARMBaseInfo.cpp
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.endif # MK_LLVM_TARGET_ARM
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.if ${MK_LLVM_TARGET_MIPS} != "no"
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SRCS_MIN+= Target/Mips/AsmParser/MipsAsmParser.cpp
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SRCS_XDW+= Target/Mips/Disassembler/MipsDisassembler.cpp
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SRCS_MIN+= Target/Mips/InstPrinter/MipsInstPrinter.cpp
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@ -940,6 +956,8 @@ SRCS_MIN+= Target/Mips/MipsSubtarget.cpp
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SRCS_MIN+= Target/Mips/MipsTargetMachine.cpp
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SRCS_MIN+= Target/Mips/MipsTargetObjectFile.cpp
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SRCS_MIN+= Target/Mips/TargetInfo/MipsTargetInfo.cpp
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.endif # MK_LLVM_TARGET_MIPS
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.if ${MK_LLVM_TARGET_POWERPC} != "no"
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SRCS_MIN+= Target/PowerPC/AsmParser/PPCAsmParser.cpp
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SRCS_MIN+= Target/PowerPC/Disassembler/PPCDisassembler.cpp
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SRCS_MIN+= Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
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@ -983,6 +1001,8 @@ SRCS_MIN+= Target/PowerPC/PPCVSXCopy.cpp
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SRCS_MIN+= Target/PowerPC/PPCVSXFMAMutate.cpp
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SRCS_MIN+= Target/PowerPC/PPCVSXSwapRemoval.cpp
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SRCS_MIN+= Target/PowerPC/TargetInfo/PowerPCTargetInfo.cpp
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.endif # MK_LLVM_TARGET_POWERPC
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.if ${MK_LLVM_TARGET_SPARC} != "no"
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SRCS_MIN+= Target/Sparc/AsmParser/SparcAsmParser.cpp
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SRCS_MIN+= Target/Sparc/DelaySlotFiller.cpp
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SRCS_XDW+= Target/Sparc/Disassembler/SparcDisassembler.cpp
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@ -1007,11 +1027,13 @@ SRCS_MIN+= Target/Sparc/SparcSubtarget.cpp
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SRCS_MIN+= Target/Sparc/SparcTargetMachine.cpp
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SRCS_MIN+= Target/Sparc/SparcTargetObjectFile.cpp
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SRCS_MIN+= Target/Sparc/TargetInfo/SparcTargetInfo.cpp
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.endif # MK_LLVM_TARGET_SPARC
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SRCS_MIN+= Target/Target.cpp
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SRCS_MIN+= Target/TargetIntrinsicInfo.cpp
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SRCS_MIN+= Target/TargetLoweringObjectFile.cpp
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SRCS_MIN+= Target/TargetMachine.cpp
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SRCS_MIN+= Target/TargetMachineC.cpp
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.if ${MK_LLVM_TARGET_X86} != "no"
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SRCS_MIN+= Target/X86/AsmParser/X86AsmInstrumentation.cpp
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SRCS_MIN+= Target/X86/AsmParser/X86AsmParser.cpp
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SRCS_XDW+= Target/X86/Disassembler/X86Disassembler.cpp
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@ -1069,6 +1091,7 @@ SRCS_MIN+= Target/X86/X86TargetTransformInfo.cpp
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SRCS_MIN+= Target/X86/X86VZeroUpper.cpp
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SRCS_MIN+= Target/X86/X86WinAllocaExpander.cpp
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SRCS_MIN+= Target/X86/X86WinEHState.cpp
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.endif # MK_LLVM_TARGET_X86
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SRCS_EXT+= ToolDrivers/llvm-dlltool/DlltoolDriver.cpp
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SRCS_EXL+= ToolDrivers/llvm-lib/LibDriver.cpp
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SRCS_MIN+= Transforms/Coroutines/CoroCleanup.cpp
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@ -1375,6 +1398,7 @@ ${arch:T}Gen${hdr:H}.inc: ${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}.td
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${LLVM_SRCS}/lib/Target/${arch:H}/${arch:T}.td
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. endfor
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.endfor
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.if ${MK_LLVM_TARGET_AARCH64} != "no"
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TGHDRS+= AArch64GenAsmMatcher.inc
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TGHDRS+= AArch64GenAsmWriter.inc
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TGHDRS+= AArch64GenAsmWriter1.inc
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@ -1390,6 +1414,8 @@ TGHDRS+= AArch64GenRegisterBank.inc
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TGHDRS+= AArch64GenRegisterInfo.inc
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TGHDRS+= AArch64GenSubtargetInfo.inc
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TGHDRS+= AArch64GenSystemOperands.inc
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.endif # MK_LLVM_TARGET_AARCH64
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.if ${MK_LLVM_TARGET_ARM} != "no"
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TGHDRS+= ARMGenAsmMatcher.inc
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TGHDRS+= ARMGenAsmWriter.inc
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TGHDRS+= ARMGenCallingConv.inc
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@ -1404,6 +1430,8 @@ TGHDRS+= ARMGenRegisterBank.inc
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TGHDRS+= ARMGenRegisterInfo.inc
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TGHDRS+= ARMGenSubtargetInfo.inc
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TGHDRS+= ARMGenSystemRegister.inc
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.endif # MK_LLVM_TARGET_ARM
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.if ${MK_LLVM_TARGET_MIPS} != "no"
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TGHDRS+= MipsGenAsmMatcher.inc
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TGHDRS+= MipsGenAsmWriter.inc
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TGHDRS+= MipsGenCallingConv.inc
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@ -1415,6 +1443,8 @@ TGHDRS+= MipsGenMCCodeEmitter.inc
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TGHDRS+= MipsGenMCPseudoLowering.inc
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TGHDRS+= MipsGenRegisterInfo.inc
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TGHDRS+= MipsGenSubtargetInfo.inc
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.endif # MK_LLVM_TARGET_MIPS
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.if ${MK_LLVM_TARGET_POWERPC} != "no"
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TGHDRS+= PPCGenAsmMatcher.inc
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TGHDRS+= PPCGenAsmWriter.inc
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TGHDRS+= PPCGenCallingConv.inc
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@ -1425,6 +1455,8 @@ TGHDRS+= PPCGenInstrInfo.inc
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TGHDRS+= PPCGenMCCodeEmitter.inc
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TGHDRS+= PPCGenRegisterInfo.inc
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TGHDRS+= PPCGenSubtargetInfo.inc
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.endif # MK_LLVM_TARGET_POWERPC
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.if ${MK_LLVM_TARGET_SPARC} != "no"
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TGHDRS+= SparcGenAsmMatcher.inc
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TGHDRS+= SparcGenAsmWriter.inc
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TGHDRS+= SparcGenCallingConv.inc
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@ -1434,6 +1466,8 @@ TGHDRS+= SparcGenInstrInfo.inc
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TGHDRS+= SparcGenMCCodeEmitter.inc
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TGHDRS+= SparcGenRegisterInfo.inc
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TGHDRS+= SparcGenSubtargetInfo.inc
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.endif # MK_LLVM_TARGET_SPARC
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.if ${MK_LLVM_TARGET_X86} != "no"
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TGHDRS+= X86GenAsmMatcher.inc
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TGHDRS+= X86GenAsmWriter.inc
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TGHDRS+= X86GenAsmWriter1.inc
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@ -1447,6 +1481,7 @@ TGHDRS+= X86GenInstrInfo.inc
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TGHDRS+= X86GenRegisterBank.inc
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TGHDRS+= X86GenRegisterInfo.inc
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TGHDRS+= X86GenSubtargetInfo.inc
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.endif # MK_LLVM_TARGET_X86
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DEPENDFILES+= ${TGHDRS:C/$/.d/}
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DPSRCS+= ${TGHDRS}
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@ -1,5 +1,7 @@
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# $FreeBSD$
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.include <src.opts.mk>
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.ifndef LLVM_SRCS
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.error Please define LLVM_SRCS before including this file
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.endif
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@ -40,6 +42,52 @@ CFLAGS+= -DLLVM_DEFAULT_TARGET_TRIPLE=\"${LLVM_TARGET_TRIPLE}\"
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CFLAGS+= -DLLVM_HOST_TRIPLE=\"${LLVM_BUILD_TRIPLE}\"
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CFLAGS+= -DDEFAULT_SYSROOT=\"${TOOLS_PREFIX}\"
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.if ${MK_LLVM_TARGET_AARCH64} != "no"
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CFLAGS+= -DLLVM_TARGET_ENABLE_AARCH64
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. if ${MACHINE_CPUARCH} == "aarch64"
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LLVM_NATIVE_ARCH= AArch64
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. endif
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.endif
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.if ${MK_LLVM_TARGET_ARM} != "no"
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CFLAGS+= -DLLVM_TARGET_ENABLE_ARM
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. if ${MACHINE_CPUARCH} == "arm"
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LLVM_NATIVE_ARCH= ARM
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. endif
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.endif
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.if ${MK_LLVM_TARGET_MIPS} != "no"
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CFLAGS+= -DLLVM_TARGET_ENABLE_MIPS
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. if ${MACHINE_CPUARCH} == "mips"
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LLVM_NATIVE_ARCH= Mips
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. endif
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.endif
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.if ${MK_LLVM_TARGET_POWERPC} != "no"
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CFLAGS+= -DLLVM_TARGET_ENABLE_POWERPC
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. if ${MACHINE_CPUARCH} == "powerpc"
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LLVM_NATIVE_ARCH= PowerPC
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. endif
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.endif
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.if ${MK_LLVM_TARGET_SPARC} != "no"
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CFLAGS+= -DLLVM_TARGET_ENABLE_SPARC
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. if ${MACHINE_CPUARCH} == "sparc64"
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LLVM_NATIVE_ARCH= Sparc
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. endif
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.endif
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.if ${MK_LLVM_TARGET_X86} != "no"
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CFLAGS+= -DLLVM_TARGET_ENABLE_X86
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. if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64"
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LLVM_NATIVE_ARCH= X86
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. endif
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.endif
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.ifdef LLVM_NATIVE_ARCH
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CFLAGS+= -DLLVM_NATIVE_ASMPARSER=LLVMInitialize${LLVM_NATIVE_ARCH}AsmParser
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CFLAGS+= -DLLVM_NATIVE_ASMPRINTER=LLVMInitialize${LLVM_NATIVE_ARCH}AsmPrinter
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CFLAGS+= -DLLVM_NATIVE_DISASSEMBLER=LLVMInitialize${LLVM_NATIVE_ARCH}Disassembler
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CFLAGS+= -DLLVM_NATIVE_TARGET=LLVMInitialize${LLVM_NATIVE_ARCH}Target
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CFLAGS+= -DLLVM_NATIVE_TARGETINFO=LLVMInitialize${LLVM_NATIVE_ARCH}TargetInfo
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CFLAGS+= -DLLVM_NATIVE_TARGETMC=LLVMInitialize${LLVM_NATIVE_ARCH}TargetMC
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.endif
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CFLAGS+= -ffunction-sections
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CFLAGS+= -fdata-sections
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LDFLAGS+= -Wl,--gc-sections
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@ -1,6 +1,6 @@
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.\" DO NOT EDIT-- this file is @generated by tools/build/options/makeman.
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.\" $FreeBSD$
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.Dd June 20, 2018
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.Dd June 22, 2018
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.Dt SRC.CONF 5
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.Os
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.Sh NAME
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@ -1019,6 +1019,66 @@ Set to use LLVM's libunwind stack unwinder (instead of GCC's unwinder).
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.Pp
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This is a default setting on
|
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amd64/amd64, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, riscv/riscv64 and riscv/riscv64sf.
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.It Va WITHOUT_LLVM_TARGET_AARCH64
|
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Set to not build LLVM target support for AArch64.
|
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.Pp
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This is a default setting on
|
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riscv/riscv64, riscv/riscv64sf and sparc64/sparc64.
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.It Va WITH_LLVM_TARGET_AARCH64
|
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Set to build LLVM target support for AArch64.
|
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.Pp
|
||||
This is a default setting on
|
||||
amd64/amd64, arm/arm, arm/armeb, arm/armv6, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and powerpc/powerpcspe.
|
||||
.It Va WITHOUT_LLVM_TARGET_ARM
|
||||
Set to not build LLVM target support for ARM.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
riscv/riscv64, riscv/riscv64sf and sparc64/sparc64.
|
||||
.It Va WITH_LLVM_TARGET_ARM
|
||||
Set to build LLVM target support for ARM.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
amd64/amd64, arm/arm, arm/armeb, arm/armv6, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and powerpc/powerpcspe.
|
||||
.It Va WITHOUT_LLVM_TARGET_MIPS
|
||||
Set to not build LLVM target support for MIPS.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
riscv/riscv64, riscv/riscv64sf and sparc64/sparc64.
|
||||
.It Va WITH_LLVM_TARGET_MIPS
|
||||
Set to build LLVM target support for MIPS.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
amd64/amd64, arm/arm, arm/armeb, arm/armv6, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and powerpc/powerpcspe.
|
||||
.It Va WITHOUT_LLVM_TARGET_POWERPC
|
||||
Set to not build LLVM target support for PowerPC.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
riscv/riscv64, riscv/riscv64sf and sparc64/sparc64.
|
||||
.It Va WITH_LLVM_TARGET_POWERPC
|
||||
Set to build LLVM target support for PowerPC.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
amd64/amd64, arm/arm, arm/armeb, arm/armv6, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and powerpc/powerpcspe.
|
||||
.It Va WITHOUT_LLVM_TARGET_SPARC
|
||||
Set to not build LLVM target support for SPARC.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
riscv/riscv64, riscv/riscv64sf and sparc64/sparc64.
|
||||
.It Va WITH_LLVM_TARGET_SPARC
|
||||
Set to build LLVM target support for SPARC.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
amd64/amd64, arm/arm, arm/armeb, arm/armv6, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and powerpc/powerpcspe.
|
||||
.It Va WITHOUT_LLVM_TARGET_X86
|
||||
Set to not build LLVM target support for X86.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
riscv/riscv64, riscv/riscv64sf and sparc64/sparc64.
|
||||
.It Va WITH_LLVM_TARGET_X86
|
||||
Set to build LLVM target support for X86.
|
||||
.Pp
|
||||
This is a default setting on
|
||||
amd64/amd64, arm/arm, arm/armeb, arm/armv6, arm/armv7, arm64/aarch64, i386/i386, mips/mipsel, mips/mips, mips/mips64el, mips/mips64, mips/mipsn32, mips/mipselhf, mips/mipshf, mips/mips64elhf, mips/mips64hf, powerpc/powerpc, powerpc/powerpc64 and powerpc/powerpcspe.
|
||||
.It Va WITH_LOADER_FIREWIRE
|
||||
Enable firewire support in /boot/loader and /boot/zfsloader on x86.
|
||||
This option is a nop on all other platforms.
|
||||
|
||||
@ -237,17 +237,23 @@ __TT=${MACHINE}
|
||||
${__T} == "amd64" || ${__TT} == "arm" || ${__T} == "i386")
|
||||
# Clang is enabled, and will be installed as the default /usr/bin/cc.
|
||||
__DEFAULT_YES_OPTIONS+=CLANG CLANG_BOOTSTRAP CLANG_FULL CLANG_IS_CC LLD
|
||||
__DEFAULT_YES_OPTIONS+=LLVM_TARGET_AARCH64 LLVM_TARGET_ARM LLVM_TARGET_MIPS
|
||||
__DEFAULT_YES_OPTIONS+=LLVM_TARGET_POWERPC LLVM_TARGET_SPARC LLVM_TARGET_X86
|
||||
__DEFAULT_NO_OPTIONS+=GCC GCC_BOOTSTRAP GNUCXX GPL_DTC
|
||||
.elif ${COMPILER_FEATURES:Mc++11} && ${__T:Mriscv*} == "" && ${__T} != "sparc64"
|
||||
# If an external compiler that supports C++11 is used as ${CC} and Clang
|
||||
# supports the target, then Clang is enabled but GCC is installed as the
|
||||
# default /usr/bin/cc.
|
||||
__DEFAULT_YES_OPTIONS+=CLANG CLANG_FULL GCC GCC_BOOTSTRAP GNUCXX GPL_DTC LLD
|
||||
__DEFAULT_YES_OPTIONS+=LLVM_TARGET_AARCH64 LLVM_TARGET_ARM LLVM_TARGET_MIPS
|
||||
__DEFAULT_YES_OPTIONS+=LLVM_TARGET_POWERPC LLVM_TARGET_SPARC LLVM_TARGET_X86
|
||||
__DEFAULT_NO_OPTIONS+=CLANG_BOOTSTRAP CLANG_IS_CC
|
||||
.else
|
||||
# Everything else disables Clang, and uses GCC instead.
|
||||
__DEFAULT_YES_OPTIONS+=GCC GCC_BOOTSTRAP GNUCXX GPL_DTC
|
||||
__DEFAULT_NO_OPTIONS+=CLANG CLANG_BOOTSTRAP CLANG_FULL CLANG_IS_CC LLD
|
||||
__DEFAULT_NO_OPTIONS+=LLVM_TARGET_AARCH64 LLVM_TARGET_ARM LLVM_TARGET_MIPS
|
||||
__DEFAULT_NO_OPTIONS+=LLVM_TARGET_POWERPC LLVM_TARGET_SPARC LLVM_TARGET_X86
|
||||
.endif
|
||||
# In-tree binutils/gcc are older versions without modern architecture support.
|
||||
.if ${__T} == "aarch64" || ${__T:Mriscv*} != ""
|
||||
|
||||
2
tools/build/options/WITHOUT_LLVM_TARGET_AARCH64
Normal file
2
tools/build/options/WITHOUT_LLVM_TARGET_AARCH64
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to not build LLVM target support for AArch64.
|
||||
2
tools/build/options/WITHOUT_LLVM_TARGET_ARM
Normal file
2
tools/build/options/WITHOUT_LLVM_TARGET_ARM
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to not build LLVM target support for ARM.
|
||||
2
tools/build/options/WITHOUT_LLVM_TARGET_MIPS
Normal file
2
tools/build/options/WITHOUT_LLVM_TARGET_MIPS
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to not build LLVM target support for MIPS.
|
||||
2
tools/build/options/WITHOUT_LLVM_TARGET_POWERPC
Normal file
2
tools/build/options/WITHOUT_LLVM_TARGET_POWERPC
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to not build LLVM target support for PowerPC.
|
||||
2
tools/build/options/WITHOUT_LLVM_TARGET_SPARC
Normal file
2
tools/build/options/WITHOUT_LLVM_TARGET_SPARC
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to not build LLVM target support for SPARC.
|
||||
2
tools/build/options/WITHOUT_LLVM_TARGET_X86
Normal file
2
tools/build/options/WITHOUT_LLVM_TARGET_X86
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to not build LLVM target support for X86.
|
||||
2
tools/build/options/WITH_LLVM_TARGET_AARCH64
Normal file
2
tools/build/options/WITH_LLVM_TARGET_AARCH64
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to build LLVM target support for AArch64.
|
||||
2
tools/build/options/WITH_LLVM_TARGET_ARM
Normal file
2
tools/build/options/WITH_LLVM_TARGET_ARM
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to build LLVM target support for ARM.
|
||||
2
tools/build/options/WITH_LLVM_TARGET_MIPS
Normal file
2
tools/build/options/WITH_LLVM_TARGET_MIPS
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to build LLVM target support for MIPS.
|
||||
2
tools/build/options/WITH_LLVM_TARGET_POWERPC
Normal file
2
tools/build/options/WITH_LLVM_TARGET_POWERPC
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to build LLVM target support for PowerPC.
|
||||
2
tools/build/options/WITH_LLVM_TARGET_SPARC
Normal file
2
tools/build/options/WITH_LLVM_TARGET_SPARC
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to build LLVM target support for SPARC.
|
||||
2
tools/build/options/WITH_LLVM_TARGET_X86
Normal file
2
tools/build/options/WITH_LLVM_TARGET_X86
Normal file
@ -0,0 +1,2 @@
|
||||
.\" $FreeBSD$
|
||||
Set to build LLVM target support for X86.
|
||||
Loading…
Reference in New Issue
Block a user