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A number of important fixes:
- mbuf reused after an RX_COPY optimized operation can sometimes have a bogus cached address, resulting in TCP hangs. Add critical save points to the cached address. Thanks to Michael and the team at Verisign for finding this problem. - A couple more spots where the rxbuf->flags member should be cleared just to be sure no incorrect RX_COPY state is left around. Thanks to Adrian for tracking these down. - Remove the rearm_queues function from the driver, this was found to be responsible for some out-of-order packets by Verisign, and was always a bandaid, with the other fixes in this delta the bandaid can finally be removed. - In the other/link interrupt handler the entire state of the EICS register was being writen back into EICR (which clears causes and thus re-enables those interrupts), this was wrong, so now mask off the queue portion of the register value, so we only clear the other/link interrupt we intend. Marc from Verisign found this. - Make the SFP+ unsupported option tuneable now, by customer request. - Finally, just a couple of minor DEBUG string fixes. I want to call out and thank all the participants in the 10G community/Intel calls for helping track down these problems and make the driver better for everyone! MFC after: 3 days, these are critical fixes for 9.2!
This commit is contained in:
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04ae0d7cc5
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=253865
@ -45,7 +45,7 @@ int ixgbe_display_debug_stats = 0;
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/*********************************************************************
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* Driver version
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*********************************************************************/
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char ixgbe_driver_version[] = "2.5.13";
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char ixgbe_driver_version[] = "2.5.15";
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/*********************************************************************
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* PCI Device ID Table
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@ -297,6 +297,7 @@ TUNABLE_INT("hw.ixgbe.rxd", &ixgbe_rxd);
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** doing so you are on your own :)
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*/
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static int allow_unsupported_sfp = FALSE;
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TUNABLE_INT("hw.ixgbe.unsupported_sfp", &allow_unsupported_sfp);
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/*
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** HW RSC control:
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@ -1071,7 +1072,7 @@ ixgbe_init_locked(struct adapter *adapter)
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u32 rxdctl, rxctrl;
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mtx_assert(&adapter->core_mtx, MA_OWNED);
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INIT_DEBUGOUT("ixgbe_init: begin");
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INIT_DEBUGOUT("ixgbe_init_locked: begin");
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hw->adapter_stopped = FALSE;
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ixgbe_stop_adapter(hw);
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callout_stop(&adapter->timer);
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@ -1382,23 +1383,6 @@ ixgbe_disable_queue(struct adapter *adapter, u32 vector)
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}
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}
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static inline void
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ixgbe_rearm_queues(struct adapter *adapter, u64 queues)
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{
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u32 mask;
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if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
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mask = (IXGBE_EIMS_RTX_QUEUE & queues);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
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} else {
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mask = (queues & 0xFFFFFFFF);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
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mask = (queues >> 32);
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IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
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}
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}
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static void
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ixgbe_handle_que(void *context, int pending)
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{
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@ -1506,6 +1490,10 @@ ixgbe_msix_que(void *arg)
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bool more;
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u32 newitr = 0;
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/* Protect against spurious interrupts */
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if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
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return;
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ixgbe_disable_queue(adapter, que->msix);
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++que->irqs;
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@ -1592,6 +1580,8 @@ ixgbe_msix_link(void *arg)
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/* First get the cause */
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reg_eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
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/* Be sure the queue bits are not cleared */
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reg_eicr = ~IXGBE_EICR_RTX_QUEUE;
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/* Clear interrupt with write */
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IXGBE_WRITE_REG(hw, IXGBE_EICR, reg_eicr);
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@ -2067,7 +2057,6 @@ ixgbe_local_timer(void *arg)
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goto watchdog;
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out:
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ixgbe_rearm_queues(adapter, adapter->que_mask);
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callout_reset(&adapter->timer, hz, ixgbe_local_timer, adapter);
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return;
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@ -3201,7 +3190,7 @@ ixgbe_free_transmit_buffers(struct tx_ring *txr)
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struct ixgbe_tx_buf *tx_buffer;
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int i;
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INIT_DEBUGOUT("free_transmit_ring: begin");
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INIT_DEBUGOUT("ixgbe_free_transmit_ring: begin");
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if (txr->tx_buffers == NULL)
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return;
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@ -4005,11 +3994,13 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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addr = PNMB(slot + sj, &paddr);
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netmap_load_map(rxr->ptag, rxbuf->pmap, addr);
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/* Update descriptor */
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/* Update descriptor and the cached value */
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rxr->rx_base[j].read.pkt_addr = htole64(paddr);
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rxbuf->addr = htole64(paddr);
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continue;
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}
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#endif /* DEV_NETMAP */
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rxbuf->flags = 0;
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rxbuf->buf = m_getjcl(M_NOWAIT, MT_DATA,
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M_PKTHDR, adapter->rx_mbuf_sz);
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if (rxbuf->buf == NULL) {
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@ -4026,8 +4017,9 @@ ixgbe_setup_receive_ring(struct rx_ring *rxr)
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goto fail;
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bus_dmamap_sync(rxr->ptag,
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rxbuf->pmap, BUS_DMASYNC_PREREAD);
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/* Update descriptor */
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/* Update the descriptor and the cached value */
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rxr->rx_base[j].read.pkt_addr = htole64(seg[0].ds_addr);
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rxbuf->addr = htole64(seg[0].ds_addr);
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}
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@ -4244,6 +4236,8 @@ ixgbe_free_receive_structures(struct adapter *adapter)
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{
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struct rx_ring *rxr = adapter->rx_rings;
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INIT_DEBUGOUT("ixgbe_free_receive_structures: begin");
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for (int i = 0; i < adapter->num_queues; i++, rxr++) {
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struct lro_ctrl *lro = &rxr->lro;
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ixgbe_free_receive_buffers(rxr);
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@ -4268,7 +4262,7 @@ ixgbe_free_receive_buffers(struct rx_ring *rxr)
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struct adapter *adapter = rxr->adapter;
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struct ixgbe_rx_buf *rxbuf;
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INIT_DEBUGOUT("free_receive_structures: begin");
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INIT_DEBUGOUT("ixgbe_free_receive_buffers: begin");
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/* Cleanup any existing buffers */
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if (rxr->rx_buffers != NULL) {
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@ -4359,6 +4353,8 @@ ixgbe_rx_discard(struct rx_ring *rxr, int i)
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rbuf->buf = NULL;
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}
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rbuf->flags = 0;
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return;
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}
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