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Prefer the cpuregs.h spellings of register and bit names over cpu.h.

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This commit is contained in:
Warner Losh 2010-07-14 00:41:22 +00:00
parent 9ae036550c
commit cded61cee5
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=210038
10 changed files with 297 additions and 289 deletions
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164
sys/mips/mips/exception.S
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@ -115,7 +115,7 @@ VECTOR(MipsTLBMiss, unknown)
.set push
.set noat
j MipsDoTLBMiss
MFC0 k0, COP_0_BAD_VADDR # get the fault address
MFC0 k0, MIPS_COP_0_BAD_VADDR # get the fault address
.set pop
VECTOR_END(MipsTLBMiss)
@ -144,7 +144,7 @@ MipsDoTLBMiss:
PTR_ADDU k1, k0, k1 #07: k1=seg entry address
PTR_L k1, 0(k1) #08: k1=seg entry
MFC0 k0, COP_0_BAD_VADDR #09: k0=bad address (again)
MFC0 k0, MIPS_COP_0_BAD_VADDR #09: k0=bad address (again)
beq k1, zero, 2f #0a: ==0 -- no page table
srl k0, PAGE_SHIFT - 2 #0b: k0=VPN (aka va>>10)
andi k0, k0, 0xff8 #0c: k0=page tab offset
@ -152,10 +152,10 @@ MipsDoTLBMiss:
lw k0, 0(k1) #0e: k0=lo0 pte
lw k1, 4(k1) #0f: k1=lo0 pte
CLEAR_PTE_SWBITS(k0)
MTC0 k0, COP_0_TLB_LO0 #12: lo0 is loaded
MTC0 k0, MIPS_COP_0_TLB_LO0 #12: lo0 is loaded
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1 #15: lo1 is loaded
MTC0 k1, MIPS_COP_0_TLB_LO1 #15: lo1 is loaded
COP0_SYNC
tlbwr #1a: write to tlb
HAZARD_DELAY
@ -176,13 +176,13 @@ VECTOR(MipsException, unknown)
* Find out what mode we came from and jump to the proper handler.
*/
.set noat
mfc0 k0, COP_0_STATUS_REG # Get the status register
mfc0 k1, COP_0_CAUSE_REG # Get the cause register value.
mfc0 k0, MIPS_COP_0_STATUS # Get the status register
mfc0 k1, MIPS_COP_0_CAUSE # Get the cause register value.
and k0, k0, SR_KSU_USER # test for user mode
# sneaky but the bits are
# with us........
sll k0, k0, 3 # shift user bit for cause index
and k1, k1, CR_EXC_CODE # Mask out the cause bits.
and k1, k1, MIPS3_CR_EXC_CODE # Mask out the cause bits.
or k1, k1, k0 # change index to user table
#if defined(__mips_n64)
PTR_SLL k1, k1, 1 # shift to get 8-byte offset
@ -207,7 +207,7 @@ VECTOR_END(MipsException)
*/
SlowFault:
.set noat
mfc0 k0, COP_0_STATUS_REG
mfc0 k0, MIPS_COP_0_STATUS
nop
and k0, k0, SR_KSU_USER
bne k0, zero, _C_LABEL(MipsUserGenException)
@ -237,28 +237,28 @@ SlowFault:
#if defined(TARGET_OCTEON)
#define CLEAR_STATUS \
mfc0 a0, COP_0_STATUS_REG ;\
mfc0 a0, MIPS_COP_0_STATUS ;\
li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
or a0, a0, a2 ; \
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \
and a0, a0, a2 ; \
mtc0 a0, COP_0_STATUS_REG ; \
mtc0 a0, MIPS_COP_0_STATUS ; \
ITLBNOPFIX
#elif defined(TARGET_XLR_XLS)
#define CLEAR_STATUS \
mfc0 a0, COP_0_STATUS_REG ;\
mfc0 a0, MIPS_COP_0_STATUS ;\
li a2, (MIPS_SR_KX | MIPS_SR_COP_2_BIT) ; \
or a0, a0, a2 ; \
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \
and a0, a0, a2 ; \
mtc0 a0, COP_0_STATUS_REG ; \
mtc0 a0, MIPS_COP_0_STATUS ; \
ITLBNOPFIX
#else
#define CLEAR_STATUS \
mfc0 a0, COP_0_STATUS_REG ;\
mfc0 a0, MIPS_COP_0_STATUS ;\
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER) ; \
and a0, a0, a2 ; \
mtc0 a0, COP_0_STATUS_REG ; \
mtc0 a0, MIPS_COP_0_STATUS ; \
ITLBNOPFIX
#endif
@ -302,10 +302,10 @@ SlowFault:
SAVE_REG(s8, S8, sp) ;\
mflo v0 ;\
mfhi v1 ;\
mfc0 a0, COP_0_STATUS_REG ;\
mfc0 a1, COP_0_CAUSE_REG ;\
MFC0 a2, COP_0_BAD_VADDR ;\
MFC0 a3, COP_0_EXC_PC ;\
mfc0 a0, MIPS_COP_0_STATUS ;\
mfc0 a1, MIPS_COP_0_CAUSE ;\
MFC0 a2, MIPS_COP_0_BAD_VADDR;\
MFC0 a3, MIPS_COP_0_EXC_PC ;\
SAVE_REG(v0, MULLO, sp) ;\
SAVE_REG(v1, MULHI, sp) ;\
SAVE_REG(a0, SR, sp) ;\
@ -332,7 +332,7 @@ SlowFault:
RESTORE_REG(t1, MULHI, sp) ;\
mtlo t0 ;\
mthi t1 ;\
MTC0 v0, COP_0_EXC_PC ;\
MTC0 v0, MIPS_COP_0_EXC_PC ;\
.set noat ;\
RESTORE_REG(AT, AST, sp) ;\
RESTORE_REG(v0, V0, sp) ;\
@ -363,7 +363,7 @@ SlowFault:
RESTORE_REG(gp, GP, sp) ;\
RESTORE_REG(ra, RA, sp) ;\
PTR_ADDU sp, sp, KERN_EXC_FRAME_SIZE;\
mtc0 k0, COP_0_STATUS_REG
mtc0 k0, MIPS_COP_0_STATUS
/*
@ -396,10 +396,10 @@ NNON_LEAF(MipsKernGenException, KERN_EXC_FRAME_SIZE, ra)
* intr filters if interrupts are enabled later
* in trap handler
*/
mfc0 a0, COP_0_STATUS_REG
and a0, a0, SR_INT_MASK
mfc0 a0, MIPS_COP_0_STATUS
and a0, a0, MIPS_SR_INT_MASK
RESTORE_REG(a1, SR, sp)
and a1, a1, ~SR_INT_MASK
and a1, a1, ~MIPS_SR_INT_MASK
or a1, a1, a0
SAVE_REG(a1, SR, sp)
RESTORE_CPU # v0 contains the return address.
@ -452,22 +452,22 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
SAVE_U_PCB_REG(t2, T2, k1)
SAVE_U_PCB_REG(t3, T3, k1)
SAVE_U_PCB_REG(ta0, TA0, k1)
mfc0 a0, COP_0_STATUS_REG # First arg is the status reg.
mfc0 a0, MIPS_COP_0_STATUS # First arg is the status reg.
SAVE_U_PCB_REG(ta1, TA1, k1)
SAVE_U_PCB_REG(ta2, TA2, k1)
SAVE_U_PCB_REG(ta3, TA3, k1)
SAVE_U_PCB_REG(s0, S0, k1)
mfc0 a1, COP_0_CAUSE_REG # Second arg is the cause reg.
mfc0 a1, MIPS_COP_0_CAUSE # Second arg is the cause reg.
SAVE_U_PCB_REG(s1, S1, k1)
SAVE_U_PCB_REG(s2, S2, k1)
SAVE_U_PCB_REG(s3, S3, k1)
SAVE_U_PCB_REG(s4, S4, k1)
MFC0 a2, COP_0_BAD_VADDR # Third arg is the fault addr
MFC0 a2, MIPS_COP_0_BAD_VADDR # Third arg is the fault addr
SAVE_U_PCB_REG(s5, S5, k1)
SAVE_U_PCB_REG(s6, S6, k1)
SAVE_U_PCB_REG(s7, S7, k1)
SAVE_U_PCB_REG(t8, T8, k1)
MFC0 a3, COP_0_EXC_PC # Fourth arg is the pc.
MFC0 a3, MIPS_COP_0_EXC_PC # Fourth arg is the pc.
SAVE_U_PCB_REG(t9, T9, k1)
SAVE_U_PCB_REG(gp, GP, k1)
SAVE_U_PCB_REG(sp, SP, k1)
@ -483,13 +483,13 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
REG_S a3, CALLFRAME_RA(sp) # for debugging
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
# Turn off fpu and enter kernel mode
and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_KSU_MASK | SR_INT_ENAB)
and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS3_SR_KSU_MASK | MIPS_SR_INT_IE)
#if defined(TARGET_OCTEON)
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX)
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
#elif defined(TARGET_XLR_XLS)
or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT)
#endif
mtc0 t0, COP_0_STATUS_REG
mtc0 t0, MIPS_COP_0_STATUS
PTR_ADDU a0, k1, U_PCB_REGS
ITLBNOPFIX
@ -521,10 +521,10 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
* Some of interrupts could be enabled by ithread
* scheduled by ast()
*/
mfc0 a0, COP_0_STATUS_REG
and a0, a0, SR_INT_MASK
mfc0 a0, MIPS_COP_0_STATUS
and a0, a0, MIPS_SR_INT_MASK
RESTORE_U_PCB_REG(a1, SR, k1)
and a1, a1, ~SR_INT_MASK
and a1, a1, ~MIPS_SR_INT_MASK
or a1, a1, a0
SAVE_U_PCB_REG(a1, SR, k1)
@ -534,7 +534,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
mthi t1
RESTORE_U_PCB_REG(a0, PC, k1)
RESTORE_U_PCB_REG(v0, V0, k1)
MTC0 a0, COP_0_EXC_PC # set return address
MTC0 a0, MIPS_COP_0_EXC_PC # set return address
RESTORE_U_PCB_REG(v1, V1, k1)
RESTORE_U_PCB_REG(a0, A0, k1)
RESTORE_U_PCB_REG(a1, A1, k1)
@ -566,7 +566,7 @@ NNON_LEAF(MipsUserGenException, CALLFRAME_SIZ, ra)
.set noat
RESTORE_U_PCB_REG(AT, AST, k1)
mtc0 k0, COP_0_STATUS_REG # still exception level
mtc0 k0, MIPS_COP_0_STATUS # still exception level
ITLBNOPFIX
sync
eret
@ -612,10 +612,10 @@ NNON_LEAF(MipsKernIntr, KERN_EXC_FRAME_SIZE, ra)
* intr filters if interrupts are enabled later
* in trap handler
*/
mfc0 a0, COP_0_STATUS_REG
and a0, a0, SR_INT_MASK
mfc0 a0, MIPS_COP_0_STATUS
and a0, a0, MIPS_SR_INT_MASK
RESTORE_REG(a1, SR, sp)
and a1, a1, ~SR_INT_MASK
and a1, a1, ~MIPS_SR_INT_MASK
or a1, a1, a0
SAVE_REG(a1, SR, sp)
REG_L v0, CALLFRAME_RA + KERN_REG_SIZE(sp)
@ -689,9 +689,9 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
mflo v0 # get lo/hi late to avoid stall
mfhi v1
mfc0 a0, COP_0_STATUS_REG
mfc0 a1, COP_0_CAUSE_REG
MFC0 a3, COP_0_EXC_PC
mfc0 a0, MIPS_COP_0_STATUS
mfc0 a1, MIPS_COP_0_CAUSE
MFC0 a3, MIPS_COP_0_EXC_PC
SAVE_U_PCB_REG(v0, MULLO, k1)
SAVE_U_PCB_REG(v1, MULHI, k1)
SAVE_U_PCB_REG(a0, SR, k1)
@ -701,13 +701,13 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
PTR_LA gp, _C_LABEL(_gp) # switch to kernel GP
# Turn off fpu, disable interrupts, set kernel mode kernel mode, clear exception level.
and t0, a0, ~(SR_COP_1_BIT | SR_EXL | SR_INT_ENAB | SR_KSU_MASK)
and t0, a0, ~(MIPS_SR_COP_1_BIT | MIPS_SR_EXL | MIPS_SR_INT_IE | MIPS3_SR_KSU_MASK)
#ifdef TARGET_OCTEON
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS32_SR_PX)
or t0, t0, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX | MIPS_SR_PX)
#elif defined(TARGET_XLR_XLS)
or t0, t0, (MIPS_SR_KX | MIPS_SR_COP_2_BIT)
#endif
mtc0 t0, COP_0_STATUS_REG
mtc0 t0, MIPS_COP_0_STATUS
ITLBNOPFIX
PTR_ADDU a0, k1, U_PCB_REGS
/*
@ -724,9 +724,9 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
* If that processor is also doing AST processing with interrupts disabled
* then we may deadlock.
*/
mfc0 a0, COP_0_STATUS_REG
or a0, a0, SR_INT_ENAB
mtc0 a0, COP_0_STATUS_REG
mfc0 a0, MIPS_COP_0_STATUS
or a0, a0, MIPS_SR_INT_IE
mtc0 a0, MIPS_COP_0_STATUS
ITLBNOPFIX
/*
@ -747,10 +747,10 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
* Some of interrupts could be disabled by
* intr filters
*/
mfc0 a0, COP_0_STATUS_REG
and a0, a0, SR_INT_MASK
mfc0 a0, MIPS_COP_0_STATUS
and a0, a0, MIPS_SR_INT_MASK
RESTORE_U_PCB_REG(a1, SR, k1)
and a1, a1, ~SR_INT_MASK
and a1, a1, ~MIPS_SR_INT_MASK
or a1, a1, a0
SAVE_U_PCB_REG(a1, SR, k1)
@ -768,7 +768,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
RESTORE_U_PCB_REG(t2, PC, k1)
mtlo t0
mthi t1
MTC0 t2, COP_0_EXC_PC # set return address
MTC0 t2, MIPS_COP_0_EXC_PC # set return address
RESTORE_U_PCB_REG(v0, V0, k1)
RESTORE_U_PCB_REG(v1, V1, k1)
RESTORE_U_PCB_REG(a0, A0, k1)
@ -792,7 +792,7 @@ NNON_LEAF(MipsUserIntr, CALLFRAME_SIZ, ra)
.set noat
RESTORE_U_PCB_REG(AT, AST, k1)
mtc0 k0, COP_0_STATUS_REG # SR with EXL set.
mtc0 k0, MIPS_COP_0_STATUS # SR with EXL set.
ITLBNOPFIX
sync
eret
@ -804,7 +804,7 @@ NLEAF(MipsTLBInvalidException)
.set noat
.set noreorder
MFC0 k0, COP_0_BAD_VADDR
MFC0 k0, MIPS_COP_0_BAD_VADDR
PTR_LI k1, VM_MAXUSER_ADDRESS
sltu k1, k0, k1
bnez k1, 1f
@ -833,7 +833,7 @@ NLEAF(MipsTLBInvalidException)
beqz k1, 3f
nop
MFC0 k0, COP_0_BAD_VADDR # k0=bad address (again)
MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
PTR_SRL k0, PAGE_SHIFT - 2 # k0=VPN
andi k0, k0, 0xffc # k0=page tab offset
PTR_ADDU k1, k1, k0 # k1=pte address
@ -852,10 +852,10 @@ NLEAF(MipsTLBInvalidException)
lw k0, 0(k1)
lw k1, 4(k1)
CLEAR_PTE_SWBITS(k0)
MTC0 k0, COP_0_TLB_LO0
MTC0 k0, MIPS_COP_0_TLB_LO0
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1
MTC0 k1, MIPS_COP_0_TLB_LO1
COP0_SYNC
b tlb_insert_entry
@ -865,16 +865,16 @@ odd_page:
lw k0, -4(k1)
lw k1, 0(k1)
CLEAR_PTE_SWBITS(k0)
MTC0 k0, COP_0_TLB_LO0
MTC0 k0, MIPS_COP_0_TLB_LO0
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1
MTC0 k1, MIPS_COP_0_TLB_LO1
COP0_SYNC
tlb_insert_entry:
tlbp
HAZARD_DELAY
mfc0 k0, COP_0_TLB_INDEX
mfc0 k0, MIPS_COP_0_TLB_INDEX
bltz k0, tlb_insert_random
nop
tlbwi
@ -890,7 +890,7 @@ tlb_insert_random:
/*
* Branch to the comprehensive exception processing.
*/
mfc0 k1, COP_0_STATUS_REG
mfc0 k1, MIPS_COP_0_STATUS
andi k1, k1, SR_KSU_USER
bnez k1, _C_LABEL(MipsUserGenException)
nop
@ -980,7 +980,7 @@ END(MipsTLBInvalidException)
*/
NLEAF(MipsTLBMissException)
.set noat
MFC0 k0, COP_0_BAD_VADDR # k0=bad address
MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address
PTR_LI k1, VM_MAX_KERNEL_ADDRESS # check fault address against
sltu k1, k1, k0 # upper bound of kernel_segmap
bnez k1, MipsKernGenException # out of bound
@ -991,7 +991,7 @@ NLEAF(MipsTLBMissException)
andi k0, k0, PTRMASK # k0=seg offset
PTR_ADDU k1, k0, k1 # k1=seg entry address
PTR_L k1, 0(k1) # k1=seg entry
MFC0 k0, COP_0_BAD_VADDR # k0=bad address (again)
MFC0 k0, MIPS_COP_0_BAD_VADDR # k0=bad address (again)
beq k1, zero, MipsKernGenException # ==0 -- no page table
PTR_SRL k0, PAGE_SHIFT - 2 # k0=VPN
andi k0, k0, 0xff8 # k0=page tab offset
@ -999,10 +999,10 @@ NLEAF(MipsTLBMissException)
lw k0, 0(k1) # k0=lo0 pte
lw k1, 4(k1) # k1=lo1 pte
CLEAR_PTE_SWBITS(k0)
MTC0 k0, COP_0_TLB_LO0 # lo0 is loaded
MTC0 k0, MIPS_COP_0_TLB_LO0 # lo0 is loaded
COP0_SYNC
CLEAR_PTE_SWBITS(k1)
MTC0 k1, COP_0_TLB_LO1 # lo1 is loaded
MTC0 k1, MIPS_COP_0_TLB_LO1 # lo1 is loaded
COP0_SYNC
tlbwr # write to tlb
HAZARD_DELAY
@ -1031,15 +1031,15 @@ END(MipsTLBMissException)
*/
NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra)
PTR_SUBU sp, sp, CALLFRAME_SIZ
mfc0 t0, COP_0_STATUS_REG
mfc0 t0, MIPS_COP_0_STATUS
REG_S ra, CALLFRAME_RA(sp)
.mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
or t1, t0, SR_COP_1_BIT
mtc0 t1, COP_0_STATUS_REG
or t1, t0, MIPS_SR_COP_1_BIT
mtc0 t1, MIPS_COP_0_STATUS
ITLBNOPFIX
cfc1 t1, FPC_CSR # stall til FP done
cfc1 t1, FPC_CSR # now get status
cfc1 t1, MIPS_FPU_CSR # stall til FP done
cfc1 t1, MIPS_FPU_CSR # now get status
nop
sll t2, t1, (31 - 17) # unimplemented operation?
bgez t2, 3f # no, normal trap
@ -1087,8 +1087,8 @@ NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra)
* Check to see if the instruction to be emulated is a floating-point
* instruction.
*/
srl a3, a0, OPCODE_SHIFT
beq a3, OPCODE_C1, 4f # this should never fail
srl a3, a0, MIPS_OPCODE_SHIFT
beq a3, MIPS_OPCODE_C1, 4f # this should never fail
nop
/*
* Send a floating point exception signal to the current process.
@ -1096,8 +1096,8 @@ NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra)
3:
GET_CPU_PCPU(a0)
PTR_L a0, PC_CURTHREAD(a0) # get current thread
cfc1 a2, FPC_CSR # code = FP execptions
ctc1 zero, FPC_CSR # Clear exceptions
cfc1 a2, MIPS_FPU_CSR # code = FP execptions
ctc1 zero, MIPS_FPU_CSR # Clear exceptions
PTR_LA t3, _C_LABEL(trapsignal)
jalr t3
li a1, SIGFPE
@ -1116,10 +1116,10 @@ NON_LEAF(MipsFPTrap, CALLFRAME_SIZ, ra)
* Turn off the floating point coprocessor and return.
*/
FPReturn:
mfc0 t0, COP_0_STATUS_REG
mfc0 t0, MIPS_COP_0_STATUS
PTR_L ra, CALLFRAME_RA(sp)
and t0, t0, ~SR_COP_1_BIT
mtc0 t0, COP_0_STATUS_REG
and t0, t0, ~MIPS_SR_COP_1_BIT
mtc0 t0, MIPS_COP_0_STATUS
ITLBNOPFIX
j ra
PTR_ADDU sp, sp, CALLFRAME_SIZ
@ -1168,15 +1168,15 @@ NESTED_NOPROFILE(MipsCacheException, KERN_EXC_FRAME_SIZE, ra)
.mask 0x80000000, -4
PTR_LA k0, _C_LABEL(panic) # return to panic
PTR_LA a0, 9f # panicstr
MFC0 a1, COP_0_ERROR_PC
mfc0 a2, COP_0_CACHE_ERR # 3rd arg cache error
MFC0 a1, MIPS_COP_0_ERROR_PC
mfc0 a2, MIPS_COP_0_CACHE_ERR # 3rd arg cache error
MTC0 k0, COP_0_ERROR_PC # set return address
MTC0 k0, MIPS_COP_0_ERROR_PC # set return address
mfc0 k0, COP_0_STATUS_REG # restore status
li k1, SR_DIAG_DE # ignore further errors
mfc0 k0, MIPS_COP_0_STATUS # restore status
li k1, MIPS_SR_DIAG_PE # ignore further errors
or k0, k1
mtc0 k0, COP_0_STATUS_REG # restore status
mtc0 k0, MIPS_COP_0_STATUS # restore status
COP0_SYNC
eret

212
sys/mips/mips/fp.S
View File

@ -41,7 +41,7 @@
#include <machine/asm.h>
#include <machine/regnum.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
#include "assym.s"
@ -107,10 +107,10 @@ NON_LEAF(MipsEmulateFP, CALLFRAME_SIZ, ra)
bgt v0, 4 << 2, ill # illegal format
or v1, v1, v0
cfc1 a1, FPC_CSR # get exception register
cfc1 a1, MIPS_FPU_CSR # get exception register
lw a3, func_fmt_tbl(v1) # switch on FUNC & FMT
and a1, a1, ~FPC_EXCEPTION_UNIMPL # clear exception
ctc1 a1, FPC_CSR
and a1, a1, ~MIPS_FPU_EXCEPTION_UNIMPL # clear exception
ctc1 a1, MIPS_FPU_CSR
j a3
.rdata
@ -665,8 +665,8 @@ add_sub_s:
3:
bne ta1, zero, result_ft_s # if FT != 0, result=FT
bne ta2, zero, result_ft_s
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
bne v0, FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_s
1:
@ -724,8 +724,8 @@ add_sub_s:
bne t2, ta2, 2f # if same, result=0
move t1, zero # result=0
move t2, zero
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
bne v0, FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_s
1:
@ -788,8 +788,8 @@ add_sub_d:
bne ta1, zero, result_ft_d # if FT != 0, result=FT
bne ta2, zero, result_ft_d
bne ta3, zero, result_ft_d
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
bne v0, FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_d
1:
@ -882,8 +882,8 @@ add_sub_d:
move t1, zero # result=0
move t2, zero
move t3, zero
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
bne v0, FPC_ROUND_RM, 1f # round to -infinity?
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
bne v0, MIPS_FPU_ROUND_RM, 1f # round to -infinity?
or t0, t0, ta0 # compute result sign
b result_fs_d
1:
@ -1078,10 +1078,10 @@ div_s:
3:
bne ta1, zero, 2f # is FT zero?
bne ta2, zero, 1f
or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0
and v0, a1, FPC_ENABLE_DIV0 # trap enabled?
or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
li t1, SEXP_INF # result is infinity
move t2, zero
b result_fs_s
@ -1152,10 +1152,10 @@ div_d:
bne ta1, zero, 2f # is FT zero?
bne ta2, zero, 1f
bne ta3, zero, 1f
or a1, a1, FPC_EXCEPTION_DIV0 | FPC_STICKY_DIV0
and v0, a1, FPC_ENABLE_DIV0 # trap enabled?
or a1, a1, MIPS_FPU_EXCEPTION_DIV0 | MIPS_FPU_STICKY_DIV0
and v0, a1, MIPS_FPU_ENABLE_DIV0 # trap enabled?
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # Save exceptions
ctc1 a1, MIPS_FPU_CSR # Save exceptions
li t1, DEXP_INF # result is infinity
move t2, zero
move t3, zero
@ -1504,10 +1504,10 @@ cvt_w:
* round result (t0 is sign, t2 is integer part, t3 is fractional part).
*/
2:
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, 3f # round to nearest
beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -1536,10 +1536,10 @@ cvt_w:
* Handle inexact exception.
*/
inexact_w:
or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT
and v0, a1, FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b result_fs_w
/*
@ -1548,10 +1548,10 @@ inexact_w:
* or generate an invalid exception.
*/
overflow_w:
or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW
and v0, a1, FPC_ENABLE_OVERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
bne v0, zero, fpe_trap
and v0, a1, FPC_ENABLE_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, inexact_w # inexact traps enabled?
b invalid_w
@ -1561,10 +1561,10 @@ overflow_w:
* or generate an invalid exception.
*/
underflow_w:
or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW
and v0, a1, FPC_ENABLE_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
bne v0, zero, fpe_trap
and v0, a1, FPC_ENABLE_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, inexact_w # inexact traps enabled?
b invalid_w
@ -1640,29 +1640,29 @@ test_cond:
and v0, v0, a0 # condition match instruction?
set_cond:
bne v0, zero, 1f
and a1, a1, ~FPC_COND_BIT # clear condition bit
and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit
b 2f
1:
or a1, a1, FPC_COND_BIT # set condition bit
or a1, a1, MIPS_FPU_COND_BIT # set condition bit
2:
ctc1 a1, FPC_CSR # save condition bit
ctc1 a1, MIPS_FPU_CSR # save condition bit
b done
unordered:
and v0, a0, COND_UNORDERED # this cmp match unordered?
bne v0, zero, 1f
and a1, a1, ~FPC_COND_BIT # clear condition bit
and a1, a1, ~MIPS_FPU_COND_BIT # clear condition bit
b 2f
1:
or a1, a1, FPC_COND_BIT # set condition bit
or a1, a1, MIPS_FPU_COND_BIT # set condition bit
2:
and v0, a0, COND_SIGNAL
beq v0, zero, 1f # is this a signaling cmp?
or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID
and v0, a1, FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
1:
ctc1 a1, FPC_CSR # save condition bit
ctc1 a1, MIPS_FPU_CSR # save condition bit
b done
/*
@ -1727,10 +1727,10 @@ norm_s:
norm_noshift_s:
move ta1, t1 # save unrounded exponent
move ta2, t2 # save unrounded fraction
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, 3f # round to nearest
beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -1770,10 +1770,10 @@ inexact_s:
and t2, t2, ~SIMPL_ONE # clear implied one bit
inexact_nobias_s:
jal set_fd_s # save result
or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT
and v0, a1, FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -1782,18 +1782,18 @@ inexact_nobias_s:
* or generate an infinity.
*/
overflow_s:
or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW
and v0, a1, FPC_ENABLE_OVERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
beq v0, zero, 1f
subu t1, t1, 192 # bias exponent
and t2, t2, ~SIMPL_ONE # clear implied one bit
jal set_fd_s # save result
b fpe_trap
1:
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, 3f # round to nearest
beq v0, FPC_ROUND_RZ, 1f # round to zero (truncate)
beq v0, FPC_ROUND_RP, 2f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
bne t0, zero, 3f
1:
li t1, SEXP_MAX # result is max finite
@ -1811,7 +1811,7 @@ overflow_s:
* "loss of accuracy" is detected as "an inexact result".
*/
underflow_s:
and v0, a1, FPC_ENABLE_UNDERFLOW
and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
beq v0, zero, 1f
/*
* Underflow is enabled so compute the result and trap.
@ -1819,7 +1819,7 @@ underflow_s:
addu t1, t1, 192 # bias exponent
and t2, t2, ~SIMPL_ONE # clear implied one bit
jal set_fd_s # save result
or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
b fpe_trap
/*
* Underflow is not enabled so compute the result,
@ -1833,15 +1833,15 @@ underflow_s:
blt t9, SFRAC_BITS+2, 3f # shift all the bits out?
move t1, zero # result is inexact zero
move t2, zero
or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
/*
* Now round the zero result.
* Only need to worry about rounding to +- infinity when the sign matches.
*/
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, inexact_nobias_s # round to nearest
beq v0, FPC_ROUND_RZ, inexact_nobias_s # round to zero
beq v0, FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_s # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_s # round to zero
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, inexact_nobias_s # if sign is positive, truncate
b 2f
1:
@ -1859,10 +1859,10 @@ underflow_s:
/*
* Now round the denormalized result.
*/
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, 3f # round to nearest
beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -1884,11 +1884,11 @@ underflow_s:
move t1, zero # denorm or zero exponent
jal set_fd_s # save result
beq t8, zero, done # check for exact result
or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW
or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT
and v0, a1, FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -1973,10 +1973,10 @@ norm_noshift_d:
move ta1, t1 # save unrounded exponent
move ta2, t2 # save unrounded fraction (MS)
move ta3, t3 # save unrounded fraction (LS)
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, 3f # round to nearest
beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -2020,10 +2020,10 @@ inexact_d:
and t2, t2, ~DIMPL_ONE # clear implied one bit
inexact_nobias_d:
jal set_fd_d # save result
or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT
and v0, a1, FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -2032,18 +2032,18 @@ inexact_nobias_d:
* or generate an infinity.
*/
overflow_d:
or a1, a1, FPC_EXCEPTION_OVERFLOW | FPC_STICKY_OVERFLOW
and v0, a1, FPC_ENABLE_OVERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_OVERFLOW | MIPS_FPU_STICKY_OVERFLOW
and v0, a1, MIPS_FPU_ENABLE_OVERFLOW
beq v0, zero, 1f
subu t1, t1, 1536 # bias exponent
and t2, t2, ~DIMPL_ONE # clear implied one bit
jal set_fd_d # save result
b fpe_trap
1:
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, 3f # round to nearest
beq v0, FPC_ROUND_RZ, 1f # round to zero (truncate)
beq v0, FPC_ROUND_RP, 2f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 1f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 2f # round to +infinity
bne t0, zero, 3f
1:
li t1, DEXP_MAX # result is max finite
@ -2063,7 +2063,7 @@ overflow_d:
* "loss of accuracy" is detected as "an inexact result".
*/
underflow_d:
and v0, a1, FPC_ENABLE_UNDERFLOW
and v0, a1, MIPS_FPU_ENABLE_UNDERFLOW
beq v0, zero, 1f
/*
* Underflow is enabled so compute the result and trap.
@ -2071,7 +2071,7 @@ underflow_d:
addu t1, t1, 1536 # bias exponent
and t2, t2, ~DIMPL_ONE # clear implied one bit
jal set_fd_d # save result
or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
b fpe_trap
/*
* Underflow is not enabled so compute the result,
@ -2087,15 +2087,15 @@ underflow_d:
move t1, zero # result is inexact zero
move t2, zero
move t3, zero
or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
/*
* Now round the zero result.
* Only need to worry about rounding to +- infinity when the sign matches.
*/
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, inexact_nobias_d # round to nearest
beq v0, FPC_ROUND_RZ, inexact_nobias_d # round to zero
beq v0, FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, inexact_nobias_d # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, inexact_nobias_d # round to zero
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, inexact_nobias_d # if sign is positive, truncate
b 2f
1:
@ -2127,10 +2127,10 @@ underflow_d:
* Now round the denormalized result.
*/
2:
and v0, a1, FPC_ROUNDING_BITS # get rounding mode
beq v0, FPC_ROUND_RN, 3f # round to nearest
beq v0, FPC_ROUND_RZ, 5f # round to zero (truncate)
beq v0, FPC_ROUND_RP, 1f # round to +infinity
and v0, a1, MIPS_FPU_ROUNDING_BITS # get rounding mode
beq v0, MIPS_FPU_ROUND_RN, 3f # round to nearest
beq v0, MIPS_FPU_ROUND_RZ, 5f # round to zero (truncate)
beq v0, MIPS_FPU_ROUND_RP, 1f # round to +infinity
beq t0, zero, 5f # if sign is positive, truncate
b 2f
1:
@ -2156,11 +2156,11 @@ underflow_d:
move t1, zero # denorm or zero exponent
jal set_fd_d # save result
beq t8, zero, done # check for exact result
or a1, a1, FPC_EXCEPTION_UNDERFLOW | FPC_STICKY_UNDERFLOW
or a1, a1, FPC_EXCEPTION_INEXACT | FPC_STICKY_INEXACT
and v0, a1, FPC_ENABLE_INEXACT
or a1, a1, MIPS_FPU_EXCEPTION_UNDERFLOW | MIPS_FPU_STICKY_UNDERFLOW
or a1, a1, MIPS_FPU_EXCEPTION_INEXACT | MIPS_FPU_STICKY_INEXACT
and v0, a1, MIPS_FPU_ENABLE_INEXACT
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
b done
/*
@ -2168,10 +2168,10 @@ underflow_d:
* the result is a quiet NAN.
*/
invalid_s: # trap invalid operation
or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID
and v0, a1, FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
move t0, zero # result is a quiet NAN
li t1, SEXP_INF
li t2, SQUIET_NAN
@ -2183,10 +2183,10 @@ invalid_s: # trap invalid operation
* the result is a quiet NAN.
*/
invalid_d: # trap invalid operation
or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID
and v0, a1, FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
move t0, zero # result is a quiet NAN
li t1, DEXP_INF
li t2, DQUIET_NAN0
@ -2199,10 +2199,10 @@ invalid_d: # trap invalid operation
* the result is INT_MAX or INT_MIN.
*/
invalid_w: # trap invalid operation
or a1, a1, FPC_EXCEPTION_INVALID | FPC_STICKY_INVALID
and v0, a1, FPC_ENABLE_INVALID
or a1, a1, MIPS_FPU_EXCEPTION_INVALID | MIPS_FPU_STICKY_INVALID
and v0, a1, MIPS_FPU_ENABLE_INVALID
bne v0, zero, fpe_trap
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
bne t0, zero, 1f
li t2, INT_MAX # result is INT_MAX
b result_fs_w
@ -2215,14 +2215,14 @@ invalid_w: # trap invalid operation
*/
fpe_trap:
move a2, a1 # code = FP CSR
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
break 0
/*
* Send an illegal instruction signal to the current process.
*/
ill:
ctc1 a1, FPC_CSR # save exceptions
ctc1 a1, MIPS_FPU_CSR # save exceptions
move a2, a0 # code = FP instruction
break 0

14
sys/mips/mips/machdep.c
View File

@ -344,19 +344,19 @@ mips_vector_init(void)
if (MipsCacheEnd - MipsCache > 0x80)
panic("startup: Cache error code too large");
bcopy(MipsTLBMiss, (void *)TLB_MISS_EXC_VEC,
bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
#if defined(TARGET_OCTEON) || defined(TARGET_XLR_XLS)
/* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
bcopy(MipsTLBMiss, (void *)XTLB_MISS_EXC_VEC,
bcopy(MipsTLBMiss, (void *)MIPS3_XTLB_MISS_EXC_VEC,
MipsTLBMissEnd - MipsTLBMiss);
#endif
bcopy(MipsException, (void *)GEN_EXC_VEC,
bcopy(MipsException, (void *)MIPS3_GEN_EXC_VEC,
MipsExceptionEnd - MipsException);
bcopy(MipsCache, (void *)CACHE_ERR_EXC_VEC,
bcopy(MipsCache, (void *)MIPS3_CACHE_ERR_EXC_VEC,
MipsCacheEnd - MipsCache);
/*
@ -369,10 +369,10 @@ mips_vector_init(void)
* Mask all interrupts. Each interrupt will be enabled
* when handler is installed for it
*/
set_intr_mask(ALL_INT_MASK);
set_intr_mask(MIPS_SR_INT_MASK);
/* Clear BEV in SR so we start handling our own exceptions */
mips_wr_status(mips_rd_status() & ~SR_BOOT_EXC_VEC);
mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
}
/*
@ -489,7 +489,7 @@ spinlock_exit(void)
void
cpu_idle(int busy)
{
if (mips_rd_status() & SR_INT_ENAB)
if (mips_rd_status() & MIPS_SR_INT_IE)
__asm __volatile ("wait");
else
panic("ints disabled in idleproc!");

12
sys/mips/mips/mpboot.S
View File

@ -38,23 +38,23 @@
#ifdef TARGET_OCTEON
#define CLEAR_STATUS \
mfc0 a0, COP_0_STATUS_REG ;\
mfc0 a0, MIPS_COP_0_STATUS ;\
li a2, (MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX) ; \
or a0, a0, a2 ; \
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER | MIPS_SR_BEV) ; \
li a2, ~(MIPS_SR_INT_IE | MIPS_SR_EXL | SR_KSU_USER | MIPS_SR_BEV) ; \
and a0, a0, a2 ; \
mtc0 a0, COP_0_STATUS_REG
mtc0 a0, MIPS_COP_0_STATUS
#else
#define CLEAR_STATUS \
mtc0 zero, COP_0_STATUS_REG
mtc0 zero, MIPS_COP_0_STATUS
#endif
GLOBAL(mpentry)
CLEAR_STATUS /* disable interrupts */
mtc0 zero, COP_0_CAUSE_REG /* clear soft interrupts */
mtc0 zero, MIPS_COP_0_CAUSE /* clear soft interrupts */
li t0, CFG_K0_CACHED /* make sure kseg0 is cached */
li t0, MIPS_CCA_CNC /* make sure kseg0 is cached */
mtc0 t0, MIPS_COP_0_CONFIG
COP0_SYNC

10
sys/mips/mips/pm_machdep.c
View File

@ -311,7 +311,7 @@ ptrace_single_step(struct thread *td)
unsigned va;
struct trapframe *locr0 = td->td_frame;
int i;
int bpinstr = BREAK_SSTEP;
int bpinstr = MIPS_BREAK_SSTEP;
int curinstr;
struct proc *p;
@ -484,13 +484,13 @@ exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
td->td_frame->sp = ((register_t) stack) & ~(sizeof(__int64_t) - 1);
td->td_frame->pc = imgp->entry_addr & ~3;
td->td_frame->t9 = imgp->entry_addr & ~3; /* abicall req */
td->td_frame->sr = SR_KSU_USER | SR_EXL | SR_INT_ENAB |
(mips_rd_status() & ALL_INT_MASK);
td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
(mips_rd_status() & MIPS_SR_INT_MASK);
#if defined(__mips_n32) || defined(__mips_n64)
td->td_frame->sr |= SR_PX;
td->td_frame->sr |= MIPS_SR_PX;
#endif
#ifdef TARGET_OCTEON
td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX |
td->td_frame->sr |= MIPS_SR_COP_2_BIT | MIPS_SR_PX | MIPS_SR_UX |
MIPS_SR_KX | MIPS_SR_SX;
#endif
/*

14
sys/mips/mips/psraccess.S
View File

@ -38,7 +38,7 @@
*/
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
#include <machine/regnum.h>
#include "opt_cputype.h"
@ -54,14 +54,14 @@
.set noreorder # Noreorder is default style!
LEAF(set_intr_mask)
li t0, SR_INT_MASK # 1 means masked so invert.
li t0, MIPS_SR_INT_MASK # 1 means masked so invert.
not a0, a0 # 1 means masked so invert.
and a0, t0 # 1 means masked so invert.
mfc0 v0, COP_0_STATUS_REG
li v1, ~SR_INT_MASK
mfc0 v0, MIPS_COP_0_STATUS
li v1, ~MIPS_SR_INT_MASK
and v1, v0
or v1, a0
mtc0 v1, COP_0_STATUS_REG
mtc0 v1, MIPS_COP_0_STATUS
MIPS_CPU_NOP_DELAY
move v0, v1
jr ra
@ -71,8 +71,8 @@ END(set_intr_mask)
LEAF(get_intr_mask)
li a0, 0
mfc0 v0, COP_0_STATUS_REG
li v1, SR_INT_MASK
mfc0 v0, MIPS_COP_0_STATUS
li v1, MIPS_SR_INT_MASK
and v0, v1
or v0, a0
jr ra

28
sys/mips/mips/support.S
View File

@ -1251,11 +1251,13 @@ END(atomic_subtract_8)
/*
* I don't know if these routines have the right number of
* NOPs in it for all processors. XXX
*
* Maybe it would be better to just leave this undefined in that case.
*/
LEAF(atomic_store_64)
mfc0 t1, COP_0_STATUS_REG
and t2, t1, ~SR_INT_ENAB
mtc0 t2, COP_0_STATUS_REG
mfc0 t1, MIPS_COP_0_STATUS
and t2, t1, ~MIPS_SR_INT_IE
mtc0 t2, MIPS_COP_0_STATUS
nop
nop
nop
@ -1266,7 +1268,7 @@ LEAF(atomic_store_64)
sd t0, (a0)
nop
nop
mtc0 t1,COP_0_STATUS_REG
mtc0 t1,MIPS_COP_0_STATUS
nop
nop
nop
@ -1276,9 +1278,9 @@ LEAF(atomic_store_64)
END(atomic_store_64)
LEAF(atomic_load_64)
mfc0 t1, COP_0_STATUS_REG
and t2, t1, ~SR_INT_ENAB
mtc0 t2, COP_0_STATUS_REG
mfc0 t1, MIPS_COP_0_STATUS
and t2, t1, ~MIPS_SR_INT_IE
mtc0 t2, MIPS_COP_0_STATUS
nop
nop
nop
@ -1289,7 +1291,7 @@ LEAF(atomic_load_64)
sd t0, (a1)
nop
nop
mtc0 t1,COP_0_STATUS_REG
mtc0 t1,MIPS_COP_0_STATUS
nop
nop
nop
@ -1355,13 +1357,13 @@ esym: .word 0
.text
LEAF(breakpoint)
break BREAK_SOVER_VAL
break MIPS_BREAK_SOVER_VAL
jr ra
nop
END(breakpoint)
LEAF(setjmp)
mfc0 v0, COP_0_STATUS_REG # Later the "real" spl value!
mfc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
REG_S s0, (SZREG * PREG_S0)(a0)
REG_S s1, (SZREG * PREG_S1)(a0)
REG_S s2, (SZREG * PREG_S2)(a0)
@ -1391,7 +1393,7 @@ LEAF(longjmp)
REG_L s7, (SZREG * PREG_S7)(a0)
REG_L s8, (SZREG * PREG_S8)(a0)
REG_L sp, (SZREG * PREG_SP)(a0)
mtc0 v0, COP_0_STATUS_REG # Later the "real" spl value!
mtc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
ITLBNOPFIX
jr ra
li v0, 1 # longjmp return
@ -1438,14 +1440,14 @@ END(casuptr)
*/
LEAF(octeon_enable_shadow)
li t1, 0x0000000f
mtc0 t1, COP_0_INFO
mtc0 t1, MIPS_COP_0_INFO
jr ra
nop
END(octeon_enable_shadow)
LEAF(octeon_get_shadow)
mfc0 v0, COP_0_INFO
mfc0 v0, MIPS_COP_0_INFO
jr ra
nop
END(octeon_get_shadow)

88
sys/mips/mips/swtch.S
View File

@ -115,9 +115,9 @@ LEAF(fork_trampoline)
DO_AST
mfc0 v0, COP_0_STATUS_REG
and v0, ~(SR_INT_ENAB)
mtc0 v0, COP_0_STATUS_REG # disable interrupts
mfc0 v0, MIPS_COP_0_STATUS
and v0, ~(MIPS_SR_INT_IE)
mtc0 v0, MIPS_COP_0_STATUS # disable interrupts
COP0_SYNC
/*
* The use of k1 for storing the PCB pointer must be done only
@ -135,7 +135,7 @@ LEAF(fork_trampoline)
RESTORE_U_PCB_REG(a0, PC, k1)
RESTORE_U_PCB_REG(AT, AST, k1)
RESTORE_U_PCB_REG(v0, V0, k1)
MTC0 a0, COP_0_EXC_PC # set return address
MTC0 a0, MIPS_COP_0_EXC_PC # set return address
RESTORE_U_PCB_REG(v1, V1, k1)
RESTORE_U_PCB_REG(a0, A0, k1)
@ -165,12 +165,12 @@ LEAF(fork_trampoline)
RESTORE_U_PCB_REG(s8, S8, k1)
RESTORE_U_PCB_REG(ra, RA, k1)
RESTORE_U_PCB_REG(sp, SP, k1)
li k1, ~SR_INT_MASK
li k1, ~MIPS_SR_INT_MASK
and k0, k0, k1
mfc0 k1, COP_0_STATUS_REG
and k1, k1, SR_INT_MASK
mfc0 k1, MIPS_COP_0_STATUS
and k1, k1, MIPS_SR_INT_MASK
or k0, k0, k1
mtc0 k0, COP_0_STATUS_REG # switch to user mode (when eret...)
mtc0 k0, MIPS_COP_0_STATUS # switch to user mode (when eret...)
HAZARD_DELAY
sync
eret
@ -189,7 +189,7 @@ LEAF(savectx)
SAVE_U_PCB_CONTEXT(s1, PREG_S1, a0)
SAVE_U_PCB_CONTEXT(s2, PREG_S2, a0)
SAVE_U_PCB_CONTEXT(s3, PREG_S3, a0)
mfc0 v0, COP_0_STATUS_REG
mfc0 v0, MIPS_COP_0_STATUS
SAVE_U_PCB_CONTEXT(s4, PREG_S4, a0)
SAVE_U_PCB_CONTEXT(s5, PREG_S5, a0)
SAVE_U_PCB_CONTEXT(s6, PREG_S6, a0)
@ -217,11 +217,11 @@ LEAF(savectx)
END(savectx)
NON_LEAF(mips_cpu_throw, CALLFRAME_SIZ, ra)
mfc0 t0, COP_0_STATUS_REG # t0 = saved status register
mfc0 t0, MIPS_COP_0_STATUS # t0 = saved status register
nop
nop
and a3, t0, ~(SR_INT_ENAB)
mtc0 a3, COP_0_STATUS_REG # Disable all interrupts
and a3, t0, ~(MIPS_SR_INT_IE)
mtc0 a3, MIPS_COP_0_STATUS # Disable all interrupts
ITLBNOPFIX
j mips_sw1 # We're not interested in old
# thread's context, so jump
@ -237,11 +237,11 @@ END(mips_cpu_throw)
* Find the highest priority process and resume it.
*/
NON_LEAF(cpu_switch, CALLFRAME_SIZ, ra)
mfc0 t0, COP_0_STATUS_REG # t0 = saved status register
mfc0 t0, MIPS_COP_0_STATUS # t0 = saved status register
nop
nop
and a3, t0, ~(SR_INT_ENAB)
mtc0 a3, COP_0_STATUS_REG # Disable all interrupts
and a3, t0, ~(MIPS_SR_INT_IE)
mtc0 a3, MIPS_COP_0_STATUS # Disable all interrupts
ITLBNOPFIX
beqz a0, mips_sw1
move a3, a0
@ -304,11 +304,11 @@ blocked_loop:
* NOTE: This is hard coded to UPAGES == 2.
* Also, there should be no TLB faults at this point.
*/
MTC0 v0, COP_0_TLB_HI # VPN = va
MTC0 v0, MIPS_COP_0_TLB_HI # VPN = va
HAZARD_DELAY
tlbp # probe VPN
HAZARD_DELAY
mfc0 s0, COP_0_TLB_INDEX
mfc0 s0, MIPS_COP_0_TLB_INDEX
HAZARD_DELAY
PTR_LI t1, MIPS_KSEG0_START # invalidate tlb entry
@ -316,21 +316,21 @@ blocked_loop:
nop
sll s0, PAGE_SHIFT + 1
addu t1, s0
MTC0 t1, COP_0_TLB_HI
mtc0 zero, COP_0_TLB_LO0
mtc0 zero, COP_0_TLB_LO1
MTC0 t1, MIPS_COP_0_TLB_HI
mtc0 zero, MIPS_COP_0_TLB_LO0
mtc0 zero, MIPS_COP_0_TLB_LO1
HAZARD_DELAY
tlbwi
HAZARD_DELAY
MTC0 v0, COP_0_TLB_HI # set VPN again
MTC0 v0, MIPS_COP_0_TLB_HI # set VPN again
entry0set:
/* SMP!! - Works only for unshared TLB case - i.e. no v-cpus */
mtc0 zero, COP_0_TLB_INDEX # TLB entry #0
mtc0 zero, MIPS_COP_0_TLB_INDEX # TLB entry #0
HAZARD_DELAY
mtc0 a1, COP_0_TLB_LO0 # upte[0]
mtc0 a1, MIPS_COP_0_TLB_LO0 # upte[0]
HAZARD_DELAY
mtc0 a2, COP_0_TLB_LO1 # upte[1]
mtc0 a2, MIPS_COP_0_TLB_LO1 # upte[1]
HAZARD_DELAY
tlbwi # set TLB entry #0
HAZARD_DELAY
@ -363,11 +363,11 @@ sw2:
* In case there are CPU-specific registers that need
* to be restored with the other registers do so here.
*/
mfc0 t0, COP_0_STATUS_REG
and t0, t0, SR_INT_MASK
and v0, v0, ~SR_INT_MASK
mfc0 t0, MIPS_COP_0_STATUS
and t0, t0, MIPS_SR_INT_MASK
and v0, v0, ~MIPS_SR_INT_MASK
or v0, v0, t0
mtc0 v0, COP_0_STATUS_REG
mtc0 v0, MIPS_COP_0_STATUS
ITLBNOPFIX
j ra
@ -393,9 +393,9 @@ END(cpu_switch)
*----------------------------------------------------------------------------
*/
LEAF(MipsSwitchFPState)
mfc0 t1, COP_0_STATUS_REG # Save old SR
li t0, SR_COP_1_BIT # enable the coprocessor
mtc0 t0, COP_0_STATUS_REG
mfc0 t1, MIPS_COP_0_STATUS # Save old SR
li t0, MIPS_SR_COP_1_BIT # enable the coprocessor
mtc0 t0, MIPS_COP_0_STATUS
ITLBNOPFIX
beq a0, zero, 1f # skip save if NULL pointer
@ -405,9 +405,9 @@ LEAF(MipsSwitchFPState)
* have completed.
*/
PTR_L a0, TD_PCB(a0) # get pointer to pcb for proc
cfc1 t0, FPC_CSR # stall til FP done
cfc1 t0, FPC_CSR # now get status
li t3, ~SR_COP_1_BIT
cfc1 t0, MIPS_FPU_CSR # stall til FP done
cfc1 t0, MIPS_FPU_CSR # now get status
li t3, ~MIPS_SR_COP_1_BIT
RESTORE_U_PCB_REG(t2, PS, a0) # get CPU status register
SAVE_U_PCB_FPSR(t0, FSR_NUM, a0) # save FP status
and t2, t2, t3 # clear COP_1 enable bit
@ -486,11 +486,11 @@ LEAF(MipsSwitchFPState)
RESTORE_U_PCB_FPREG($f30, F30_NUM, a1)
RESTORE_U_PCB_FPREG($f31, F31_NUM, a1)
and t0, t0, ~FPC_EXCEPTION_BITS
ctc1 t0, FPC_CSR
and t0, t0, ~MIPS_FPU_EXCEPTION_BITS
ctc1 t0, MIPS_FPU_CSR
nop
mtc0 t1, COP_0_STATUS_REG # Restore the status register.
mtc0 t1, MIPS_COP_0_STATUS # Restore the status register.
ITLBNOPFIX
j ra
nop
@ -515,9 +515,9 @@ END(MipsSwitchFPState)
*/
LEAF(MipsSaveCurFPState)
PTR_L a0, TD_PCB(a0) # get pointer to pcb for thread
mfc0 t1, COP_0_STATUS_REG # Disable interrupts and
li t0, SR_COP_1_BIT # enable the coprocessor
mtc0 t0, COP_0_STATUS_REG
mfc0 t1, MIPS_COP_0_STATUS # Disable interrupts and
li t0, MIPS_SR_COP_1_BIT # enable the coprocessor
mtc0 t0, MIPS_COP_0_STATUS
ITLBNOPFIX
GET_CPU_PCPU(a1)
PTR_S zero, PC_FPCURTHREAD(a1) # indicate state has been saved
@ -526,10 +526,10 @@ LEAF(MipsSaveCurFPState)
* have completed.
*/
RESTORE_U_PCB_REG(t2, PS, a0) # get CPU status register
li t3, ~SR_COP_1_BIT
li t3, ~MIPS_SR_COP_1_BIT
and t2, t2, t3 # clear COP_1 enable bit
cfc1 t0, FPC_CSR # stall til FP done
cfc1 t0, FPC_CSR # now get status
cfc1 t0, MIPS_FPU_CSR # stall til FP done
cfc1 t0, MIPS_FPU_CSR # now get status
SAVE_U_PCB_REG(t2, PS, a0) # save new status register
SAVE_U_PCB_FPSR(t0, FSR_NUM, a0) # save FP status
/*
@ -568,7 +568,7 @@ LEAF(MipsSaveCurFPState)
SAVE_U_PCB_FPREG($f30, F30_NUM, a0)
SAVE_U_PCB_FPREG($f31, F31_NUM, a0)
mtc0 t1, COP_0_STATUS_REG # Restore the status register.
mtc0 t1, MIPS_COP_0_STATUS # Restore the status register.
ITLBNOPFIX
j ra
nop

28
sys/mips/mips/trap.c
View File

@ -289,7 +289,7 @@ trap(struct trapframe *trapframe)
trapdebug_enter(trapframe, 0);
type = (trapframe->cause & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT;
type = (trapframe->cause & MIPS3_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
if (TRAPF_USERMODE(trapframe)) {
type |= T_USER;
usermode = 1;
@ -302,8 +302,8 @@ trap(struct trapframe *trapframe)
* was off disable all so we don't accidently enable it when doing a
* return to userland.
*/
if (trapframe->sr & SR_INT_ENAB) {
set_intr_mask(~(trapframe->sr & ALL_INT_MASK));
if (trapframe->sr & MIPS_SR_INT_IE) {
set_intr_mask(~(trapframe->sr & MIPS_SR_INT_MASK));
intr_enable();
} else {
intr_disable();
@ -827,7 +827,8 @@ trap(struct trapframe *trapframe)
p->p_comm, p->p_pid, instr, trapframe->pc,
p->p_md.md_ss_addr, p->p_md.md_ss_instr); /* XXX */
#endif
if (td->td_md.md_ss_addr != va || instr != BREAK_SSTEP) {
if (td->td_md.md_ss_addr != va ||
instr != MIPS_BREAK_SSTEP) {
i = SIGTRAP;
addr = trapframe->pc;
break;
@ -897,13 +898,13 @@ trap(struct trapframe *trapframe)
case T_COP_UNUSABLE + T_USER:
#if !defined(CPU_HAVEFPU)
/* FP (COP1) instruction */
if ((trapframe->cause & CR_COP_ERR) == 0x10000000) {
if ((trapframe->cause & MIPS_CR_COP_ERR) == 0x10000000) {
log_illegal_instruction("COP1_UNUSABLE", trapframe);
i = SIGILL;
break;
}
#endif
if ((trapframe->cause & CR_COP_ERR) != 0x10000000) {
if ((trapframe->cause & MIPS_CR_COP_ERR) != 0x10000000) {
log_illegal_instruction("COPn_UNUSABLE", trapframe);
i = SIGILL; /* only FPU instructions allowed */
break;
@ -911,7 +912,7 @@ trap(struct trapframe *trapframe)
addr = trapframe->pc;
MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
PCPU_SET(fpcurthread, td);
td->td_frame->sr |= SR_COP_1_BIT;
td->td_frame->sr |= MIPS_SR_COP_1_BIT;
td->td_md.md_flags |= MDTD_FPUSED;
goto out;
@ -1047,10 +1048,13 @@ trapDump(char *msg)
break;
printf("%s: ADR %jx PC %jx CR %jx SR %jx\n",
trap_type[(trp->cause & CR_EXC_CODE) >> CR_EXC_CODE_SHIFT],
(intmax_t)trp->vadr, (intmax_t)trp->pc, (intmax_t)trp->cause, (intmax_t)trp->status);
trap_type[(trp->cause & MIPS3_CR_EXC_CODE) >>
MIPS_CR_EXC_CODE_SHIFT],
(intmax_t)trp->vadr, (intmax_t)trp->pc,
(intmax_t)trp->cause, (intmax_t)trp->status);
printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra, (intmax_t)trp->sp, (int)trp->code);
printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra,
(intmax_t)trp->sp, (int)trp->code);
}
intr_restore(s);
}
@ -1178,9 +1182,9 @@ MipsEmulateBranch(struct trapframe *framePtr, uintptr_t instPC, int fpcCSR,
case OP_BCx:
case OP_BCy:
if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
condition = fpcCSR & FPC_COND_BIT;
condition = fpcCSR & MIPS_FPU_COND_BIT;
else
condition = !(fpcCSR & FPC_COND_BIT);
condition = !(fpcCSR & MIPS_FPU_COND_BIT);
if (condition)
retAddr = GetBranchDest(instPC, inst);
else

16
sys/mips/mips/vm_machdep.c
View File

@ -148,7 +148,8 @@ cpu_fork(register struct thread *td1,register struct proc *p2,
pcb2->pcb_context[PCB_REG_S0] = (register_t)(intptr_t)fork_return;
pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td2;
pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td2->td_frame;
pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | SR_INT_MASK) & mips_rd_status();
pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | MIPS_SR_INT_MASK) &
mips_rd_status();
/*
* FREEBSD_DEVELOPERS_FIXME:
* Setup any other CPU-Specific registers (Not MIPS Standard)
@ -160,7 +161,7 @@ cpu_fork(register struct thread *td1,register struct proc *p2,
td2->td_md.md_saved_intr = MIPS_SR_INT_IE;
td2->td_md.md_spinlock_count = 1;
#ifdef TARGET_OCTEON
pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
#endif
}
@ -350,11 +351,12 @@ cpu_set_upcall(struct thread *td, struct thread *td0)
pcb2->pcb_context[PCB_REG_S1] = (register_t)(intptr_t)td;
pcb2->pcb_context[PCB_REG_S2] = (register_t)(intptr_t)td->td_frame;
/* Dont set IE bit in SR. sched lock release will take care of it */
pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | SR_INT_MASK) & mips_rd_status();
pcb2->pcb_context[PCB_REG_SR] = (MIPS_SR_KX | MIPS_SR_INT_MASK) &
mips_rd_status();
#ifdef TARGET_OCTEON
pcb2->pcb_context[PCB_REG_SR] |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT |
MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX;
#endif
/*
@ -369,7 +371,7 @@ cpu_set_upcall(struct thread *td, struct thread *td0)
#if 0
/* Maybe we need to fix this? */
td->td_md.md_saved_sr = ( (MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT) |
(MIPS32_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX) |
(MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX | MIPS_SR_SX) |
(MIPS_SR_INT_IE | MIPS_HARD_INT_MASK));
#endif
}
@ -412,10 +414,10 @@ cpu_set_upcall_kse(struct thread *td, void (*entry)(void *), void *arg,
/*
* Keep interrupt mask
*/
tf->sr = SR_KSU_USER | SR_EXL | (SR_INT_MASK & mips_rd_status()) |
tf->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | (MIPS_SR_INT_MASK & mips_rd_status()) |
MIPS_SR_INT_IE;
#ifdef TARGET_OCTEON
tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS32_SR_PX | MIPS_SR_UX |
tf->sr |= MIPS_SR_INT_IE | MIPS_SR_COP_0_BIT | MIPS_SR_PX | MIPS_SR_UX |
MIPS_SR_KX;
#endif
/* tf->sr |= (ALL_INT_MASK & idle_mask) | SR_INT_ENAB; */