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mirror of https://git.FreeBSD.org/src.git synced 2025-01-01 12:19:28 +00:00

Partially revert r215182. There appears to be a silicon bug on the 970

that causes AP bringup to fail if some of the Cell HID-register code
is anywhere in the instruction stream. Pending a better solution, cache
performance on SMP Cell systems running without a hypervisor will be
suboptimal.
This commit is contained in:
Nathan Whitehorn 2010-11-12 20:26:34 +00:00
parent e97af4eedf
commit cebdaa5881
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=215197

View File

@ -228,8 +228,8 @@ cpudep_save_config(void *dummy)
powerpc_sync();
break;
#ifdef __powerpc64__
case IBMCELLBE:
#ifdef NOTYET /* Causes problems if in instruction stream on 970 */
if (mfmsr() & PSL_HV) {
bsp_state[0] = mfspr(SPR_HID0);
bsp_state[1] = mfspr(SPR_HID1);
@ -238,11 +238,11 @@ cpudep_save_config(void *dummy)
bsp_state[4] = mfspr(SPR_CELL_TSCR);
}
#endif
bsp_state[5] = mfspr(SPR_CELL_TSRL);
break;
#endif
case MPC7450:
case MPC7455:
case MPC7457:
@ -303,8 +303,8 @@ cpudep_ap_setup()
powerpc_sync();
break;
#ifdef __powerpc64__
case IBMCELLBE:
#ifdef NOTYET /* Causes problems if in instruction stream on 970 */
if (mfmsr() & PSL_HV) {
mtspr(SPR_HID0, bsp_state[0]);
mtspr(SPR_HID1, bsp_state[1]);
@ -313,11 +313,11 @@ cpudep_ap_setup()
mtspr(SPR_CELL_TSCR, bsp_state[4]);
}
#endif
mtspr(SPR_CELL_TSRL, bsp_state[5]);
break;
#endif
case MPC7450:
case MPC7455:
case MPC7457: