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Code Issues Releases Activity

o) Fix the intr_* functions to not spam the whole status register, just the IE

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bit.
o) Remove some unused inlines.
o) Generate CP0 access functions for 64-bit TLB registers when building for
   n64.
o) Add an inline function version of the COP0_SYNC macro.
This commit is contained in:
Juli Mallett 2010-04-16 23:46:30 +00:00
parent 4e859425ae
commit d0985cfb41
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=206713
1 changed files with 45 additions and 56 deletions
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101
sys/mips/include/cpufunc.h
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@ -1,5 +1,29 @@
/* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
/*-
* Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
*
@ -58,15 +82,17 @@ mips_barrier(void)
: : : "memory");
}
static __inline void
mips_cp0_sync(void)
{
__asm __volatile (__XSTRING(COP0_SYNC));
}
static __inline void
mips_wbflush(void)
{
__asm __volatile ("sync" : : : "memory");
mips_barrier();
#if 0
__asm __volatile("mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
: : "r" (flag));
#endif
}
static __inline void
@ -82,54 +108,7 @@ mips_write_membar(void)
}
#ifdef _KERNEL
static __inline void
mips_tlbp(void)
{
__asm __volatile ("tlbp");
mips_barrier();
#if 0
register_t ret;
register_t tmp;
__asm __volatile("mfc0 %0, $12\n" /* MIPS_COP_0_STATUS */
"and %1, %0, $~1\n" /* MIPS_SR_INT_IE */
"mtc0 %1, $12\n" /* MIPS_COP_0_STATUS */
: "=r" (ret), "=r" (tmp));
return (ret);
#endif
}
static __inline void
mips_tlbr(void)
{
__asm __volatile ("tlbr");
mips_barrier();
}
static __inline void
mips_tlbwi(void)
{
__asm __volatile ("tlbwi");
mips_barrier();
#if 0
__asm __volatile("mfc %0, $12\n" /* MIPS_COP_0_STATUS */
"or %0, %0, $1\n" /* MIPS_SR_INT_IE */
"mtc0 %0, $12\n" /* MIPS_COP_0_STATUS */
: "=r" (tmp));
#endif
}
static __inline void
mips_tlbwr(void)
{
__asm __volatile ("tlbwr");
mips_barrier();
}
#if 0 /* XXX mips64 */
#if defined(__mips_n32) || defined(__mips_n64)
#define MIPS_RDRW64_COP0(n,r) \
static __inline uint64_t \
mips_rd_ ## n (void) \
@ -152,10 +131,12 @@ mips_wr_ ## n (uint64_t a0) \
mips_barrier(); \
} struct __hack
#if defined(__mips_n64)
MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
#endif
MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
#undef MIPS_RDRW64_COP0
@ -230,12 +211,15 @@ MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
/* XXX: Some of these registers are specific to MIPS32. */
#if !defined(__mips_n64)
MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
MIPS_RDRW32_COP0(entrylow, MIPS_COP_0_TLB_LOW);
MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
#endif
MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
/* XXX 64-bit? */
MIPS_RDRW32_COP0_SEL(prid, MIPS_COP_0_PRID, 1);
MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 1);
MIPS_RDRW32_COP0_SEL(watchlo, MIPS_COP_0_WATCH_LO, 2);
@ -250,7 +234,6 @@ MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 1);
MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 2);
MIPS_RDRW32_COP0_SEL(perfcnt, MIPS_COP_0_PERFCNT, 3);
#undef MIPS_RDRW32_COP0
static __inline register_t
@ -261,7 +244,7 @@ intr_disable(void)
s = mips_rd_status();
mips_wr_status(s & ~MIPS_SR_INT_IE);
return (s);
return (s & MIPS_SR_INT_IE);
}
static __inline register_t
@ -275,7 +258,13 @@ intr_enable(void)
return (s);
}
#define intr_restore(s) mips_wr_status((s))
static __inline void
intr_restore(register_t ie)
{
if (ie == MIPS_SR_INT_IE) {
intr_enable();
}
}
static __inline void
breakpoint(void)