mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-17 15:27:36 +00:00
Mostly rewrite the imx i2c driver. This started out as an attempt to fix
one specific problem: the driver didn't check for ACK/NAK after writing a slave address byte to the bus, and some slaves signal that they are busy (such as when completing an internal write to flash memory) by sending a NAK in response to being addressed. While working on that problem I discovered that the driver's handling of error conditions in general didn't match the state transition diagram in the reference manual, and making that right resulted in a lot of code reorganization. Along the way various other changes also happened... - Remove a mutex that wasn't protecting anything. - Remove some mystery DELAY()s, document the few that remain. - Use pause_sbt(9) to yield the processor for the bulk of the time it takes to transfer each byte rather than busy-polling the whole time. - Disable the controller when no transfers are in progress; since we don't operate in slave mode, there's no reason to run the hardware. - Remove a bunch of unecessary code from probe().
This commit is contained in:
Ian Lepore
parent
c8cbf0d5ea
commit
d2c05e201f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=289091
@ -1,6 +1,7 @@
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/*-
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* Copyright (C) 2008-2009 Semihalf, Michal Hajduk
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* Copyright (c) 2012, 2013 The FreeBSD Foundation
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* Copyright (c) 2015 Ian Lepore <ian@FreeBSD.org>
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* All rights reserved.
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*
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* Portions of this software were developed by Oleksandr Rybalko
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@ -28,6 +29,19 @@
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* SUCH DAMAGE.
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*/
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/*
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* I2C driver for Freescale i.MX hardware.
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*
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* Note that the hardware is capable of running as both a master and a slave.
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* This driver currently implements only master-mode operations.
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*
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* This driver supports multi-master i2c busses, by detecting bus arbitration
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* loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of
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* retries if some other master jumps onto the bus and interrupts one of our
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* transfer cycles resulting in arbitration loss in mid-transfer. The caller
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* must handle retries in a way that makes sense for the slave being addressed.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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@ -43,9 +57,6 @@ __FBSDID("$FreeBSD$");
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <arm/freescale/imx/imx_ccmvar.h>
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#include <dev/iicbus/iiconf.h>
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@ -108,13 +119,6 @@ static struct clkdiv clkdiv_table[] = {
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{ 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f}
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};
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#ifdef DEBUG
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#define debugf(fmt, args...) do { printf("%s(): ", __func__); \
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printf(fmt,##args); } while (0)
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#else
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#define debugf(fmt, args...)
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#endif
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static struct ofw_compat_data compat_data[] = {
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{"fsl,imx6q-i2c", 1},
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{"fsl,imx-i2c", 1},
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@ -125,10 +129,8 @@ struct i2c_softc {
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device_t dev;
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device_t iicbus;
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struct resource *res;
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struct mtx mutex;
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int rid;
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bus_space_handle_t bsh;
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bus_space_tag_t bst;
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sbintime_t byte_time_sbt;
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};
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static phandle_t i2c_get_node(device_t, device_t);
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@ -158,7 +160,7 @@ static device_method_t i2c_methods[] = {
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DEVMETHOD(iicbus_write, i2c_write),
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DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
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{ 0, 0 }
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DEVMETHOD_END
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};
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static driver_t i2c_driver = {
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@ -184,14 +186,14 @@ static __inline void
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i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val)
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{
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bus_space_write_1(sc->bst, sc->bsh, off, val);
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bus_write_1(sc->res, off, val);
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}
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static __inline uint8_t
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i2c_read_reg(struct i2c_softc *sc, bus_size_t off)
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{
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return (bus_space_read_1(sc->bst, sc->bsh, off));
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return (bus_read_1(sc->res, off));
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}
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static __inline void
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@ -204,60 +206,77 @@ i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask)
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i2c_write_reg(sc, off, status);
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}
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/* Wait for transfer interrupt flag */
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/* Wait for bus to become busy or not-busy. */
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static int
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wait_for_iif(struct i2c_softc *sc)
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wait_for_busbusy(struct i2c_softc *sc, int wantbusy)
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{
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int retry;
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int retry, srb;
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retry = 1000;
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while (retry --) {
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if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MIF)
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srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB;
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if ((srb && wantbusy) || (!srb && !wantbusy))
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return (IIC_NOERR);
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DELAY(10);
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DELAY(1);
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}
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return (IIC_ETIMEOUT);
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}
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/* Wait for free bus */
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/* Wait for transfer to complete, optionally check RXAK. */
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static int
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wait_for_nibb(struct i2c_softc *sc)
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wait_for_xfer(struct i2c_softc *sc, int checkack)
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{
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int retry;
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int retry, sr;
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retry = 1000;
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/*
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* Sleep for about the time it takes to transfer a byte (with precision
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* set to tolerate 5% oversleep). We calculate the approximate byte
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* transfer time when we set the bus speed divisor. Slaves are allowed
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* to do clock-stretching so the actual transfer time can be larger, but
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* this gets the bulk of the waiting out of the way without tying up the
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* processor the whole time.
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*/
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pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0);
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retry = 10000;
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while (retry --) {
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if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0)
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return (IIC_NOERR);
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DELAY(10);
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sr = i2c_read_reg(sc, I2C_STATUS_REG);
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if (sr & I2CSR_MIF) {
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if (sr & I2CSR_MAL)
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return (IIC_EBUSBSY);
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else if (checkack && (sr & I2CSR_RXAK))
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return (IIC_ENOACK);
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else
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return (IIC_NOERR);
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}
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DELAY(1);
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}
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return (IIC_ETIMEOUT);
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}
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/* Wait for transfer complete+interrupt flag */
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/*
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* Implement the error handling shown in the state diagram of the imx6 reference
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* manual. If there was an error, then:
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* - Clear master mode (MSTA and MTX).
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* - Wait for the bus to become free or for a timeout to happen.
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* - Disable the controller.
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*/
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static int
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wait_for_icf(struct i2c_softc *sc)
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i2c_error_handler(struct i2c_softc *sc, int error)
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{
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int retry;
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retry = 1000;
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while (retry --) {
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if ((i2c_read_reg(sc, I2C_STATUS_REG) &
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(I2CSR_MCF|I2CSR_MIF)) == (I2CSR_MCF|I2CSR_MIF))
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return (IIC_NOERR);
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DELAY(10);
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if (error != 0) {
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i2c_write_reg(sc, I2C_STATUS_REG, 0);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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wait_for_busbusy(sc, false);
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i2c_write_reg(sc, I2C_CONTROL_REG, 0);
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}
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return (IIC_ETIMEOUT);
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return (error);
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}
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static int
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i2c_probe(device_t dev)
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{
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struct i2c_softc *sc;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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@ -265,23 +284,7 @@ i2c_probe(device_t dev)
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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sc = device_get_softc(dev);
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sc->rid = 0;
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
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RF_ACTIVE);
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if (sc->res == NULL) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->bst = rman_get_bustag(sc->res);
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sc->bsh = rman_get_bushandle(sc->res);
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/* Enable I2C */
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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bus_release_resource(dev, SYS_RES_MEMORY, sc->rid, sc->res);
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device_set_desc(dev, "Freescale i.MX I2C bus controller");
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device_set_desc(dev, "Freescale i.MX I2C");
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return (BUS_PROBE_DEFAULT);
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}
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@ -295,28 +298,21 @@ i2c_attach(device_t dev)
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sc->dev = dev;
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sc->rid = 0;
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mtx_init(&sc->mutex, device_get_nameunit(dev), "I2C", MTX_DEF);
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sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid,
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RF_ACTIVE);
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if (sc->res == NULL) {
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device_printf(dev, "could not allocate resources");
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mtx_destroy(&sc->mutex);
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return (ENXIO);
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}
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sc->bst = rman_get_bustag(sc->res);
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sc->bsh = rman_get_bushandle(sc->res);
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sc->iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->iicbus == NULL) {
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device_printf(dev, "could not add iicbus child");
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mtx_destroy(&sc->mutex);
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return (ENXIO);
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}
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bus_generic_attach(dev);
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return (IIC_NOERR);
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return (0);
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}
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static int
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@ -327,34 +323,20 @@ i2c_repeated_start(device_t dev, u_char slave, int timeout)
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sc = device_get_softc(dev);
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mtx_lock(&sc->mutex);
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i2c_write_reg(sc, I2C_ADDR_REG, slave);
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if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) {
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mtx_unlock(&sc->mutex);
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return (IIC_EBUSBSY);
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return (IIC_EBUSERR);
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}
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/* Set repeated start condition */
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DELAY(10);
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/*
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* Set repeated start condition, delay (per reference manual, min 156nS)
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* before writing slave address, wait for ack after write.
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*/
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i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA);
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DELAY(10);
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/* Clear status */
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DELAY(1);
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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/* Write target address - LSB is R/W bit */
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i2c_write_reg(sc, I2C_DATA_REG, slave);
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error = wait_for_iif(sc);
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/* Clear status */
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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mtx_unlock(&sc->mutex);
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if (error)
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return (error);
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return (IIC_NOERR);
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error = wait_for_xfer(sc, true);
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return (i2c_error_handler(sc, error));
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}
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static int
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@ -365,53 +347,30 @@ i2c_start(device_t dev, u_char slave, int timeout)
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sc = device_get_softc(dev);
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mtx_lock(&sc->mutex);
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i2c_write_reg(sc, I2C_ADDR_REG, slave);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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DELAY(10); /* Delay for controller to sample bus state. */
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if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) {
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mtx_unlock(&sc->mutex);
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return (IIC_EBUSBSY);
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return (i2c_error_handler(sc, IIC_EBUSBSY));
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}
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/* Set start condition */
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i2c_write_reg(sc, I2C_CONTROL_REG,
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I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK);
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DELAY(100);
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i2c_write_reg(sc, I2C_CONTROL_REG,
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I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX | I2CCR_TXAK);
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/* Clear status */
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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/* Write target address - LSB is R/W bit */
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX);
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if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR)
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return (i2c_error_handler(sc, error));
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i2c_write_reg(sc, I2C_STATUS_REG, 0);
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i2c_write_reg(sc, I2C_DATA_REG, slave);
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error = wait_for_iif(sc);
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mtx_unlock(&sc->mutex);
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if (error)
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return (error);
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return (IIC_NOERR);
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error = wait_for_xfer(sc, true);
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return (i2c_error_handler(sc, error));
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}
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static int
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i2c_stop(device_t dev)
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{
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struct i2c_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mutex);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK);
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DELAY(100);
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/* Reset controller if bus still busy after STOP */
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if (wait_for_nibb(sc) == IIC_ETIMEOUT) {
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i2c_write_reg(sc, I2C_CONTROL_REG, 0);
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DELAY(1000);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK);
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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}
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mtx_unlock(&sc->mutex);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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wait_for_busbusy(sc, false);
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i2c_write_reg(sc, I2C_CONTROL_REG, 0);
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return (IIC_NOERR);
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}
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@ -434,19 +393,23 @@ i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr)
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if (clkdiv_table[i].divisor >= div)
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break;
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}
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div = clkdiv_table[i].regcode;
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mtx_lock(&sc->mutex);
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/*
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* Calculate roughly how long it will take to transfer a byte (which
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* requires 9 clock cycles) at the new bus speed. This value is used to
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* pause() while waiting for transfer-complete. With a 66MHz IPG clock
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* and the actual i2c bus speeds that leads to, for nominal 100KHz and
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* 400KHz bus speeds the transfer times are roughly 104uS and 22uS.
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*/
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busfreq = ipgfreq / clkdiv_table[i].divisor;
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sc->byte_time_sbt = SBT_1US * (9000000 / busfreq);
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/*
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* Disable the controller (do the reset), and set the new clock divisor.
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*/
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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i2c_write_reg(sc, I2C_CONTROL_REG, 0x0);
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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DELAY(1000);
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i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)div);
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN);
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DELAY(1000);
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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mtx_unlock(&sc->mutex);
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i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode);
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return (IIC_NOERR);
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}
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@ -459,48 +422,42 @@ i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay)
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sc = device_get_softc(dev);
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*read = 0;
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mtx_lock(&sc->mutex);
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if (len) {
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if (len == 1)
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
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I2CCR_MSTA | I2CCR_TXAK);
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else
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i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
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I2CCR_MSTA);
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/* dummy read */
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/* Dummy read to prime the receiver. */
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i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
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i2c_read_reg(sc, I2C_DATA_REG);
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DELAY(1000);
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}
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error = 0;
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*read = 0;
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while (*read < len) {
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error = wait_for_icf(sc);
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if (error) {
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mtx_unlock(&sc->mutex);
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return (error);
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}
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if ((error = wait_for_xfer(sc, false)) != IIC_NOERR)
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break;
|
||||
i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
|
||||
if ((*read == len - 2) && last) {
|
||||
/* NO ACK on last byte */
|
||||
i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
|
||||
I2CCR_MSTA | I2CCR_TXAK);
|
||||
if (last) {
|
||||
if (*read == len - 2) {
|
||||
/* NO ACK on last byte */
|
||||
i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
|
||||
I2CCR_MSTA | I2CCR_TXAK);
|
||||
} else if (*read == len - 1) {
|
||||
/* Transfer done, signal stop. */
|
||||
i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
|
||||
I2CCR_TXAK);
|
||||
wait_for_busbusy(sc, false);
|
||||
}
|
||||
}
|
||||
|
||||
if ((*read == len - 1) && last) {
|
||||
/* Transfer done, remove master bit */
|
||||
i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN |
|
||||
I2CCR_TXAK);
|
||||
}
|
||||
|
||||
reg = i2c_read_reg(sc, I2C_DATA_REG);
|
||||
*buf++ = reg;
|
||||
(*read)++;
|
||||
}
|
||||
mtx_unlock(&sc->mutex);
|
||||
|
||||
return (IIC_NOERR);
|
||||
return (i2c_error_handler(sc, error));
|
||||
}
|
||||
|
||||
static int
|
||||
@ -510,22 +467,16 @@ i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout)
|
||||
int error;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
*sent = 0;
|
||||
|
||||
mtx_lock(&sc->mutex);
|
||||
error = 0;
|
||||
*sent = 0;
|
||||
while (*sent < len) {
|
||||
i2c_write_reg(sc, I2C_STATUS_REG, 0x0);
|
||||
i2c_write_reg(sc, I2C_DATA_REG, *buf++);
|
||||
|
||||
error = wait_for_iif(sc);
|
||||
if (error) {
|
||||
mtx_unlock(&sc->mutex);
|
||||
return (error);
|
||||
}
|
||||
|
||||
if ((error = wait_for_xfer(sc, true)) != IIC_NOERR)
|
||||
break;
|
||||
(*sent)++;
|
||||
}
|
||||
mtx_unlock(&sc->mutex);
|
||||
|
||||
return (IIC_NOERR);
|
||||
return (i2c_error_handler(sc, error));
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user