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Add a new RMW macro for analog register writes which implements the needed

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wait period between operations.
This commit is contained in:
Adrian Chadd 2011-02-07 21:30:13 +00:00
parent 678b238c85
commit d9a80efdc2
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=218415
1 changed files with 4 additions and 0 deletions
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4
sys/dev/ath/ath_hal/ah_internal.h
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@ -466,6 +466,10 @@ isBigEndian(void)
#define OS_REG_CLR_BIT(_a, _r, _f) \
OS_REG_WRITE(_a, _r, OS_REG_READ(_a, _r) &~ (_f))
/* Analog register writes may require a delay between each one (eg Merlin?) */
#define OS_A_REG_RMW_FIELD(_a, _r, _f, _v) \
do { OS_REG_WRITE(_a, _r, (OS_REG_READ(_a, _r) &~ (_f)) | (((_v) << _f##_S) & (_f))) ; OS_DELAY(100); } while (0)
/* system-configurable parameters */
extern int ath_hal_dma_beacon_response_time; /* in TU's */
extern int ath_hal_sw_beacon_response_time; /* in TU's */