mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-17 15:27:36 +00:00
Make SATA XPT negotiate and enable some additional SATA features, such as:
- device initiated power management (some devices support only this way); - Automatic Partial to Slumber Transition (more power saving); - DMA auto-activation (expected to slightly improve performance). More features could be added later, when hardware supports.
This commit is contained in:
Alexander Motin
parent
f930c0db49
commit
da6808c111
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=207499
@ -2855,6 +2855,10 @@ cts_print(struct cam_device *device, struct ccb_trans_settings *cts)
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fprintf(stdout, "%sNumber of tags: %d\n", pathstr,
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sata->tags);
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}
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if ((sata->valid & CTS_SATA_VALID_CAPS) != 0) {
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fprintf(stdout, "%sSATA capabilities: %08x\n", pathstr,
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sata->caps);
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}
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}
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if (cts->protocol == PROTO_SCSI) {
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struct ccb_trans_settings_scsi *scsi=
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@ -101,6 +101,7 @@ struct pmp_softc {
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int events;
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#define PMP_EV_RESET 1
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#define PMP_EV_RESCAN 2
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u_int caps;
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struct task sysctl_task;
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struct sysctl_ctx_list sysctl_ctx;
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struct sysctl_oid *sysctl_tree;
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@ -457,6 +458,14 @@ pmpstart(struct cam_periph *periph, union ccb *start_ccb)
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ata_pm_read_cmd(ataio, 2, 15);
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break;
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case PMP_STATE_PRECONFIG:
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/* Get/update host SATA capabilities. */
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bzero(&cts, sizeof(cts));
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xpt_setup_ccb(&cts.ccb_h, periph->path, CAM_PRIORITY_NONE);
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cts.ccb_h.func_code = XPT_GET_TRAN_SETTINGS;
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cts.type = CTS_TYPE_CURRENT_SETTINGS;
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xpt_action((union ccb *)&cts);
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if (cts.xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
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softc->caps = cts.xport_specific.sata.caps;
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cam_fill_ataio(ataio,
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pmp_retry_count,
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pmpdone,
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@ -644,14 +653,16 @@ pmpdone(struct cam_periph *periph, union ccb *done_ccb)
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(done_ccb->ataio.res.lba_mid << 16) +
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(done_ccb->ataio.res.lba_low << 8) +
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done_ccb->ataio.res.sector_count;
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if ((res & 0xf0f) == 0x103 && (res & 0x0f0) != 0) {
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if (((res & 0xf0f) == 0x103 && (res & 0x0f0) != 0) ||
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(res & 0x600) != 0) {
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if (bootverbose) {
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printf("%s%d: port %d status: %08x\n",
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periph->periph_name, periph->unit_number,
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softc->pm_step, res);
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}
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/* Report device speed. */
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if (xpt_create_path(&dpath, periph,
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/* Report device speed if it is online. */
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if ((res & 0xf0f) == 0x103 &&
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xpt_create_path(&dpath, periph,
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xpt_path_path_id(periph->path),
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softc->pm_step, 0) == CAM_REQ_CMP) {
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bzero(&cts, sizeof(cts));
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@ -660,6 +671,9 @@ pmpdone(struct cam_periph *periph, union ccb *done_ccb)
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cts.type = CTS_TYPE_CURRENT_SETTINGS;
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cts.xport_specific.sata.revision = (res & 0x0f0) >> 4;
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cts.xport_specific.sata.valid = CTS_SATA_VALID_REVISION;
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cts.xport_specific.sata.caps = softc->caps &
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(CTS_SATA_CAPS_H_PMREQ | CTS_SATA_CAPS_H_DMAAA);
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cts.xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
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xpt_action((union ccb *)&cts);
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xpt_free_path(dpath);
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}
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@ -88,6 +88,9 @@ typedef enum {
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PROBE_IDENTIFY,
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PROBE_SPINUP,
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PROBE_SETMODE,
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PROBE_SETPM,
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PROBE_SETAPST,
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PROBE_SETDMAAA,
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PROBE_SET_MULTI,
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PROBE_INQUIRY,
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PROBE_FULL_INQUIRY,
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@ -101,6 +104,9 @@ static char *probe_action_text[] = {
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"PROBE_IDENTIFY",
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"PROBE_SPINUP",
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"PROBE_SETMODE",
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"PROBE_SETPM",
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"PROBE_SETAPST",
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"PROBE_SETDMAAA",
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"PROBE_SET_MULTI",
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"PROBE_INQUIRY",
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"PROBE_FULL_INQUIRY",
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@ -132,6 +138,7 @@ typedef struct {
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uint32_t pm_prv;
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int restart;
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int spinup;
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u_int caps;
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struct cam_periph *periph;
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} probe_softc;
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@ -393,6 +400,45 @@ probestart(struct cam_periph *periph, union ccb *start_ccb)
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ata_28bit_cmd(ataio, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
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break;
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}
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case PROBE_SETPM:
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cam_fill_ataio(ataio,
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1,
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probedone,
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CAM_DIR_NONE,
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0,
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NULL,
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0,
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30*1000);
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ata_28bit_cmd(ataio, ATA_SETFEATURES,
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(softc->caps & CTS_SATA_CAPS_H_PMREQ) ? 0x10 : 0x90,
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0, 0x03);
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break;
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case PROBE_SETAPST:
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cam_fill_ataio(ataio,
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1,
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probedone,
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CAM_DIR_NONE,
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0,
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NULL,
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0,
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30*1000);
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ata_28bit_cmd(ataio, ATA_SETFEATURES,
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(softc->caps & CTS_SATA_CAPS_H_APST) ? 0x10 : 0x90,
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0, 0x07);
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break;
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case PROBE_SETDMAAA:
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cam_fill_ataio(ataio,
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1,
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probedone,
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CAM_DIR_NONE,
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0,
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NULL,
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0,
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30*1000);
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ata_28bit_cmd(ataio, ATA_SETFEATURES,
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(softc->caps & CTS_SATA_CAPS_H_DMAAA) ? 0x10 : 0x90,
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0, 0x02);
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break;
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case PROBE_SET_MULTI:
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{
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u_int sectors, bytecount;
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@ -685,6 +731,7 @@ probedone(struct cam_periph *periph, union ccb *done_ccb)
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probe_softc *softc;
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struct cam_path *path;
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u_int32_t priority;
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u_int caps;
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int found = 1;
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CAM_DEBUG(done_ccb->ccb_h.path, CAM_DEBUG_TRACE, ("probedone\n"));
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@ -879,6 +926,67 @@ device_fail: if ((!softc->restart) &&
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xpt_schedule(periph, priority);
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return;
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case PROBE_SETMODE:
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if (path->device->transport != XPORT_SATA)
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goto notsata;
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/* Set supported bits. */
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bzero(&cts, sizeof(cts));
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xpt_setup_ccb(&cts.ccb_h, path, CAM_PRIORITY_NONE);
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cts.ccb_h.func_code = XPT_GET_TRAN_SETTINGS;
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cts.type = CTS_TYPE_CURRENT_SETTINGS;
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xpt_action((union ccb *)&cts);
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if (cts.xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
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caps = cts.xport_specific.sata.caps & CTS_SATA_CAPS_H;
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else
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caps = 0;
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if (ident_buf->satacapabilities != 0xffff) {
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if (ident_buf->satacapabilities & ATA_SUPPORT_IFPWRMNGTRCV)
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caps |= CTS_SATA_CAPS_D_PMREQ;
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if (ident_buf->satacapabilities & ATA_SUPPORT_HAPST)
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caps |= CTS_SATA_CAPS_D_APST;
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}
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/* Mask unwanted bits. */
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bzero(&cts, sizeof(cts));
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xpt_setup_ccb(&cts.ccb_h, path, CAM_PRIORITY_NONE);
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cts.ccb_h.func_code = XPT_GET_TRAN_SETTINGS;
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cts.type = CTS_TYPE_USER_SETTINGS;
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xpt_action((union ccb *)&cts);
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if (cts.xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
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caps &= cts.xport_specific.sata.caps;
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/* Store result to SIM. */
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bzero(&cts, sizeof(cts));
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xpt_setup_ccb(&cts.ccb_h, path, CAM_PRIORITY_NONE);
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cts.ccb_h.func_code = XPT_SET_TRAN_SETTINGS;
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cts.type = CTS_TYPE_CURRENT_SETTINGS;
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cts.xport_specific.sata.caps = caps;
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cts.xport_specific.sata.valid = CTS_SATA_VALID_CAPS;
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xpt_action((union ccb *)&cts);
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softc->caps = caps;
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if (ident_buf->satasupport & ATA_SUPPORT_IFPWRMNGT) {
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PROBE_SET_ACTION(softc, PROBE_SETPM);
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xpt_release_ccb(done_ccb);
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xpt_schedule(periph, priority);
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return;
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}
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/* FALLTHROUGH */
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case PROBE_SETPM:
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if (ident_buf->satacapabilities != 0xffff &&
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ident_buf->satacapabilities & ATA_SUPPORT_DAPST) {
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PROBE_SET_ACTION(softc, PROBE_SETAPST);
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xpt_release_ccb(done_ccb);
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xpt_schedule(periph, priority);
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return;
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}
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/* FALLTHROUGH */
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case PROBE_SETAPST:
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if (ident_buf->satasupport & ATA_SUPPORT_AUTOACTIVATE) {
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PROBE_SET_ACTION(softc, PROBE_SETDMAAA);
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xpt_release_ccb(done_ccb);
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xpt_schedule(periph, priority);
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return;
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}
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/* FALLTHROUGH */
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case PROBE_SETDMAAA:
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notsata:
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if (path->device->protocol == PROTO_ATA) {
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PROBE_SET_ACTION(softc, PROBE_SET_MULTI);
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} else {
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@ -964,6 +1072,35 @@ device_fail: if ((!softc->restart) &&
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snprintf(ident_buf->revision, sizeof(ident_buf->revision),
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"%04x", softc->pm_prv);
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path->device->flags |= CAM_DEV_IDENTIFY_DATA_VALID;
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/* Set supported bits. */
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bzero(&cts, sizeof(cts));
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xpt_setup_ccb(&cts.ccb_h, path, CAM_PRIORITY_NONE);
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cts.ccb_h.func_code = XPT_GET_TRAN_SETTINGS;
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cts.type = CTS_TYPE_CURRENT_SETTINGS;
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xpt_action((union ccb *)&cts);
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if (cts.xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
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caps = cts.xport_specific.sata.caps & CTS_SATA_CAPS_H;
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else
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caps = 0;
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/* All PMPs must support PM requests. */
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caps |= CTS_SATA_CAPS_D_PMREQ;
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/* Mask unwanted bits. */
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bzero(&cts, sizeof(cts));
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xpt_setup_ccb(&cts.ccb_h, path, CAM_PRIORITY_NONE);
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cts.ccb_h.func_code = XPT_GET_TRAN_SETTINGS;
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cts.type = CTS_TYPE_USER_SETTINGS;
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xpt_action((union ccb *)&cts);
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if (cts.xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
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caps &= cts.xport_specific.sata.caps;
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/* Store result to SIM. */
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bzero(&cts, sizeof(cts));
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xpt_setup_ccb(&cts.ccb_h, path, CAM_PRIORITY_NONE);
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cts.ccb_h.func_code = XPT_SET_TRAN_SETTINGS;
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cts.type = CTS_TYPE_CURRENT_SETTINGS;
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cts.xport_specific.sata.caps = caps;
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cts.xport_specific.sata.valid = CTS_SATA_VALID_CAPS;
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xpt_action((union ccb *)&cts);
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softc->caps = caps;
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if (periph->path->device->flags & CAM_DEV_UNCONFIGURED) {
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path->device->flags &= ~CAM_DEV_UNCONFIGURED;
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xpt_acquire_device(path->device);
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@ -837,12 +837,21 @@ struct ccb_trans_settings_sata {
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#define CTS_SATA_VALID_PM 0x08
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#define CTS_SATA_VALID_TAGS 0x10
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#define CTS_SATA_VALID_ATAPI 0x20
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#define CTS_SATA_VALID_CAPS 0x40
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int mode; /* Legacy PATA mode */
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u_int bytecount; /* Length of PIO transaction */
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int revision; /* SATA revision */
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u_int pm_present; /* PM is present (XPT->SIM) */
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u_int tags; /* Number of allowed tags */
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u_int atapi; /* Length of ATAPI CDB */
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u_int caps; /* Device and host SATA caps. */
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#define CTS_SATA_CAPS_H 0x0000ffff
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#define CTS_SATA_CAPS_H_PMREQ 0x00000001
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#define CTS_SATA_CAPS_H_APST 0x00000002
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#define CTS_SATA_CAPS_H_DMAAA 0x00000010 /* Auto-activation */
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#define CTS_SATA_CAPS_D 0xffff0000
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#define CTS_SATA_CAPS_D_PMREQ 0x00010000
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#define CTS_SATA_CAPS_D_APST 0x00020000
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};
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/* Get/Set transfer rate/width/disconnection/tag queueing settings */
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@ -111,6 +111,7 @@ static struct {
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#define AHCI_Q_EDGEIS 64
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#define AHCI_Q_SATA2 128
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#define AHCI_Q_NOBSYRES 256
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#define AHCI_Q_NOAA 512
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} ahci_ids[] = {
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{0x43801002, 0x00, "ATI IXP600", 0},
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{0x43901002, 0x00, "ATI IXP700", 0},
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@ -167,75 +168,75 @@ static struct {
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{0x614511ab, 0x00, "Marvell 88SX6145", AHCI_Q_NOFORCE|AHCI_Q_4CH|AHCI_Q_EDGEIS},
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{0x91231b4b, 0x11, "Marvell 88SE912x", AHCI_Q_NOBSYRES},
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{0x91231b4b, 0x00, "Marvell 88SE912x", AHCI_Q_EDGEIS|AHCI_Q_SATA2|AHCI_Q_NOBSYRES},
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{0x044c10de, 0x00, "NVIDIA MCP65", 0},
|
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{0x044d10de, 0x00, "NVIDIA MCP65", 0},
|
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{0x044e10de, 0x00, "NVIDIA MCP65", 0},
|
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{0x044f10de, 0x00, "NVIDIA MCP65", 0},
|
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{0x045c10de, 0x00, "NVIDIA MCP65", 0},
|
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{0x045d10de, 0x00, "NVIDIA MCP65", 0},
|
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{0x045e10de, 0x00, "NVIDIA MCP65", 0},
|
||||
{0x045f10de, 0x00, "NVIDIA MCP65", 0},
|
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{0x055010de, 0x00, "NVIDIA MCP67", 0},
|
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{0x055110de, 0x00, "NVIDIA MCP67", 0},
|
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{0x055210de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055310de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055410de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055510de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055610de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055710de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055810de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055910de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055A10de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x055B10de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x058410de, 0x00, "NVIDIA MCP67", 0},
|
||||
{0x07f010de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f110de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f210de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f310de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f410de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f510de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f610de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f710de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f810de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07f910de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07fa10de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x07fb10de, 0x00, "NVIDIA MCP73", 0},
|
||||
{0x0ad010de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad110de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad210de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad310de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad410de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad510de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad610de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad710de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad810de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ad910de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ada10de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0adb10de, 0x00, "NVIDIA MCP77", 0},
|
||||
{0x0ab410de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0ab510de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0ab610de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0ab710de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0ab810de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0ab910de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0aba10de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0abb10de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0abc10de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0abd10de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0abe10de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0abf10de, 0x00, "NVIDIA MCP79", 0},
|
||||
{0x0d8410de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8510de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8610de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8710de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8810de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8910de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8a10de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8b10de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8c10de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8d10de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8e10de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x0d8f10de, 0x00, "NVIDIA MCP89", 0},
|
||||
{0x044c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x044d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x044e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x044f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x045c10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x045d10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x045e10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x045f10de, 0x00, "NVIDIA MCP65", AHCI_Q_NOAA},
|
||||
{0x055010de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055110de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055210de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055310de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055510de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055610de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055710de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055810de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055910de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055A10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x055B10de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x058410de, 0x00, "NVIDIA MCP67", AHCI_Q_NOAA},
|
||||
{0x07f010de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f110de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f210de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f310de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f410de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f510de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f610de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f710de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f810de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07f910de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07fa10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x07fb10de, 0x00, "NVIDIA MCP73", AHCI_Q_NOAA},
|
||||
{0x0ad010de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad110de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad210de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad310de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad410de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad510de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad610de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad710de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad810de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ad910de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ada10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0adb10de, 0x00, "NVIDIA MCP77", AHCI_Q_NOAA},
|
||||
{0x0ab410de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0ab510de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0ab610de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0ab710de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0ab810de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0ab910de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0aba10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0abb10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0abc10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0abd10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0abe10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0abf10de, 0x00, "NVIDIA MCP79", AHCI_Q_NOAA},
|
||||
{0x0d8410de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8510de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8610de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8710de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8810de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8910de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8a10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8b10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8c10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8d10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8e10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x0d8f10de, 0x00, "NVIDIA MCP89", AHCI_Q_NOAA},
|
||||
{0x33491106, 0x00, "VIA VT8251", 0},
|
||||
{0x62871106, 0x00, "VIA VT8251", 0},
|
||||
{0x11841039, 0x00, "SiS 966", 0},
|
||||
@ -860,7 +861,14 @@ ahci_ch_attach(device_t dev)
|
||||
ch->user[i].mode = 0;
|
||||
ch->user[i].bytecount = 8192;
|
||||
ch->user[i].tags = ch->numslots;
|
||||
ch->user[i].caps = 0;
|
||||
ch->curr[i] = ch->user[i];
|
||||
if (ch->pm_level) {
|
||||
ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
|
||||
CTS_SATA_CAPS_H_APST |
|
||||
CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
|
||||
}
|
||||
ch->user[i].caps |= CTS_SATA_CAPS_H_DMAAA;
|
||||
}
|
||||
rid = ch->unit;
|
||||
if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
||||
@ -1960,7 +1968,8 @@ ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
|
||||
et != AHCI_ERR_TIMEOUT)
|
||||
ahci_rearm_timeout(dev);
|
||||
/* Start PM timer. */
|
||||
if (ch->numrslots == 0 && ch->pm_level > 3) {
|
||||
if (ch->numrslots == 0 && ch->pm_level > 3 &&
|
||||
(ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
|
||||
callout_schedule(&ch->pm_timer,
|
||||
(ch->pm_level == 4) ? hz / 1000 : hz / 8);
|
||||
}
|
||||
@ -2464,6 +2473,8 @@ ahciaction(struct cam_sim *sim, union ccb *ccb)
|
||||
ch->pm_present = cts->xport_specific.sata.pm_present;
|
||||
if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
|
||||
d->atapi = cts->xport_specific.sata.atapi;
|
||||
if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
|
||||
d->caps = cts->xport_specific.sata.caps;
|
||||
ccb->ccb_h.status = CAM_REQ_CMP;
|
||||
break;
|
||||
}
|
||||
@ -2496,9 +2507,24 @@ ahciaction(struct cam_sim *sim, union ccb *ccb)
|
||||
cts->xport_specific.sata.valid |=
|
||||
CTS_SATA_VALID_REVISION;
|
||||
}
|
||||
cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
|
||||
if (ch->pm_level) {
|
||||
if (ch->caps & (AHCI_CAP_PSC | AHCI_CAP_SSC))
|
||||
cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
|
||||
if (ch->caps2 & AHCI_CAP2_APST)
|
||||
cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_APST;
|
||||
}
|
||||
if ((ch->caps & AHCI_CAP_SNCQ) &&
|
||||
(ch->quirks & AHCI_Q_NOAA) == 0)
|
||||
cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_DMAAA;
|
||||
cts->xport_specific.sata.caps &=
|
||||
ch->user[ccb->ccb_h.target_id].caps;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
|
||||
} else {
|
||||
cts->xport_specific.sata.revision = d->revision;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
|
||||
cts->xport_specific.sata.caps = d->caps;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
|
||||
}
|
||||
cts->xport_specific.sata.mode = d->mode;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
|
||||
|
||||
@ -372,6 +372,7 @@ struct ahci_device {
|
||||
u_int bytecount;
|
||||
u_int atapi;
|
||||
u_int tags;
|
||||
u_int caps;
|
||||
};
|
||||
|
||||
/* structure describing an ATA channel */
|
||||
|
||||
@ -448,6 +448,8 @@ siis_ch_attach(device_t dev)
|
||||
ch->user[i].bytecount = 8192;
|
||||
ch->user[i].tags = SIIS_MAX_SLOTS;
|
||||
ch->curr[i] = ch->user[i];
|
||||
if (ch->pm_level)
|
||||
ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ;
|
||||
}
|
||||
mtx_init(&ch->mtx, "SIIS channel lock", NULL, MTX_DEF);
|
||||
rid = ch->unit;
|
||||
@ -1697,6 +1699,8 @@ siisaction(struct cam_sim *sim, union ccb *ccb)
|
||||
}
|
||||
if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
|
||||
d->atapi = cts->xport_specific.sata.atapi;
|
||||
if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
|
||||
d->caps = cts->xport_specific.sata.caps;
|
||||
ccb->ccb_h.status = CAM_REQ_CMP;
|
||||
break;
|
||||
}
|
||||
@ -1729,9 +1733,17 @@ siisaction(struct cam_sim *sim, union ccb *ccb)
|
||||
cts->xport_specific.sata.valid |=
|
||||
CTS_SATA_VALID_REVISION;
|
||||
}
|
||||
cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
|
||||
if (ch->pm_level)
|
||||
cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
|
||||
cts->xport_specific.sata.caps &=
|
||||
ch->user[ccb->ccb_h.target_id].caps;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
|
||||
} else {
|
||||
cts->xport_specific.sata.revision = d->revision;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
|
||||
cts->xport_specific.sata.caps = d->caps;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
|
||||
}
|
||||
cts->xport_specific.sata.mode = d->mode;
|
||||
cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
|
||||
|
||||
@ -358,6 +358,7 @@ struct siis_device {
|
||||
u_int bytecount;
|
||||
u_int atapi;
|
||||
u_int tags;
|
||||
u_int caps;
|
||||
};
|
||||
|
||||
/* structure describing an ATA channel */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user