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Code Issues Releases Activity

Defer allowing async. requests after self ID's have received.

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This should fix some problem of SBP2 device probing.

Prior to rev 1.41, we keep writing the register while bus reset phase.
But in rev 1.41, we ignore successive bus reset events and some chips seem to
clear the register after we write to it.

Tested by: Michael Reifenberger <root@nihil.reifenberger.com>
This commit is contained in:
Hidetoshi Shimokawa 2003-03-03 04:10:56 +00:00
parent 1889afca0c
commit dcae7539cb
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=111787
1 changed files with 6 additions and 7 deletions
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13
sys/dev/firewire/fwohci.c
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@ -1783,13 +1783,6 @@ fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
#endif
fw_busreset(fc);
OWRITE(sc, OHCI_AREQHI, 1 << 31);
/* XXX insecure ?? */
OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
OWRITE(sc, OHCI_PREQLO, 0xffffffff);
OWRITE(sc, OHCI_PREQUPPER, 0x10000);
}
busresetout:
if((stat & OHCI_INT_DMA_IR )){
@ -1857,6 +1850,12 @@ fwohci_intr_body(struct fwohci_softc *sc, u_int32_t stat, int count)
#endif
/* Enable bus reset interrupt */
OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
/* Allow async. request to us */
OWRITE(sc, OHCI_AREQHI, 1 << 31);
/* XXX insecure ?? */
OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
OWRITE(sc, OHCI_PREQLO, 0xffffffff);
OWRITE(sc, OHCI_PREQUPPER, 0x10000);
/*
** Checking whether the node is root or not. If root, turn on
** cycle master.