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Code Issues Releases Activity

Set enable bit when writing the configuration address in configuration

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mode 1. Omission of this bit makes all config register accesses fail in
on recent chip sets ...

(The problem was reported and debug output provided by: Steve Passe)
This commit is contained in:
Stefan Eßer 1997-05-26 21:11:05 +00:00
parent c4ed75ce19
commit e0c57a9615
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=26172
6 changed files with 12 additions and 12 deletions
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4
sys/amd64/pci/pci_bus.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
*
*/
@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT,
outl(CONF1_ADDR_PORT, 0x8000 |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
break;

4
sys/amd64/pci/pci_cfgreg.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
*
*/
@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT,
outl(CONF1_ADDR_PORT, 0x8000 |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
break;

4
sys/i386/isa/pcibus.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
*
*/
@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT,
outl(CONF1_ADDR_PORT, 0x8000 |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
break;

4
sys/i386/pci/pci_bus.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
*
*/
@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT,
outl(CONF1_ADDR_PORT, 0x8000 |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
break;

4
sys/i386/pci/pci_cfgreg.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
*
*/
@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT,
outl(CONF1_ADDR_PORT, 0x8000 |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
break;

4
sys/i386/pci/pci_pir.c
View File

@ -23,7 +23,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* $Id$
* $Id: pcibus.c,v 1.36 1997/05/26 15:08:42 se Exp $
*
*/
@ -59,7 +59,7 @@ pci_cfgenable(unsigned bus, unsigned slot, unsigned func, int reg, int bytes)
&& (reg & (bytes -1)) == 0) {
switch (cfgmech) {
case 1:
outl(CONF1_ADDR_PORT,
outl(CONF1_ADDR_PORT, 0x8000 |
(bus << 16) | (slot << 11) | (func << 8) | reg);
dataport = CONF1_DATA_PORT;
break;