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Add some magic taken from OS X and Linux to support early revision K2
SATA controllers, like those found on the G5 Xserve. Reviewed by: mav
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parent
f3755df16d
commit
e5310f3310
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=198583
@ -41,6 +41,9 @@ __FBSDID("$FreeBSD$");
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#ifdef __powerpc__
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#include <machine/intr_machdep.h>
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#endif
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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@ -106,6 +109,13 @@ static int
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ata_serverworks_status(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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/*
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* Check if this interrupt belongs to our channel.
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*/
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if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
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return (0);
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/*
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* We need to do a 4-byte read on the status reg before the values
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@ -208,8 +218,29 @@ ata_serverworks_ch_attach(device_t dev)
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ch->hw.tf_write = ata_serverworks_tf_write;
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#ifdef __powerpc__
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ch->hw.status = ata_serverworks_status;
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/* Make sure that our interrupt is edge triggered */
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powerpc_config_intr(bus_get_resource_start(device_get_parent(dev),
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SYS_RES_IRQ, 0), INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
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#endif
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if (ctlr->chip->chipid == ATA_K2) {
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/*
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* The revision 1 K2 SATA controller has interesting bugs. Patch them.
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* These magic numbers regulate interrupt delivery in the first few
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* cases and are pure magic in the last case.
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*
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* Values obtained from the Darwin driver.
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*/
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ATA_IDX_OUTB(ch, ATA_BMSTAT_PORT, 0x04);
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ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
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ATA_IDX_OUTL(ch, ATA_SCONTROL, 0x00000300);
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ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0);
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ATA_OUTL(ctlr->r_res2, ch_offset + 0x80,
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ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
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}
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/* chip does not reliably do 64K DMA transfers */
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ch->dma.max_iosize = 64 * DEV_BSIZE;
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