mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-28 16:43:09 +00:00
I'll be making some rather substantial changes to the pci attachment
of the pcic class of devices. Go ahead and move it to the "usual" place. I say "usual" in quotes since it isn't exactly right (not in dev/blah), but it is closer than before.
This commit is contained in:
Warner Losh
parent
804e80065b
commit
e7c00509d5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=76539
@ -1142,6 +1142,7 @@ pccard/pccard.c count card
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pccard/pccard_beep.c optional card
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pccard/pccard_nbk.c optional card
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pccard/pcic.c optional pcic card
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pccard/pcic_pci.c optional pcic card pci
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pci/agp.c optional agp
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pci/agp_if.m optional agp
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pci/agp_intel.c optional agp
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@ -1176,7 +1177,6 @@ pci/meteor.c count meteor pci
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pci/ncr.c optional ncr
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pci/ohci_pci.c optional ohci
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dev/pccbb/pccbb.c optional pccbb
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pci/pcic_p.c optional pcic pci card
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pci/simos.c optional simos
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pci/uhci_pci.c optional uhci
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pci/xrpu.c optional xrpu
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@ -35,7 +35,7 @@
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#include <sys/bus.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <pci/pcic_p.h>
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#include <pccard/pcic_pci.h>
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#include <pccard/i82365.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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442
sys/pci/pcic_p.c
442
sys/pci/pcic_p.c
@ -1,442 +0,0 @@
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/*
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* Copyright (c) 1997 Ted Faber
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice immediately at the beginning of the file, without modification,
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* this list of conditions, and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Absolutely no warranty of function or purpose is made by the author
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* Ted Faber.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <pci/pcic_p.h>
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#include <pccard/i82365.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#define PRVERB(x) if (bootverbose) device_printf x
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/*
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* Set up the CL-PD6832 to look like a ISA based PCMCIA chip (a
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* PD672X). This routine is called once per PCMCIA socket.
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*/
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static void
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pd6832_legacy_init(device_t dev)
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{
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u_long bcr; /* to set interrupts */
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u_short io_port; /* the io_port to map this slot on */
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static int num6832; /* The number of 6832s initialized */
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int unit;
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num6832 = 0;
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unit = device_get_unit(dev);
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/*
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* Some BIOS leave the legacy address uninitialized. This
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* insures that the PD6832 puts itself where the driver will
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* look. We assume that multiple 6832's should be laid out
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* sequentially. We only initialize the first socket's legacy port,
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* the other is a dummy.
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*/
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io_port = PCIC_INDEX_0 + num6832 * CLPD6832_NUM_REGS;
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if (unit == 0)
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pci_write_config(dev, CLPD6832_LEGACY_16BIT_IOADDR,
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io_port & ~CLPD6832_LEGACY_16BIT_IOENABLE, 4);
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/*
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* I think this should be a call to pci_map_port, but that
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* routine won't map regiaters above 0x28, and the register we
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* need to map is 0x44.
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*/
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io_port = pci_read_config(dev, CLPD6832_LEGACY_16BIT_IOADDR, 4) &
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~CLPD6832_LEGACY_16BIT_IOENABLE;
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/*
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* Configure the first I/O window to contain CLPD6832_NUM_REGS
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* words and deactivate the second by setting the limit lower
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* than the base.
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*/
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pci_write_config(dev, CLPD6832_IO_BASE0, io_port | 1, 4);
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pci_write_config(dev, CLPD6832_IO_LIMIT0,
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(io_port + CLPD6832_NUM_REGS) | 1, 4);
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pci_write_config(dev, CLPD6832_IO_BASE1, (io_port + 0x20) | 1, 4);
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pci_write_config(dev, CLPD6832_IO_LIMIT1, io_port | 1, 4);
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/*
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* Set default operating mode (I/O port space) and allocate
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* this socket to the current unit.
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*/
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pci_write_config(dev, PCIR_COMMAND, CLPD6832_COMMAND_DEFAULTS, 4);
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pci_write_config(dev, CLPD6832_SOCKET, unit, 4);
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/*
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* Set up the card inserted/card removed interrupts to come
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* through the isa IRQ.
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*/
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bcr = pci_read_config(dev, CLPD6832_BRIDGE_CONTROL, 4);
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bcr |= (CLPD6832_BCR_ISA_IRQ|CLPD6832_BCR_MGMT_IRQ_ENA);
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pci_write_config(dev, CLPD6832_BRIDGE_CONTROL, bcr, 4);
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/* After initializing 2 sockets, the chip is fully configured */
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if (unit == 1)
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num6832++;
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PRVERB((dev, "CardBus: Legacy PC-card 16bit I/O address [0x%x]\n",
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io_port));
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}
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/*
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* TI1XXX PCI-CardBus Host Adapter specific function code.
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* This function is separated from pcic_pci_attach().
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* Support Device: TI1130,TI1131,TI1250,TI1220.
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* Test Device: TI1221.
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* Takeshi Shibagaki(shiba@jp.freebsd.org).
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*/
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static void
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ti1xxx_pci_init(device_t dev)
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{
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u_long syscntl,devcntl,cardcntl;
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u_int32_t device_id = pci_get_devid(dev);
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char buf[128];
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int ti113x = (device_id == PCI_DEVICE_ID_PCIC_TI1130)
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|| (device_id == PCI_DEVICE_ID_PCIC_TI1131);
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syscntl = pci_read_config(dev, TI113X_PCI_SYSTEM_CONTROL, 4);
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devcntl = pci_read_config(dev, TI113X_PCI_DEVICE_CONTROL, 1);
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cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
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switch(ti113x){
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case 0 :
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strcpy(buf, "TI12XX PCI Config Reg: ");
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break;
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case 1 :
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strcpy(buf, "TI113X PCI Config Reg: ");
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/*
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* Default card control register setting is
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* PCI interrupt. The method of this code
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* switches PCI INT and ISA IRQ by bit 7 of
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* Bridge Control Register(Offset:0x3e,0x13e).
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* Takeshi Shibagaki(shiba@jp.freebsd.org)
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*/
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cardcntl |= TI113X_CARDCNTL_PCI_IREQ;
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cardcntl |= TI113X_CARDCNTL_PCI_CSC;
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pci_write_config(dev, TI113X_PCI_CARD_CONTROL, cardcntl, 1);
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cardcntl = pci_read_config(dev, TI113X_PCI_CARD_CONTROL, 1);
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if (syscntl & TI113X_SYSCNTL_CLKRUN_ENA){
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if (syscntl & TI113X_SYSCNTL_CLKRUN_SEL)
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strcat(buf, "[clkrun irq 12]");
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else
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strcat(buf, "[clkrun irq 10]");
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}
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break;
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}
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if (cardcntl & TI113X_CARDCNTL_RING_ENA)
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strcat(buf, "[ring enable]");
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if (cardcntl & TI113X_CARDCNTL_SPKR_ENA)
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strcat(buf, "[speaker enable]");
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if (syscntl & TI113X_SYSCNTL_PWRSAVINGS)
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strcat(buf, "[pwr save]");
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switch(devcntl & TI113X_DEVCNTL_INTR_MASK){
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case TI113X_DEVCNTL_INTR_ISA :
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strcat(buf, "[CSC parallel isa irq]");
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break;
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case TI113X_DEVCNTL_INTR_SERIAL :
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strcat(buf, "[CSC serial isa irq]");
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break;
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case TI113X_DEVCNTL_INTR_NONE :
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strcat(buf, "[pci only]");
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break;
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case TI12XX_DEVCNTL_INTR_ALLSERIAL :
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strcat(buf, "[FUNC pci int + CSC serial isa irq]");
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break;
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}
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device_printf(dev, "%s\n",buf);
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}
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static void
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generic_cardbus_attach(device_t dev)
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{
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u_int16_t brgcntl;
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u_int32_t iobase;
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int unit;
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unit = device_get_unit(dev);
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/* Output ISA IRQ indicated in ExCA register(0x03). */
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brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
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brgcntl |= CB_BCR_INT_EXCA;
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pci_write_config(dev, CB_PCI_BRIDGE_CTRL, brgcntl, 2);
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/* 16bit Legacy Mode Base Address */
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if (unit != 0)
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return;
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iobase = pci_read_config(dev, CB_PCI_LEGACY16_IOADDR, 2) &
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~CB_PCI_LEGACY16_IOENABLE;
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if (!iobase) {
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iobase = 0x3e0 | CB_PCI_LEGACY16_IOENABLE;
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pci_write_config(dev, CB_PCI_LEGACY16_IOADDR, iobase, 2);
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iobase = pci_read_config(dev, CB_PCI_LEGACY16_IOADDR, 2)
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& ~CB_PCI_LEGACY16_IOENABLE;
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}
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PRVERB((dev, "Legacy address set to %#x\n", iobase));
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return;
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}
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/*
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* Return the ID string for the controller if the vendor/product id
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* matches, NULL otherwise.
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*/
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static int
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pcic_pci_probe(device_t dev)
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{
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u_int32_t device_id;
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char *desc;
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device_id = pci_get_devid(dev);
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desc = NULL;
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switch (device_id) {
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case PCI_DEVICE_ID_PCIC_CLPD6832:
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desc = "Cirrus Logic PD6832 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1130:
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desc = "TI PCI-1130 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1131:
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desc = "TI PCI-1131 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1211:
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desc = "TI PCI-1211 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1220:
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desc = "TI PCI-1220 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1221:
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desc = "TI PCI-1221 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1225:
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desc = "TI PCI-1225 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1250:
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desc = "TI PCI-1250 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1251:
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desc = "TI PCI-1251 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1251B:
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desc = "TI PCI-1251B PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1410:
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desc = "TI PCI-1410 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1420:
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desc = "TI PCI-1420 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1450:
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desc = "TI PCI-1450 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1451:
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desc = "TI PCI-1451 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_TOSHIBA_TOPIC95:
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desc = "Toshiba ToPIC95 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_TOSHIBA_TOPIC97:
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desc = "Toshiba ToPIC97 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_RICOH_RL5C465:
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desc = "Ricoh RL5C465 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_RICOH_RL5C475:
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desc = "Ricoh RL5C475 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_RICOH_RL5C476:
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desc = "Ricoh RL5C476 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_RICOH_RL5C478:
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desc = "Ricoh RL5C478 PCI-CardBus Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_OZ6832:
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desc = "O2micro 6832 PCI-Cardbus Bridge";
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break;
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/* 16bit PC-card bridges */
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case PCI_DEVICE_ID_PCIC_CLPD6729:
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desc = "Cirrus Logic PD6729/6730 PC-Card Controller";
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break;
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case PCI_DEVICE_ID_PCIC_OZ6729:
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desc = "O2micro OZ6729 PC-Card Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_OZ6730:
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desc = "O2micro OZ6730 PC-Card Bridge";
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break;
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case PCI_DEVICE_ID_PCIC_TI1031:
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desc = "TI PCI-1031 PCI-PCMCIA Bridge";
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break;
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default:
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break;
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}
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if (desc == NULL)
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return (ENXIO);
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device_set_desc(dev, desc);
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return 0; /* exact match */
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}
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static void
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ricoh_init(device_t dev)
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{
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u_int16_t brgcntl;
|
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/*
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* Ricoh chips have a legacy bridge enable different than most
|
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* Code cribbed from NEWBUS's bridge code since I can't find a
|
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* datasheet for them that has register definitions.
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*/
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brgcntl = pci_read_config(dev, CB_PCI_BRIDGE_CTRL, 2);
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brgcntl |= CB_BCR_RL_3E0_EN;
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brgcntl &= ~CB_BCR_RL_3E2_EN;
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pci_write_config(dev, CLPD6832_BRIDGE_CONTROL, brgcntl, 4);
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}
|
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/*
|
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* General PCI based card dispatch routine. Right now
|
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* it only understands the Ricoh, CL-PD6832 and TI parts. It does
|
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* try to do generic things with other parts.
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*/
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static int
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pcic_pci_attach(device_t dev)
|
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{
|
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u_int32_t device_id = pci_get_devid(dev);
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u_long command;
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/* Init. CardBus/PC-card controllers as 16-bit PC-card controllers */
|
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|
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/* Place any per "slot" initialization here */
|
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|
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/*
|
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* In sys/pci/pcireg.h, PCIR_COMMAND must be separated
|
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* PCI_COMMAND_REG(0x04) and PCI_STATUS_REG(0x06).
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* Takeshi Shibagaki(shiba@jp.freebsd.org).
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*/
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command = pci_read_config(dev, PCIR_COMMAND, 4);
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command |= PCIM_CMD_PORTEN | PCIM_CMD_MEMEN;
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pci_write_config(dev, PCIR_COMMAND, command, 4);
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switch (device_id) {
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case PCI_DEVICE_ID_RICOH_RL5C465:
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case PCI_DEVICE_ID_RICOH_RL5C466:
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ricoh_init(dev);
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generic_cardbus_attach(dev);
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break;
|
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case PCI_DEVICE_ID_PCIC_TI1130:
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case PCI_DEVICE_ID_PCIC_TI1131:
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case PCI_DEVICE_ID_PCIC_TI1211:
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case PCI_DEVICE_ID_PCIC_TI1220:
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case PCI_DEVICE_ID_PCIC_TI1221:
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case PCI_DEVICE_ID_PCIC_TI1225:
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case PCI_DEVICE_ID_PCIC_TI1250:
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case PCI_DEVICE_ID_PCIC_TI1251:
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case PCI_DEVICE_ID_PCIC_TI1251B:
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case PCI_DEVICE_ID_PCIC_TI1410:
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case PCI_DEVICE_ID_PCIC_TI1420:
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case PCI_DEVICE_ID_PCIC_TI1450:
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case PCI_DEVICE_ID_PCIC_TI1451:
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ti1xxx_pci_init(dev);
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/* FALLTHROUGH */
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default:
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generic_cardbus_attach(dev);
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break;
|
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case PCI_DEVICE_ID_PCIC_CLPD6832:
|
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case PCI_DEVICE_ID_PCIC_TI1031: /* 1031 is like 6832 */
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pd6832_legacy_init(dev);
|
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break;
|
||||
}
|
||||
|
||||
if (bootverbose) {
|
||||
int i, j;
|
||||
u_char *p;
|
||||
u_long *pl;
|
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|
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printf("PCI Config space:\n");
|
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for (j = 0; j < 0x98; j += 16) {
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printf("%02x: ", j);
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||||
for (i = 0; i < 16; i += 4)
|
||||
printf(" %08x", pci_read_config(dev, i+j, 4));
|
||||
printf("\n");
|
||||
}
|
||||
p = (u_char *)pmap_mapdev(pci_read_config(dev, 0x10, 4),
|
||||
0x1000);
|
||||
pl = (u_long *)p;
|
||||
printf("Cardbus Socket registers:\n");
|
||||
printf("00: ");
|
||||
for (i = 0; i < 4; i += 1)
|
||||
printf(" %08lx:", pl[i]);
|
||||
printf("\n10: ");
|
||||
for (i = 4; i < 8; i += 1)
|
||||
printf(" %08lx:", pl[i]);
|
||||
printf("\nExCa registers:\n");
|
||||
for (i = 0; i < 0x40; i += 16)
|
||||
printf("%02x: %16D\n", i, p + 0x800 + i, " ");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
pcic_pci_detach(device_t dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static device_method_t pcic_pci_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, pcic_pci_probe),
|
||||
DEVMETHOD(device_attach, pcic_pci_attach),
|
||||
DEVMETHOD(device_detach, pcic_pci_detach),
|
||||
DEVMETHOD(device_suspend, bus_generic_suspend),
|
||||
DEVMETHOD(device_resume, bus_generic_resume),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
|
||||
{0, 0}
|
||||
};
|
||||
|
||||
static driver_t pcic_pci_driver = {
|
||||
"pcic-pci",
|
||||
pcic_pci_methods,
|
||||
0 /* no softc */
|
||||
};
|
||||
|
||||
static devclass_t pcic_pci_devclass;
|
||||
|
||||
DRIVER_MODULE(pcic_pci, pci, pcic_pci_driver, pcic_pci_devclass, 0, 0);
|
||||
164
sys/pci/pcic_p.h
164
sys/pci/pcic_p.h
@ -1,164 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 1997 Ted Faber
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice immediately at the beginning of the file, without modification,
|
||||
* this list of conditions, and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. Absolutely no warranty of function or purpose is made by the author
|
||||
* Ted Faber.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
|
||||
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/* PCI/CardBus Device IDs */
|
||||
#define PCI_DEVICE_ID_PCIC_OZ6729 0x67291217ul
|
||||
#define PCI_DEVICE_ID_PCIC_OZ6730 0x673A1217ul
|
||||
#define PCI_DEVICE_ID_PCIC_OZ6832 0x68321217ul
|
||||
#define PCI_DEVICE_ID_PCIC_CLPD6729 0x11001013ul
|
||||
#define PCI_DEVICE_ID_PCIC_CLPD6832 0x11101013ul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1031 0xac13104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1130 0xac12104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1131 0xac15104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1211 0xac1e104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1220 0xac17104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1221 0xac19104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1225 0xac1c104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1250 0xac16104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1251 0xac1d104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1251B 0xac1f104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1410 0xac50104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1420 0xac51104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1450 0xac1b104cul
|
||||
#define PCI_DEVICE_ID_PCIC_TI1451 0xac52104cul
|
||||
#define PCI_DEVICE_ID_TOSHIBA_TOPIC95 0x060a1179ul
|
||||
#define PCI_DEVICE_ID_TOSHIBA_TOPIC97 0x060f1179ul
|
||||
#define PCI_DEVICE_ID_RICOH_RL5C465 0x04651180ul
|
||||
#define PCI_DEVICE_ID_RICOH_RL5C466 0x04661180ul
|
||||
#define PCI_DEVICE_ID_RICOH_RL5C475 0x04751180ul
|
||||
#define PCI_DEVICE_ID_RICOH_RL5C476 0x04761180ul
|
||||
#define PCI_DEVICE_ID_RICOH_RL5C478 0x04781180ul
|
||||
|
||||
/* CL-PD6832 CardBus defines */
|
||||
#define CLPD6832_IO_BASE0 0x002c
|
||||
#define CLPD6832_IO_LIMIT0 0x0030
|
||||
#define CLPD6832_IO_BASE1 0x0034
|
||||
#define CLPD6832_IO_LIMIT1 0x0038
|
||||
#define CLPD6832_BRIDGE_CONTROL 0x003c
|
||||
#define CLPD6832_LEGACY_16BIT_IOADDR 0x0044
|
||||
#define CLPD6832_LEGACY_16BIT_IOENABLE 0x0001
|
||||
#define CLPD6832_SOCKET 0x004c
|
||||
|
||||
/* Configuration constants */
|
||||
#define CLPD6832_BCR_MGMT_IRQ_ENA 0x08000000
|
||||
#define CLPD6832_BCR_ISA_IRQ 0x00800000
|
||||
#define CLPD6832_COMMAND_DEFAULTS 0x00000045
|
||||
#define CLPD6832_NUM_REGS 2
|
||||
|
||||
/* End of CL-PD6832 defines */
|
||||
/* Texas Instruments PCI-1130/1131 CardBus Controller */
|
||||
#define TI113X_PCI_SYSTEM_CONTROL 0x80 /* System Control */
|
||||
#define TI113X_PCI_RETRY_STATUS 0x90 /* Retry Status */
|
||||
#define TI113X_PCI_CARD_CONTROL 0x91 /* Card Control */
|
||||
#define TI113X_PCI_DEVICE_CONTROL 0x92 /* Device Control */
|
||||
#define TI113X_PCI_BUFFER_CONTROL 0x93 /* Buffer Control */
|
||||
#define TI113X_PCI_SOCKET_DMA0 0x94 /* Socket DMA Register 0 */
|
||||
#define TI113X_PCI_SOCKET_DMA1 0x98 /* Socket DMA Register 1 */
|
||||
|
||||
/* Card control register (TI113X_SYSTEM_CONTROL == 0x80) */
|
||||
#define TI113X_SYSCNTL_INTRTIE 0x20000000u
|
||||
#define TI113X_SYSCNTL_SMIENB 0x00800000u
|
||||
#define TI113X_SYSCNTL_VCC_PROTECT 0x00200000u
|
||||
#define TI113X_SYSCNTL_CLKRUN_SEL 0x00000080u
|
||||
#define TI113X_SYSCNTL_PWRSAVINGS 0x00000040u
|
||||
#define TI113X_SYSCNTL_KEEP_CLK 0x00000002u
|
||||
#define TI113X_SYSCNTL_CLKRUN_ENA 0x00000001u
|
||||
|
||||
/* Card control register (TI113X_CARD_CONTROL == 0x91) */
|
||||
#define TI113X_CARDCNTL_RING_ENA 0x80u
|
||||
#define TI113X_CARDCNTL_ZOOM_VIDEO 0x40u
|
||||
#define TI113X_CARDCNTL_PCI_IRQ_ENA 0x20u
|
||||
#define TI113X_CARDCNTL_PCI_IREQ 0x10u
|
||||
#define TI113X_CARDCNTL_PCI_CSC 0x08u
|
||||
#define TI113X_CARDCNTL_MASK (TI113X_CARDCNTL_PCI_IRQ_ENA | TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
|
||||
#define TI113X_FUNC0_VALID TI113X_CARDCNTL_MASK
|
||||
#define TI113X_FUNC1_VALID (TI113X_CARDCNTL_PCI_IREQ | TI113X_CARDCNTL_PCI_CSC)
|
||||
/* Reserved bit 0x04u */
|
||||
#define TI113X_CARDCNTL_SPKR_ENA 0x02u
|
||||
#define TI113X_CARDCNTL_INT 0x01u
|
||||
|
||||
/* Device control register (TI113X_DEVICE_CONTROL == 0x92) */
|
||||
#define TI113X_DEVCNTL_5V_SOCKET 0x40u
|
||||
#define TI113X_DEVCNTL_3V_SOCKET 0x20u
|
||||
#define TI113X_DEVCNTL_INTR_MASK 0x06u
|
||||
#define TI113X_DEVCNTL_INTR_NONE 0x00u
|
||||
#define TI113X_DEVCNTL_INTR_ISA 0x02u
|
||||
#define TI113X_DEVCNTL_INTR_SERIAL 0x04u
|
||||
/* TI12XX specific code */
|
||||
#define TI12XX_DEVCNTL_INTR_ALLSERIAL 0x06u
|
||||
/* Texas Instruments PCI-1130/1131 CardBus Controller */
|
||||
#define TI113X_ExCA_IO_OFFSET0 0x36 /* Offset of I/O window */
|
||||
#define TI113X_ExCA_IO_OFFSET1 0x38 /* Offset of I/O window */
|
||||
#define TI113X_ExCA_MEM_WINDOW_PAGE 0x3C /* Memory Window Page */
|
||||
|
||||
/* sanpei */
|
||||
|
||||
/* For Bridge Control register (CB_PCI_BRIDGE_CTRL) */
|
||||
#define CB_BCR_MASTER_ABORT 0x0020
|
||||
#define CB_BCR_CB_RESET 0x0040
|
||||
#define CB_BCR_INT_EXCA 0x0080
|
||||
#define CB_BCR_WRITE_POST_EN 0x0400
|
||||
/* additional bits for Ricoh's cardbus products */
|
||||
#define CB_BCR_RL_3E0_EN 0x0800
|
||||
#define CB_BCR_RL_3E2_EN 0x1000
|
||||
|
||||
/* PCI Configuration Registers (common) */
|
||||
#define CB_PCI_VENDOR_ID 0x00 /* vendor ID */
|
||||
#define CB_PCI_DEVICE_ID 0x02 /* device ID */
|
||||
#define CB_PCI_COMMAND 0x04 /* PCI command */
|
||||
#define CB_PCI_STATUS 0x06 /* PCI status */
|
||||
#define CB_PCI_REVISION_ID 0x08 /* PCI revision ID */
|
||||
#define CB_PCI_CLASS 0x09 /* PCI class code */
|
||||
#define CB_PCI_CACHE_LINE_SIZE 0x0c /* Cache line size */
|
||||
#define CB_PCI_LATENCY 0x0d /* PCI latency timer */
|
||||
#define CB_PCI_HEADER_TYPE 0x0e /* PCI header type */
|
||||
#define CB_PCI_BIST 0x0f /* Built-in self test */
|
||||
#define CB_PCI_SOCKET_BASE 0x10 /* Socket/ExCA base address reg. */
|
||||
#define CB_PCI_CB_STATUS 0x16 /* CardBus Status */
|
||||
#define CB_PCI_PCI_BUS_NUM 0x18 /* PCI bus number */
|
||||
#define CB_PCI_CB_BUS_NUM 0x19 /* CardBus bus number */
|
||||
#define CB_PCI_CB_SUB_BUS_NUM 0x1A /* Subordinate CardBus bus number */
|
||||
#define CB_PCI_CB_LATENCY 0x1A /* CardBus latency timer */
|
||||
#define CB_PCI_MEMBASE0 0x1C /* Memory base register 0 */
|
||||
#define CB_PCI_MEMLIMIT0 0x20 /* Memory limit register 0 */
|
||||
#define CB_PCI_MEMBASE1 0x24 /* Memory base register 1 */
|
||||
#define CB_PCI_MEMLIMIT1 0x28 /* Memory limit register 1 */
|
||||
#define CB_PCI_IOBASE0 0x2C /* I/O base register 0 */
|
||||
#define CB_PCI_IOLIMIT0 0x30 /* I/O limit register 0 */
|
||||
#define CB_PCI_IOBASE1 0x34 /* I/O base register 1 */
|
||||
#define CB_PCI_IOLIMIT1 0x38 /* I/O limit register 1 */
|
||||
#define CB_PCI_INT_LINE 0x3C /* Interrupt Line */
|
||||
#define CB_PCI_INT_PIN 0x3D /* Interrupt Pin */
|
||||
#define CB_PCI_BRIDGE_CTRL 0x3E /* Bridge Control */
|
||||
#define CB_PCI_SUBSYS_VENDOR_ID 0x40 /* Subsystem Vendor ID */
|
||||
#define CB_PCI_SUBSYS_ID 0x42 /* Subsystem ID */
|
||||
#define CB_PCI_LEGACY16_IOADDR 0x44 /* Legacy 16bit I/O address */
|
||||
#define CB_PCI_LEGACY16_IOENABLE 0x01 /* Enable Legacy 16bit I/O address */
|
||||
Loading…
Reference in New Issue
Block a user